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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-13 13:57:10 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-13 13:57:10 +0200 |
| commit | 7c1135fc5356609e4de50a6b93309446ac15461f (patch) | |
| tree | a6057e69b9e645c6a75b42a703b0de9d0959ac48 /arch/riscv/include/asm/cache.h | |
| parent | 2562e8e4968454c3c90659976e78ea6a8981dd2a (diff) | |
| parent | d2c655d34cb204c5ba56891b4e597d53330de4d8 (diff) | |
| download | barebox-7c1135fc5356609e4de50a6b93309446ac15461f.tar.gz barebox-7c1135fc5356609e4de50a6b93309446ac15461f.tar.xz | |
Merge branch 'for-next/riscv'
Diffstat (limited to 'arch/riscv/include/asm/cache.h')
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9a0b9326b2..c787f89001 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -6,10 +6,29 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#include <asm/vendorid_list.h> + +static inline void thead_local_flush_icache_all(void) +{ + /* + * According [1] "13.3 Example of cache settings" + * [1]: https://github.com/T-head-Semi/openc906/blob/main/ \ + * doc/openc906%20datasheet.pd + */ + __asm__ volatile (".long 0x0100000b" ::: "memory"); /* th.icache.iall */ + __asm__ volatile (".long 0x01b0000b" ::: "memory"); /* th.sync.is */ +} + static inline void local_flush_icache_all(void) { -#ifdef HAS_CACHE - asm volatile ("fence.i" ::: "memory"); +#ifdef CONFIG_HAS_CACHE + switch(riscv_vendor_id()) { + case THEAD_VENDOR_ID: + thead_local_flush_icache_all(); + break; + default: + __asm__ volatile ("fence.i" ::: "memory"); + } #endif } |