diff options
| author | Marco Felsch <m.felsch@pengutronix.de> | 2022-10-05 13:12:08 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-07 10:29:53 +0200 |
| commit | 16d4bd3330f796be0ab5c52bbd470c99d00b25e6 (patch) | |
| tree | 70c415915e6c72b6f0b0cbd77c227e2a373aa691 /arch/riscv | |
| parent | ac33f77ac47ffb2c1de4029ae1083d6f4e421e32 (diff) | |
| download | barebox-16d4bd3330f796be0ab5c52bbd470c99d00b25e6.tar.gz barebox-16d4bd3330f796be0ab5c52bbd470c99d00b25e6.tar.xz | |
RISC-V: cache: fix local_flush_icache_all enabling
Commit fe181ffda9 ("RISC-V: support incoherent I-Cache") added the
support to handle non-coherent caches and introduced the HAS_CACHE
Kconfig symbol. The symbol must be used with CONFIG_ prefixed since this
is the final Kconfig symbol which can be used within the code.
Fixes: fe181ffda9 ("RISC-V: support incoherent I-Cache")
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20221005111214.148844-1-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9a0b9326b2..6d69ed49bd 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ static inline void local_flush_icache_all(void) { -#ifdef HAS_CACHE +#ifdef CONFIG_HAS_CACHE asm volatile ("fence.i" ::: "memory"); #endif } |