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| author | Ahmad Fatoum <ahmad@a3f.at> | 2021-12-03 07:33:40 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-12-13 23:13:13 +0100 |
| commit | 35dd3095cddde1175356ebfa6b1fe500d677853d (patch) | |
| tree | cfbcea237e7ba3fbe00b94da430fe4b1194415d9 /arch/riscv | |
| parent | 3a726d01792bdd03eb16b74f1565ce30995abb75 (diff) | |
| download | barebox-35dd3095cddde1175356ebfa6b1fe500d677853d.tar.gz barebox-35dd3095cddde1175356ebfa6b1fe500d677853d.tar.xz | |
RISC-V: interrupts: fix Zifencei emulation on rv64
Zifencei emulaton was added for bare bones 32-bit targets, but the code
is there on 64-bit too. The instruction skip at the end of the function
skips 4 bytes, the size of an instruction on both rv32 and rv64. The
instruction decoder however assumes instructions are size(long) bytes,
which is 8 > 4 on rv64. Fix this.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20211203063340.1026512-1-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/interrupts.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/interrupts.c b/arch/riscv/cpu/interrupts.c index 0e8951b619..1f2d7b8857 100644 --- a/arch/riscv/cpu/interrupts.c +++ b/arch/riscv/cpu/interrupts.c @@ -122,7 +122,7 @@ unsigned long handle_trap(struct pt_regs *regs) goto skip; if (regs->cause == 2) { /* illegal instruction */ - switch(*(unsigned long *)regs->epc) { + switch(*(u32 *)regs->epc) { case 0x0000100f: /* fence.i */ goto skip; default: |