diff options
| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2024-01-10 17:01:06 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-01-11 15:11:02 +0100 |
| commit | 4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f (patch) | |
| tree | f425a204d1978a7205b06f49d229108dfa7c0cc9 /arch/riscv | |
| parent | 62753977d4231a160e4fb3bd3fe585e151792eb4 (diff) | |
| download | barebox-4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f.tar.gz barebox-4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f.tar.xz | |
RISC-V: StarFive: J7100: set /soc/dma-noncoherent
With upcoming changes, cache handling will be skipped on RISC-V, because
arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA
masters though, so note that in the DT.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240110160112.4134162-5-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig.socs | 1 | ||||
| -rw-r--r-- | arch/riscv/dts/jh7100.dtsi | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 56ba5ecf58..cef9cd5230 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -88,6 +88,7 @@ config SOC_STARFIVE_JH7100 bool select SOC_STARFIVE_JH71XX select SIFIVE_L2 + select OF_DMA_COHERENCY help Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent with respect to DMA masters like GMAC and DW MMC controller. diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi index e3990582af..b11801553b 100644 --- a/arch/riscv/dts/jh7100.dtsi +++ b/arch/riscv/dts/jh7100.dtsi @@ -212,6 +212,7 @@ #clock-cells = <1>; compatible = "simple-bus"; ranges; + dma-noncoherent; intram0: sram@18000000 { compatible = "mmio-sram"; |