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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-06-19 06:50:38 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-24 08:53:47 +0200 |
| commit | 9af34bc9603e70eb328b144d63f14ca1ef0d8cd5 (patch) | |
| tree | 017de90868af50826a7a1866a646543d09889cfc /arch/riscv | |
| parent | fe181ffda91593e6ba975f8d28cb4e5abb5b0bc4 (diff) | |
| download | barebox-9af34bc9603e70eb328b144d63f14ca1ef0d8cd5.tar.gz barebox-9af34bc9603e70eb328b144d63f14ca1ef0d8cd5.tar.xz | |
drivers: soc: sifive: add basic L2 cache controller driver
SiFive SoCs are cache coherent with respect to other DMA masters,
so there is no need to explicitly flush cache lines.
Incoming StarFive SoC uses SiFive CPU and L2 cache controller,
but is cache-incoherent and thus needs the maintenance for DMA.
Add a basic driver that exports the cache flush function for
SoC-specific drivers to use.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-13-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig.socs | 5 | ||||
| -rw-r--r-- | arch/riscv/include/asm/barrier.h | 27 |
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec2315d4e..b4fdfd9741 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -64,5 +64,10 @@ config SOC_STARFIVE_JH7100 endif +comment "CPU features" + +config SIFIVE_L2 + bool "SiFive L2 cache controller" + depends on CPU_SIFIVE endmenu diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h new file mode 100644 index 0000000000..eff529307a --- /dev/null +++ b/arch/riscv/include/asm/barrier.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Based on arch/arm/include/asm/barrier.h + * + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2013 Regents of the University of California + * Copyright (C) 2017 SiFive + */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#ifndef __ASSEMBLY__ + +#define nop() __asm__ __volatile__ ("nop") + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BARRIER_H */ |