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authorSascha Hauer <s.hauer@pengutronix.de>2016-03-30 12:00:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-04-01 14:06:11 +0200
commit25ab9fcaf862459650ae052e20527331d3ceefb9 (patch)
treed9656deacbe05fe29d1a193f7dc1f8a5235f1c91 /arch
parent1ff0ffbfd9c46aa40b2e0f9bb00b3f367e9fbfe8 (diff)
downloadbarebox-25ab9fcaf862459650ae052e20527331d3ceefb9.tar.gz
barebox-25ab9fcaf862459650ae052e20527331d3ceefb9.tar.xz
ARM: i.MX6: esdctl: Fix CS0_end for 4GiB/cs
On i.MX6 a single chipselect can have 4GiB. In this case the calculation for CS0_end overflows the 7 bit field. Clamp it to 127, the maximum supported value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/imx6-mmdc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 146df573e4..8f661e3dfe 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -1199,7 +1199,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trtp = twtr;
- cs0_end = 4 * sysinfo->cs_density - 1 + 8;
+ cs0_end = min(4 * sysinfo->cs_density - 1 + 8, 127);
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);