diff options
| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-08-05 14:54:10 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-08 14:32:08 +0200 |
| commit | cd5fc818a2d79d0a477b57dbd64f36dc876f4abb (patch) | |
| tree | 36d6df7d0ac6fa7811c5594d227631083f3598bd /drivers/ddr | |
| parent | 6e48ef8732de8bd6fc8df69a5c87100ebf3ba8d1 (diff) | |
| download | barebox-cd5fc818a2d79d0a477b57dbd64f36dc876f4abb.tar.gz barebox-cd5fc818a2d79d0a477b57dbd64f36dc876f4abb.tar.xz | |
ARM: i.MX8M: remove struct dram_timing_info::dram_type again
We had added dram_timing_info::dram_type to allow the same build to
support both DDR4 and LPDDR4. Since then imx8m_ddr_init has gained a new
member describing the DRAM type, so we can just use that instead of the
struct member. The benefit of that is that we can keep the DRAM timing
code resulting from the generator unchanged.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20220805125413.1046239-7-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 5 | ||||
| -rw-r--r-- | drivers/ddr/imx8m/ddrphy_train.c | 6 |
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index f046ea52df..18969ddb53 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -50,10 +50,11 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) #define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 int imx8m_ddr_init(struct dram_timing_info *dram_timing, - enum ddrc_type ddrc_type) + unsigned type) { unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; unsigned int tmp, initial_drate, target_freq; + enum ddrc_type ddrc_type = get_ddrc_type(type); int ret; pr_debug("start DRAM init\n"); @@ -134,7 +135,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, */ pr_debug("ddrphy config start\n"); - ret = ddr_cfg_phy(dram_timing, ddrc_type); + ret = ddr_cfg_phy(dram_timing, type); if (ret) return ret; diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index f739c65107..e9d35afdfb 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -93,8 +93,10 @@ void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type) DDRC_PHY_DMEM, dmem, dsize); } -int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type ddrc_type) +int ddr_cfg_phy(struct dram_timing_info *dram_timing, unsigned type) { + enum ddrc_type ddrc_type = get_ddrc_type(type); + enum dram_type dram_type = get_dram_type(type); struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; unsigned int num; @@ -120,7 +122,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type ddrc_type) /* load the dram training firmware image */ dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddr_load_train_code(dram_timing->dram_type, fsp_msg->fw_type); + ddr_load_train_code(dram_type, fsp_msg->fw_type); /* load the frequency set point message block parameter */ dram_cfg = fsp_msg->fsp_cfg; |