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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:18:47 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:47 +0100 |
| commit | f810e554d692cee7250b072073b72a587ed026c2 (patch) | |
| tree | 633509ce0e4a81ec4a97f7b58355bfd40962dc64 /drivers | |
| parent | 6d0393e12bcda21465c514e6a34947bfd7c8727d (diff) | |
| download | barebox-f810e554d692cee7250b072073b72a587ed026c2.tar.gz barebox-f810e554d692cee7250b072073b72a587ed026c2.tar.xz | |
PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces
Port of a Linux commit 7e00dfd0fbbb2fc276592613f76ded0b9a139a04
The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.
Make the signature of the override functions the same as the default
accessors. This makes the default dw_pcie_readl_rc() and the corresponding
override more structurally similar: both will compute the final register
address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed
the address and passed it to the override.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/pcie-designware.c | 4 | ||||
| -rw-r--r-- | drivers/pci/pcie-designware.h | 5 |
2 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index fd529c114a..4595167c47 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -145,7 +145,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) { if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + reg); + return pp->ops->readl_rc(pp, reg); return readl(pp->dbi_base + reg); } @@ -153,7 +153,7 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) { if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + reg); + pp->ops->writel_rc(pp, val, reg); else writel(val, pp->dbi_base + reg); } diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h index 62f04e69b1..b7ce737184 100644 --- a/drivers/pci/pcie-designware.h +++ b/drivers/pci/pcie-designware.h @@ -47,9 +47,8 @@ struct pcie_port { }; struct pcie_host_ops { - u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base); - void (*writel_rc)(struct pcie_port *pp, - u32 val, void __iomem *dbi_base); + u32 (*readl_rc)(struct pcie_port *pp, u32 reg); + void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, |