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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-05-06 08:56:43 +0200 |
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| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-05-06 08:56:43 +0200 |
| commit | 461f8cfc7ea788428240271818363333ceff5c4c (patch) | |
| tree | a3d6e3737c203ea29f8db2a6ddaadc326247376c /dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt | |
| parent | 6345d37ae50c3ac8dd0e6176bc846fe211cbddd4 (diff) | |
| download | barebox-461f8cfc7ea788428240271818363333ceff5c4c.tar.gz barebox-461f8cfc7ea788428240271818363333ceff5c4c.tar.xz | |
dts: update to v4.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt')
| -rw-r--r-- | dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt new file mode 100644 index 0000000000..44aa3c451c --- /dev/null +++ b/dts/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt @@ -0,0 +1,14 @@ +Freescale Vybrid Miscellaneous System Control - CPU Configuration + +The MSCM IP contains multiple sub modules, this binding describes the first +block of registers which contains CPU configuration information. + +Required properties: +- compatible: "fsl,vf610-mscm-cpucfg", "syscon" +- reg: the register range of the MSCM CPU configuration registers + +Example: + mscm_cpucfg: cpucfg@40001000 { + compatible = "fsl,vf610-mscm-cpucfg", "syscon"; + reg = <0x40001000 0x800>; + } |