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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
| commit | 2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch) | |
| tree | 468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/Bindings/arm/l2c2x0.yaml | |
| parent | 785f926d4527184194b6424bc39ce367e2cea7d8 (diff) | |
| download | barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz | |
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/l2c2x0.yaml')
| -rw-r--r-- | dts/Bindings/arm/l2c2x0.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/dts/Bindings/arm/l2c2x0.yaml b/dts/Bindings/arm/l2c2x0.yaml index bfc5c18556..913a8cd8b2 100644 --- a/dts/Bindings/arm/l2c2x0.yaml +++ b/dts/Bindings/arm/l2c2x0.yaml @@ -176,6 +176,10 @@ properties: description: disable parity checking on the L2 cache (L220 or PL310). type: boolean + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that |