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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 09:15:32 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 10:41:39 +0200 |
commit | e54923b76e345080b73f3ae7f508657e5c63a9eb (patch) | |
tree | 8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts/Bindings/arm/mediatek/mediatek,infracfg.txt | |
parent | d4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff) | |
download | barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz |
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/mediatek/mediatek,infracfg.txt')
-rw-r--r-- | dts/Bindings/arm/mediatek/mediatek,infracfg.txt | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt deleted file mode 100644 index f66bd72057..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek infracfg controller -============================ - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt7986-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; |