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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 09:15:32 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 10:41:39 +0200 |
commit | e54923b76e345080b73f3ae7f508657e5c63a9eb (patch) | |
tree | 8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml | |
parent | d4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff) | |
download | barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz |
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml')
-rw-r--r-- | dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml new file mode 100644 index 0000000000..0886e2e335 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek System Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. + The mcusys provides mux control to select the clock source in AP MCU. + The device nodes also provide the system control capacity for configuration. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-mcusys + - mediatek,mt8186-topckgen + - mediatek,mt8186-infracfg_ao + - mediatek,mt8186-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; |