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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-14 09:05:53 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-18 08:32:25 +0100 |
commit | 81ce4a7dec8ba066c73692e10634091b14c1e494 (patch) | |
tree | d61574b25fda47711e3efab57c7a5739de477565 /dts/Bindings/clock/fsl,plldig.yaml | |
parent | 84b7f86bef670f6751d67131738555fa53ca3f6b (diff) | |
download | barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.gz barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.xz |
dts: update to v5.6-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock/fsl,plldig.yaml')
-rw-r--r-- | dts/Bindings/clock/fsl,plldig.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/dts/Bindings/clock/fsl,plldig.yaml b/dts/Bindings/clock/fsl,plldig.yaml new file mode 100644 index 0000000000..c8350030b3 --- /dev/null +++ b/dts/Bindings/clock/fsl,plldig.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + fsl,vco-hz: + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... |