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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-29 14:38:07 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-29 14:38:07 +0200 |
| commit | d9a15385467936649b6c2cfeb7ab377002ddce0f (patch) | |
| tree | 39175107fc884a29fbba83f47d104f493833fe19 /dts/Bindings/clock/renesas,cpg-mssr.txt | |
| parent | bfe946c9593513b0ad1b440bcd997b263487b945 (diff) | |
| download | barebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.gz barebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.xz | |
dts: update to v4.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock/renesas,cpg-mssr.txt')
| -rw-r--r-- | dts/Bindings/clock/renesas,cpg-mssr.txt | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt index fefb802302..394d725ac7 100644 --- a/dts/Bindings/clock/renesas,cpg-mssr.txt +++ b/dts/Bindings/clock/renesas,cpg-mssr.txt @@ -13,7 +13,8 @@ They provide the following functionalities: Required Properties: - compatible: Must be one of: - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC + - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) + - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) - reg: Base address and length of the memory resource used by the CPG/MSSR block @@ -21,8 +22,8 @@ Required Properties: - clocks: References to external parent clocks, one entry for each entry in clock-names - clock-names: List of external parent clock names. Valid names are: - - "extal" (r8a7795) - - "extalr" (r8a7795) + - "extal" (r8a7795, r8a7796) + - "extalr" (r8a7795, r8a7796) - #clock-cells: Must be 2 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" |