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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:33:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:39 +0100 |
commit | a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch) | |
tree | 69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/Bindings/clock/renesas,rz-cpg-clocks.txt | |
parent | 48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff) | |
download | barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.xz |
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/clock/renesas,rz-cpg-clocks.txt')
-rw-r--r-- | dts/Bindings/clock/renesas,rz-cpg-clocks.txt | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt index b0f7ddb8cd..bb51a33a1f 100644 --- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt +++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt @@ -2,6 +2,8 @@ The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable CPU and GPU clocks, and several fixed ratio dividers. +The CPG also provides a Clock Domain for SoC devices, in combination with the +CPG Module Stop (MSTP) Clocks. Required Properties: @@ -14,10 +16,18 @@ Required Properties: - #clock-cells: Must be 1 - clock-output-names: The names of the clocks. Supported clocks are "pll", "i", and "g" + - #power-domain-cells: Must be 0 +SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed +through an MSTP clock should refer to the CPG device node in their +"power-domains" property, as documented by the generic PM domain bindings in +Documentation/devicetree/bindings/power/power_domain.txt. -Example -------- + +Examples +-------- + + - CPG device node: cpg_clocks: cpg_clocks@fcfe0000 { #clock-cells = <1>; @@ -26,4 +36,19 @@ Example reg = <0xfcfe0000 0x18>; clocks = <&extal_clk>, <&usb_x1_clk>; clock-output-names = "pll", "i", "g"; + #power-domain-cells = <0>; + }; + + + - CPG/MSTP Clock Domain member device node: + + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; |