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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:33:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:39 +0100 |
commit | a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch) | |
tree | 69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/Bindings/cpufreq | |
parent | 48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff) | |
download | barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.xz |
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/cpufreq')
-rw-r--r-- | dts/Bindings/cpufreq/tegra124-cpufreq.txt | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/dts/Bindings/cpufreq/tegra124-cpufreq.txt b/dts/Bindings/cpufreq/tegra124-cpufreq.txt new file mode 100644 index 0000000000..b1669fbfb7 --- /dev/null +++ b/dts/Bindings/cpufreq/tegra124-cpufreq.txt @@ -0,0 +1,44 @@ +Tegra124 CPU frequency scaling driver bindings +---------------------------------------------- + +Both required and optional properties listed below must be defined +under node /cpus/cpu@0. + +Required properties: +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - cpu_g: Clock mux for the fast CPU cluster. + - cpu_lp: Clock mux for the low-power CPU cluster. + - pll_x: Fast PLL clocksource. + - pll_p: Auxiliary PLL used during fast PLL rate changes. + - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. +- vdd-cpu-supply: Regulator for CPU voltage + +Optional properties: +- clock-latency: Specify the possible maximum transition latency for clock, + in unit of nanoseconds. + +Example: +-------- +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; + vdd-cpu-supply: <&vdd_cpu>; + }; + + <...> +}; |