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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 08:14:56 +0200 |
| commit | 6b85c20d46812bdbc062b863261c3e5100e30556 (patch) | |
| tree | e067c9889eaf55d5e793b05a14000276f2669e9f /dts/Bindings/crypto | |
| parent | 9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff) | |
| download | barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz barebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.xz | |
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/crypto')
| -rw-r--r-- | dts/Bindings/crypto/arm-cryptocell.txt | 3 | ||||
| -rw-r--r-- | dts/Bindings/crypto/fsl-sec4.txt | 17 | ||||
| -rw-r--r-- | dts/Bindings/crypto/inside-secure-safexcel.txt | 6 |
3 files changed, 24 insertions, 2 deletions
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt index cec8d5d74e..c2598ab27f 100644 --- a/dts/Bindings/crypto/arm-cryptocell.txt +++ b/dts/Bindings/crypto/arm-cryptocell.txt @@ -1,7 +1,8 @@ Arm TrustZone CryptoCell cryptographic engine Required properties: -- compatible: Should be "arm,cryptocell-712-ree". +- compatible: Should be one of: "arm,cryptocell-712-ree", + "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree". - reg: Base physical address of the engine and length of memory mapped region. - interrupts: Interrupt number for the device. diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt index 76aec8a372..3c1f3a229e 100644 --- a/dts/Bindings/crypto/fsl-sec4.txt +++ b/dts/Bindings/crypto/fsl-sec4.txt @@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: <u32> Definition: LP register offset. default it is 0x34. + - clocks + Usage: optional, required if SNVS LP RTC requires explicit + enablement of clocks + Value type: <prop_encoded-array> + Definition: a clock specifier describing the clock required for + enabling and disabling SNVS LP RTC. + + - clock-names + Usage: optional, required if SNVS LP RTC requires explicit + enablement of clocks + Value type: <string> + Definition: clock name string should be "snvs-rtc". + EXAMPLE sec_mon_rtc_lp@1 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; interrupts = <93 2>; regmap = <&snvs>; offset = <0x34>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; ===================================================================== @@ -543,6 +558,8 @@ FULL EXAMPLE regmap = <&sec_mon>; offset = <0x34>; interrupts = <93 2>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; snvs-pwrkey@020cc000 { diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt index 30c3ce6b50..5dba55cdfa 100644 --- a/dts/Bindings/crypto/inside-secure-safexcel.txt +++ b/dts/Bindings/crypto/inside-secure-safexcel.txt @@ -8,7 +8,11 @@ Required properties: - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". Optional properties: -- clocks: Reference to the crypto engine clock. +- clocks: Reference to the crypto engine clocks, the second clock is + needed for the Armada 7K/8K SoCs. +- clock-names: mandatory if there is a second clock, in this case the + name must be "core" for the first clock and "reg" for + the second one. Example: |