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authorSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-05-08 08:14:56 +0200
commit6b85c20d46812bdbc062b863261c3e5100e30556 (patch)
treee067c9889eaf55d5e793b05a14000276f2669e9f /dts/Bindings
parent9d8c00bdf7c1e8b614a797f0a15fa45bf6387224 (diff)
downloadbarebox-6b85c20d46812bdbc062b863261c3e5100e30556.tar.gz
dts: update to v4.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/arm/arm,scmi.txt179
-rw-r--r--dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp42
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt33
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt23
-rw-r--r--dts/Bindings/arm/mediatek.txt9
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,audsys.txt20
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,pciesys.txt2
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt2
-rw-r--r--dts/Bindings/arm/npcm/npcm.txt6
-rw-r--r--dts/Bindings/arm/omap/ctrl.txt1
-rw-r--r--dts/Bindings/arm/omap/mpu.txt16
-rw-r--r--dts/Bindings/arm/qcom.txt1
-rw-r--r--dts/Bindings/arm/rockchip.txt12
-rw-r--r--dts/Bindings/arm/samsung/pmu.txt6
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt4
-rw-r--r--dts/Bindings/arm/shmobile.txt18
-rw-r--r--dts/Bindings/arm/stm32.txt1
-rw-r--r--dts/Bindings/arm/sunxi/smp-sram.txt44
-rw-r--r--dts/Bindings/arm/tegra.txt16
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt2
-rw-r--r--dts/Bindings/arm/xilinx.txt56
-rw-r--r--dts/Bindings/ata/ahci-platform.txt1
-rw-r--r--dts/Bindings/ata/imx-sata.txt1
-rw-r--r--dts/Bindings/ata/nvidia,tegra124-ahci.txt36
-rw-r--r--dts/Bindings/bus/nvidia,tegra20-gmi.txt6
-rw-r--r--dts/Bindings/clock/imx6sll-clock.txt36
-rw-r--r--dts/Bindings/clock/intc_stratix10.txt20
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt6
-rw-r--r--dts/Bindings/clock/rockchip,rk3328-cru.txt1
-rw-r--r--dts/Bindings/clock/silabs,si544.txt25
-rw-r--r--dts/Bindings/clock/st,stm32mp1-rcc.txt60
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt4
-rw-r--r--dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt93
-rw-r--r--dts/Bindings/clock/ti/davinci/pll.txt96
-rw-r--r--dts/Bindings/clock/ti/davinci/psc.txt71
-rw-r--r--dts/Bindings/clock/ti/divider.txt3
-rw-r--r--dts/Bindings/clock/ti/mux.txt3
-rw-r--r--dts/Bindings/connector/samsung,usb-connector-11pin.txt49
-rw-r--r--dts/Bindings/connector/usb-connector.txt75
-rw-r--r--dts/Bindings/cpufreq/cpufreq-dt.txt4
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt4
-rw-r--r--dts/Bindings/cris/axis.txt9
-rw-r--r--dts/Bindings/cris/boards.txt8
-rw-r--r--dts/Bindings/crypto/arm-cryptocell.txt3
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt17
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt6
-rw-r--r--dts/Bindings/display/bridge/renesas,lvds.txt58
-rw-r--r--dts/Bindings/display/bridge/ti,ths813x.txt (renamed from dts/Bindings/display/bridge/ti,ths8135.txt)13
-rw-r--r--dts/Bindings/display/connector/dvi-connector.txt1
-rw-r--r--dts/Bindings/display/etnaviv/etnaviv-drm.txt24
-rw-r--r--dts/Bindings/display/msm/dsi.txt26
-rw-r--r--dts/Bindings/display/panel/arm,versatile-tft-panel.txt31
-rw-r--r--dts/Bindings/display/panel/auo,g104sn02.txt12
-rw-r--r--dts/Bindings/display/panel/display-timing.txt5
-rw-r--r--dts/Bindings/display/panel/koe,tx31d200vm0baa.txt25
-rw-r--r--dts/Bindings/display/panel/orisetech,otm8009a.txt2
-rw-r--r--dts/Bindings/display/panel/raydium,rm68200.txt25
-rw-r--r--dts/Bindings/display/panel/simple-panel.txt4
-rw-r--r--dts/Bindings/display/renesas,du.txt35
-rw-r--r--dts/Bindings/display/rockchip/cdn-dp-rockchip.txt74
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.txt2
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt104
-rw-r--r--dts/Bindings/dma/brcm,bcm2835-dma.txt4
-rw-r--r--dts/Bindings/dma/mtk-hsdma.txt33
-rw-r--r--dts/Bindings/dma/qcom_bam_dma.txt4
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt2
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps,dw-axi-dmac.txt41
-rw-r--r--dts/Bindings/dma/stm32-dma.txt6
-rw-r--r--dts/Bindings/eeprom/at24.txt4
-rw-r--r--dts/Bindings/fsi/fsi.txt151
-rw-r--r--dts/Bindings/gpio/gpio-eic-sprd.txt97
-rw-r--r--dts/Bindings/gpio/gpio-etraxfs.txt22
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt2
-rw-r--r--dts/Bindings/gpio/gpio-sprd.txt28
-rw-r--r--dts/Bindings/gpio/gpio-tz1090-pdc.txt45
-rw-r--r--dts/Bindings/gpio/gpio-tz1090.txt88
-rw-r--r--dts/Bindings/gpio/gpio.txt7
-rw-r--r--dts/Bindings/gpio/nintendo,hollywood-gpio.txt27
-rw-r--r--dts/Bindings/gpio/raspberrypi,firmware-gpio.txt30
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.txt1
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt2
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--dts/Bindings/i2c/i2c-synquacer.txt29
-rw-r--r--dts/Bindings/iio/adc/axp20x_adc.txt48
-rw-r--r--dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt8
-rw-r--r--dts/Bindings/iio/potentiometer/ad5272.txt27
-rw-r--r--dts/Bindings/iio/temperature/mlx90632.txt28
-rw-r--r--dts/Bindings/input/gpio-keys.txt8
-rw-r--r--dts/Bindings/input/zii,rave-sp-pwrbutton.txt22
-rw-r--r--dts/Bindings/interrupt-controller/andestech,ativic32.txt19
-rw-r--r--dts/Bindings/interrupt-controller/axis,crisv32-intc.txt23
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt22
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt78
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.txt5
-rw-r--r--dts/Bindings/iommu/rockchip,iommu.txt7
-rw-r--r--dts/Bindings/ipmi/aspeed-kcs-bmc.txt25
-rw-r--r--dts/Bindings/jailhouse.txt8
-rw-r--r--dts/Bindings/mailbox/hisilicon,hi3660-mailbox.txt51
-rw-r--r--dts/Bindings/mailbox/mailbox.txt28
-rw-r--r--dts/Bindings/media/coda.txt5
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt18
-rw-r--r--dts/Bindings/media/i2c/ov2685.txt41
-rw-r--r--dts/Bindings/media/i2c/ov5695.txt41
-rw-r--r--dts/Bindings/media/i2c/ov7670.txt16
-rw-r--r--dts/Bindings/media/i2c/ov9650.txt36
-rw-r--r--dts/Bindings/media/i2c/tda1997x.txt178
-rw-r--r--dts/Bindings/media/rcar_vin.txt4
-rw-r--r--dts/Bindings/media/renesas,ceu.txt81
-rw-r--r--dts/Bindings/media/s5p-mfc.txt1
-rw-r--r--dts/Bindings/media/spi/sony-cxd2880.txt14
-rw-r--r--dts/Bindings/media/sunxi-ir.txt3
-rw-r--r--dts/Bindings/memory-controllers/ti/emif.txt13
-rw-r--r--dts/Bindings/metag/meta.txt30
-rw-r--r--dts/Bindings/mfd/aspeed-lpc.txt62
-rw-r--r--dts/Bindings/mips/mscc.txt43
-rw-r--r--dts/Bindings/mmc/hi3798cv200-dw-mshc.txt40
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt1
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt4
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc.txt9
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt1
-rw-r--r--dts/Bindings/mtd/fsl-quadspi.txt24
-rw-r--r--dts/Bindings/mtd/marvell-nand.txt5
-rw-r--r--dts/Bindings/mtd/mtd-physmap.txt7
-rw-r--r--dts/Bindings/mtd/pxa3xx-nand.txt50
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt4
-rw-r--r--dts/Bindings/nds32/andestech-boards40
-rw-r--r--dts/Bindings/nds32/atl2c.txt28
-rw-r--r--dts/Bindings/nds32/cpus.txt38
-rw-r--r--dts/Bindings/net/dsa/marvell.txt11
-rw-r--r--dts/Bindings/net/ethernet.txt2
-rw-r--r--dts/Bindings/net/fsl-tsec-phy.txt6
-rw-r--r--dts/Bindings/net/ieee802154/mcr20a.txt23
-rw-r--r--dts/Bindings/net/macb.txt1
-rw-r--r--dts/Bindings/net/meson-dwmac.txt5
-rw-r--r--dts/Bindings/net/nixge.txt32
-rw-r--r--dts/Bindings/net/renesas,ravb.txt1
-rw-r--r--dts/Bindings/net/sff,sfp.txt5
-rw-r--r--dts/Bindings/net/socionext,uniphier-ave4.txt1
-rw-r--r--dts/Bindings/net/ti,dp83867.txt2
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt23
-rw-r--r--dts/Bindings/nvmem/snvs-lpgpr.txt3
-rw-r--r--dts/Bindings/pci/hisilicon-histb-pcie.txt1
-rw-r--r--dts/Bindings/pci/mediatek-pcie.txt11
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt4
-rw-r--r--dts/Bindings/pci/rcar-pci.txt6
-rw-r--r--dts/Bindings/perf/arm-ccn.txt (renamed from dts/Bindings/arm/ccn.txt)0
-rw-r--r--dts/Bindings/phy/meson-gxl-usb2-phy.txt4
-rw-r--r--dts/Bindings/phy/meson-gxl-usb3-phy.txt31
-rw-r--r--dts/Bindings/phy/nvidia,tegra20-usb-phy.txt4
-rw-r--r--dts/Bindings/phy/phy-hi3798cv200-combphy.txt59
-rw-r--r--dts/Bindings/phy/phy-hisi-inno-usb2.txt71
-rw-r--r--dts/Bindings/phy/phy-mapphone-mdm6600.txt29
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt4
-rw-r--r--dts/Bindings/phy/phy-rockchip-typec.txt35
-rw-r--r--dts/Bindings/phy/phy-stm32-usbphyc.txt73
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt6
-rw-r--r--dts/Bindings/phy/qcom-qusb2-phy.txt5
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb3.txt2
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt1
-rw-r--r--dts/Bindings/pinctrl/actions,s900-pinctrl.txt178
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt16
-rw-r--r--dts/Bindings/pinctrl/fsl,imx6sll-pinctrl.txt40
-rw-r--r--dts/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt127
-rw-r--r--dts/Bindings/pinctrl/img,tz1090-pinctrl.txt227
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mcp23s08.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt65xx.txt4
-rw-r--r--dts/Bindings/pinctrl/qcom,sdm845-pinctrl.txt176
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt4
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt1
-rw-r--r--dts/Bindings/pmem/pmem-region.txt65
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt2
-rw-r--r--dts/Bindings/power/reset/gpio-poweroff.txt3
-rw-r--r--dts/Bindings/power/reset/ocelot-reset.txt14
-rw-r--r--dts/Bindings/power/supply/axp20x_battery.txt8
-rw-r--r--dts/Bindings/powerpc/nintendo/wii.txt9
-rw-r--r--dts/Bindings/pwm/ingenic,jz47xx-pwm.txt25
-rw-r--r--dts/Bindings/pwm/pwm-stm32-lp.txt3
-rw-r--r--dts/Bindings/pwm/pwm-sun4i.txt2
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt11
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.txt10
-rw-r--r--dts/Bindings/regulator/88pg86x.txt22
-rw-r--r--dts/Bindings/regulator/fixed-regulator.txt1
-rw-r--r--dts/Bindings/regulator/gpio-regulator.txt2
-rw-r--r--dts/Bindings/regulator/qcom,smd-rpm-regulator.txt48
-rw-r--r--dts/Bindings/reset/renesas,rst.txt2
-rw-r--r--dts/Bindings/reset/st,stm32mp1-rcc.txt6
-rw-r--r--dts/Bindings/rng/imx-rng.txt (renamed from dts/Bindings/rng/imx-rngc.txt)11
-rw-r--r--dts/Bindings/rng/ks-sa-rng.txt21
-rw-r--r--dts/Bindings/rng/omap_rng.txt7
-rw-r--r--dts/Bindings/rng/st,stm32-rng.txt4
-rw-r--r--dts/Bindings/rtc/isil,isl12026.txt28
-rw-r--r--dts/Bindings/scsi/hisilicon-sas.txt7
-rw-r--r--dts/Bindings/serial/8250.txt1
-rw-r--r--dts/Bindings/serial/axis,etraxfs-uart.txt22
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt2
-rw-r--r--dts/Bindings/serial/st,stm32-usart.txt2
-rw-r--r--dts/Bindings/soc/bcm/brcm,bcm2835-vchiq.txt16
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt5
-rw-r--r--dts/Bindings/sound/ak4458.txt23
-rw-r--r--dts/Bindings/sound/ak5558.txt22
-rw-r--r--dts/Bindings/sound/brcm,bcm2835-i2s.txt9
-rw-r--r--dts/Bindings/sound/da7219.txt6
-rw-r--r--dts/Bindings/sound/dmic.txt2
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt1
-rw-r--r--dts/Bindings/sound/imx-audio-wm8962.txt53
-rw-r--r--dts/Bindings/sound/max98090.txt2
-rw-r--r--dts/Bindings/sound/maxim,max9759.txt18
-rw-r--r--dts/Bindings/sound/mt2701-afe-pcm.txt2
-rw-r--r--dts/Bindings/sound/pcm1789.txt22
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt1
-rw-r--r--dts/Bindings/sound/rockchip,rk3288-hdmi-analog.txt2
-rw-r--r--dts/Bindings/sound/rohm,bd28623.txt29
-rw-r--r--dts/Bindings/sound/rt5651.txt17
-rw-r--r--dts/Bindings/sound/rt5665.txt4
-rw-r--r--dts/Bindings/sound/samsung,odroid.txt8
-rw-r--r--dts/Bindings/sound/samsung,tm2-audio.txt14
-rw-r--r--dts/Bindings/sound/samsung-i2s.txt22
-rw-r--r--dts/Bindings/sound/sgtl5000.txt3
-rw-r--r--dts/Bindings/sound/snow.txt13
-rw-r--r--dts/Bindings/sound/st,stm32-sai.txt6
-rw-r--r--dts/Bindings/sound/tda7419.txt38
-rw-r--r--dts/Bindings/sound/uniphier,aio.txt45
-rw-r--r--dts/Bindings/sound/wm8524.txt2
-rw-r--r--dts/Bindings/spi/sh-msiof.txt1
-rw-r--r--dts/Bindings/spi/spi-gpio.txt24
-rw-r--r--dts/Bindings/timer/andestech,atcpit100-timer.txt33
-rw-r--r--dts/Bindings/trivial-devices.txt12
-rw-r--r--dts/Bindings/usb/amlogic,dwc3.txt42
-rw-r--r--dts/Bindings/usb/dwc3.txt16
-rw-r--r--dts/Bindings/usb/mediatek,mtk-xhci.txt5
-rw-r--r--dts/Bindings/usb/mediatek,mtu3.txt5
-rw-r--r--dts/Bindings/usb/usb-ehci.txt6
-rw-r--r--dts/Bindings/usb/usb-hcd.txt9
-rw-r--r--dts/Bindings/usb/usb-ohci.txt6
-rw-r--r--dts/Bindings/usb/usb-uhci.txt3
-rw-r--r--dts/Bindings/usb/usb-xhci.txt5
-rw-r--r--dts/Bindings/vendor-prefixes.txt2
-rw-r--r--dts/Bindings/watchdog/fsl-imx-wdt.txt2
-rw-r--r--dts/Bindings/watchdog/meson-wdt.txt4
-rw-r--r--dts/Bindings/watchdog/mtk-wdt.txt4
-rw-r--r--dts/Bindings/watchdog/nuvoton,npcm-wdt.txt28
-rw-r--r--dts/Bindings/watchdog/sirfsoc_wdt.txt4
-rw-r--r--dts/Bindings/watchdog/sunxi-wdt.txt10
-rw-r--r--dts/Bindings/x86/ce4100.txt37
249 files changed, 4688 insertions, 975 deletions
diff --git a/dts/Bindings/arm/arm,scmi.txt b/dts/Bindings/arm/arm,scmi.txt
new file mode 100644
index 0000000..5f3719a
--- /dev/null
+++ b/dts/Bindings/arm/arm,scmi.txt
@@ -0,0 +1,179 @@
+System Control and Management Interface (SCMI) Message Protocol
+----------------------------------------------------------
+
+The SCMI is intended to allow agents such as OSPM to manage various functions
+that are provided by the hardware platform it is running on, including power
+and performance functions.
+
+This binding is intended to define the interface the firmware implementing
+the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
+and Management Interface Platform Design Document")[0] provide for OSPM in
+the device tree.
+
+Required properties:
+
+The scmi node with the following properties shall be under the /firmware/ node.
+
+- compatible : shall be "arm,scmi"
+- mboxes: List of phandle and mailbox channel specifiers. It should contain
+ exactly one or two mailboxes, one for transmitting messages("tx")
+ and another optional for receiving the notifications("rx") if
+ supported.
+- shmem : List of phandle pointing to the shared memory(SHM) area as per
+ generic mailbox client binding.
+- #address-cells : should be '1' if the device has sub-nodes, maps to
+ protocol identifier for a given sub-node.
+- #size-cells : should be '0' as 'reg' property doesn't have any size
+ associated with it.
+
+Optional properties:
+
+- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
+about the generic mailbox controller and client driver bindings.
+
+The mailbox is the only permitted method of calling the SCMI firmware.
+Mailbox doorbell is used as a mechanism to alert the presence of a
+messages and/or notification.
+
+Each protocol supported shall have a sub-node with corresponding compatible
+as described in the following sections. If the platform supports dedicated
+communication channel for a particular protocol, the 3 properties namely:
+mboxes, mbox-names and shmem shall be present in the sub-node corresponding
+to that protocol.
+
+Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Required properties:
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
+
+Power domain bindings for the power domains based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding for the SCMI power domain providers uses the generic power
+domain binding[2].
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+ domain ID value used by SCMI commands.
+
+Sensor bindings for the sensors based on SCMI Message Protocol
+--------------------------------------------------------------
+SCMI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- #thermal-sensor-cells: should be set to 1. This property follows the
+ thermal device tree bindings[3].
+
+ Valid cell values are raw identifiers (Sensor ID)
+ as used by the firmware. Refer to platform details
+ for your implementation for the IDs to use.
+
+SRAM and Shared Memory for SCMI
+-------------------------------
+
+A small area of SRAM is reserved for SCMI communication between application
+processors and SCP.
+
+The properties should follow the generic mmio-sram description found in [4]
+
+Each sub-node represents the reserved area for SCMI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
+ shared memory
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/power/power_domain.txt
+[3] Documentation/devicetree/bindings/thermal/thermal.txt
+[4] Documentation/devicetree/bindings/sram/sram.txt
+
+Example:
+
+sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox@40000000 {
+ ....
+ #mbox-cells = <1>;
+ reg = <0x0 0x40000000 0x0 0x10000>;
+};
+
+firmware {
+
+ ...
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensors0: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scmi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scmi_clk 4>;
+ power-domains = <&scmi_devpd 1>;
+};
+
+thermal-zones {
+ soc_thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ /* sensor ID */
+ thermal-sensors = <&scmi_sensors0 3>;
+ ...
+ };
+};
diff --git a/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
new file mode 100644
index 0000000..8e04330
--- /dev/null
+++ b/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm750-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name: "nuvoton,npcm750-smp"
+Compatible machines: "nuvoton,npcm750"
+Compatible CPUs: "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index f4a7770..29e1dc5 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -185,6 +185,7 @@ described below.
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
+ "qcom,kryo385"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@@ -198,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
+ "allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"
diff --git a/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
new file mode 100644
index 0000000..10bd35f
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
@@ -0,0 +1,33 @@
+Hisilicon Hip06 Low Pin Count device
+ Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ Hip06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+Required properties:
+- compatible: value should be as follows:
+ (a) "hisilicon,hip06-lpc"
+ (b) "hisilicon,hip07-lpc"
+- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
+- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
+- reg: base memory range where the LPC register set is mapped.
+
+Note:
+ The node name before '@' must be "isa" to represent the binding stick to the
+ ISA/EISA binding specification.
+
+Example:
+
+isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+};
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index 7111fbc..199cd36 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -75,6 +75,29 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon Hi3798CV200 Peripheral Controller
+
+The Hi3798CV200 Peripheral Controller controls peripherals, queries
+their status, and configures some functions of peripherals.
+
+Required properties:
+- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
+ and "simple-mfd".
+- reg: Register address and size of Peripheral Controller.
+- #address-cells: Should be 1.
+- #size-cells: Should be 1.
+
+Examples:
+
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon Hi6220 system controller
Required properties:
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 91d5178..7d21ab3 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -50,6 +50,15 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Reference board for MT7623a with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
+- Reference board for MT7623a with NAND:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
+- Reference board for MT7623n with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
index 9b8f578..34a69ba 100644
--- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
+ - "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- #clock-cells: Must be 1
@@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+Required sub-nodes:
+-------
+For common binding part and usage, refer to
+../sonud/mt2701-afe-pcm.txt.
+
Example:
-audsys: audsys@11220000 {
- compatible = "mediatek,mt7622-audsys", "syscon";
- reg = <0 0x11220000 0 0x1000>;
- #clock-cells = <1>;
-};
+ audsys: clock-controller@11220000 {
+ compatible = "mediatek,mt7622-audsys", "syscon";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ ...
+ };
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840..8f5335b 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt b/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f12..7fe5dc6 100644
--- a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt b/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
index 0076001..b8184da 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/npcm/npcm.txt b/dts/Bindings/arm/npcm/npcm.txt
new file mode 100644
index 0000000..2d87d9e
--- /dev/null
+++ b/dts/Bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+ - compatible = "nuvoton,npcm750";
+
diff --git a/dts/Bindings/arm/omap/ctrl.txt b/dts/Bindings/arm/omap/ctrl.txt
index ce8dabf..f35b779 100644
--- a/dts/Bindings/arm/omap/ctrl.txt
+++ b/dts/Bindings/arm/omap/ctrl.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
+ "ti,omap5-scm-wkup-pad-conf"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)
diff --git a/dts/Bindings/arm/omap/mpu.txt b/dts/Bindings/arm/omap/mpu.txt
index 763695d..f301e63 100644
--- a/dts/Bindings/arm/omap/mpu.txt
+++ b/dts/Bindings/arm/omap/mpu.txt
@@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
+am335x and am437x only:
+- pm-sram: Phandles to ocmcram nodes to be used for power management.
+ First should be type 'protect-exec' for the driver to use to copy
+ and run PM functions, second should be regular pool to be used for
+ data region for code. See Documentation/devicetree/bindings/sram/sram.txt
+ for more details.
+
Examples:
- For an OMAP5 SMP system:
@@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
+
+- For an AM335x system:
+
+mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ pm-sram = <&pm_sram_code
+ &pm_sram_data>;
+};
diff --git a/dts/Bindings/arm/qcom.txt b/dts/Bindings/arm/qcom.txt
index 0ed4d39..ee532e7 100644
--- a/dts/Bindings/arm/qcom.txt
+++ b/dts/Bindings/arm/qcom.txt
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
msm8996
mdm9615
ipq8074
+ sdm845
The 'board' element must be one of the following strings:
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 326d24b..1c1d62d 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -50,6 +50,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+- Firefly roc-rk3328-cc board:
+ Required root node properties:
+ - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -181,10 +185,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire board standalone:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
+
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
+
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt
index 779f561..1668578 100644
--- a/dts/Bindings/arm/samsung/pmu.txt
+++ b/dts/Bindings/arm/samsung/pmu.txt
@@ -43,6 +43,12 @@ following properties:
- interrupt-parent: a phandle indicating which interrupt controller
this PMU signals interrupts to.
+
+Optional nodes:
+
+- nodes defining the restart and poweroff syscon children
+
+
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 469ac98..14510b2 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -9,7 +9,11 @@ Required root node properties:
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
+ - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
+ - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
+ - "samsung,midas" - for Exynos4412-based Samsung Midas board.
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
+ - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 5c3af7e..d3d1df9 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,8 +39,12 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car M3-N (R8A77965)
+ compatible = "renesas,r8a77965"
- R-Car V3M (R8A77970)
compatible = "renesas,r8a77970"
+ - R-Car V3H (R8A77980)
+ compatible = "renesas,r8a77980"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@@ -52,11 +56,13 @@ Boards:
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
- compatible = "renesas,armadillo800eva"
+ compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+ compatible = "renesas,condor", "renesas,r8a77980"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
@@ -102,19 +108,25 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
+ - Salvator-X (RTP0RC7796SIPB0011S (M3N))
+ compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
+ - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
+ compatible = "renesas,salvator-xs", "renesas,r8a77965"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- - V3MSK
+ - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+ compatible = "renesas,stout", "renesas,r8a7790"
+ - V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- - Wheat
+ - Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/dts/Bindings/arm/stm32.txt b/dts/Bindings/arm/stm32.txt
index 05762b0..6808ed9 100644
--- a/dts/Bindings/arm/stm32.txt
+++ b/dts/Bindings/arm/stm32.txt
@@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
+ st,stm32mp157
diff --git a/dts/Bindings/arm/sunxi/smp-sram.txt b/dts/Bindings/arm/sunxi/smp-sram.txt
new file mode 100644
index 0000000..082e6a9
--- /dev/null
+++ b/dts/Bindings/arm/sunxi/smp-sram.txt
@@ -0,0 +1,44 @@
+Allwinner SRAM for smp bringup:
+------------------------------------------------
+
+Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
+primary core (cpu0). Once the core gets powered up it checks if a magic
+value is set at a specific location. If it is then the BROM will jump
+to the software entry address, instead of executing a standard boot.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Note that this is separate from the Allwinner SRAM controller found in
+../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
+any device.
+
+Also there are no "secure-only" properties. The implementation should
+check if this SRAM is usable first.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+ "allwinner,sun9i-a80-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+ sram_b: sram@20000 {
+ /* 256 KiB secure SRAM at 0x20000 */
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x40000>;
+
+ smp-sram@1000 {
+ /*
+ * This is checked by BROM to determine if
+ * cpu0 should jump to SMP entry vector
+ */
+ compatible = "allwinner,sun9i-a80-smp-sram";
+ reg = <0x1000 0x8>;
+ };
+ };
diff --git a/dts/Bindings/arm/tegra.txt b/dts/Bindings/arm/tegra.txt
index 7f1411b..32f62bb 100644
--- a/dts/Bindings/arm/tegra.txt
+++ b/dts/Bindings/arm/tegra.txt
@@ -9,6 +9,12 @@ following compatible values:
nvidia,tegra20
nvidia,tegra30
+ nvidia,tegra114
+ nvidia,tegra124
+ nvidia,tegra132
+ nvidia,tegra210
+ nvidia,tegra186
+ nvidia,tegra194
Boards
-------------------------------------------
@@ -26,8 +32,18 @@ board-specific compatible values:
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
+ nvidia,dalmore
nvidia,harmony
+ nvidia,jetson-tk1
+ nvidia,norrin
+ nvidia,p2371-0000
+ nvidia,p2371-2180
+ nvidia,p2571
+ nvidia,p2771-0000
+ nvidia,p2972-0000
+ nvidia,roth
nvidia,seaboard
+ nvidia,tn7
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 078a58b..5a3bf7c 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
+ - "nvidia,tegra194-pmc": for Tegra194
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@@ -10,6 +11,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
+ - "misc" (Only for Tegra194)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
diff --git a/dts/Bindings/arm/xilinx.txt b/dts/Bindings/arm/xilinx.txt
index 1f79953..b9043bc 100644
--- a/dts/Bindings/arm/xilinx.txt
+++ b/dts/Bindings/arm/xilinx.txt
@@ -5,3 +5,59 @@ shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-7000";
+
+Additional compatible strings:
+
+- Xilinx internal board cc108
+ "xlnx,zynq-cc108"
+
+- Xilinx internal board zc770 with different FMC cards
+ "xlnx,zynq-zc770-xm010"
+ "xlnx,zynq-zc770-xm011"
+ "xlnx,zynq-zc770-xm012"
+ "xlnx,zynq-zc770-xm013"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+---------------------------------------------------------------
+
+Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
+
+Boards with ZynqMP SOC based on an ARM Cortex A53 processor
+shall have the following properties.
+
+Required root node properties:
+ - compatible = "xlnx,zynqmp";
+
+
+Additional compatible strings:
+
+- Xilinx internal board zc1232
+ "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
+
+- Xilinx internal board zc1254
+ "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
+
+- Xilinx internal board zc1275
+ "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
+
+- Xilinx internal board zc1751
+ "xlnx,zynqmp-zc1751"
+
+- Xilinx 96boards compatible board zcu100
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
+
+- Xilinx evaluation board zcu102
+ "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
+
+- Xilinx evaluation board zcu104
+ "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
+
+- Xilinx evaluation board zcu106
+ "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
+
+- Xilinx evaluation board zcu111
+ "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index c760ecb..f4006d3 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -30,6 +30,7 @@ compatible:
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
+- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
diff --git a/dts/Bindings/ata/imx-sata.txt b/dts/Bindings/ata/imx-sata.txt
index a3d1471..781f887 100644
--- a/dts/Bindings/ata/imx-sata.txt
+++ b/dts/Bindings/ata/imx-sata.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
+ - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
- interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each
diff --git a/dts/Bindings/ata/nvidia,tegra124-ahci.txt b/dts/Bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3..12ab2f7 100644
--- a/dts/Bindings/ata/nvidia,tegra124-ahci.txt
+++ b/dts/Bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,9 +1,10 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
- is tegra132.
+- compatible : Must be one of:
+ - Tegra124 : "nvidia,tegra124-ahci"
+ - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
+ - Tegra210 : "nvidia,tegra210-ahci"
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
@@ -13,8 +14,6 @@ Required properties :
- clock-names : Must include the following entries:
- sata
- sata-oob
- - cml1
- - pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
@@ -24,9 +23,22 @@ Required properties :
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+ - For Tegra124 and Tegra132:
+ - sata-phy : XUSB PADCTL SATA PHY
+- For Tegra124 and Tegra132:
+ - hvdd-supply : Defines the SATA HVDD regulator
+ - vddio-supply : Defines the SATA VDDIO regulator
+ - avdd-supply : Defines the SATA AVDD regulator
+ - target-5v-supply : Defines the SATA 5V power regulator
+ - target-12v-supply : Defines the SATA 12V power regulator
+
+Optional properties:
+- reg :
+ - AUX register set
+- clock-names :
+ - cml1 :
+ cml1 clock should be defined here if the PHY driver
+ doesn't manage them. If it does, they should not be.
+- phy-names :
+ - For T210:
+ - sata-phy
diff --git a/dts/Bindings/bus/nvidia,tegra20-gmi.txt b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
index 3e21eb8..c1e7062 100644
--- a/dts/Bindings/bus/nvidia,tegra20-gmi.txt
+++ b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
@@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -109,7 +108,7 @@ gmi@70090000 {
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -120,7 +119,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;
diff --git a/dts/Bindings/clock/imx6sll-clock.txt b/dts/Bindings/clock/imx6sll-clock.txt
new file mode 100644
index 0000000..fee849d
--- /dev/null
+++ b/dts/Bindings/clock/imx6sll-clock.txt
@@ -0,0 +1,36 @@
+* Clock bindings for Freescale i.MX6 SLL
+
+Required properties:
+- compatible: Should be "fsl,imx6sll-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
+for the full list of i.MX6 SLL clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx6sll-clock.h>
+
+clks: clock-controller@20c4000 {
+ compatible = "fsl,imx6sll-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+};
+
+uart1: serial@2020000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
+ <&clks IMX6SLL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+};
diff --git a/dts/Bindings/clock/intc_stratix10.txt b/dts/Bindings/clock/intc_stratix10.txt
new file mode 100644
index 0000000..9f4ec5c
--- /dev/null
+++ b/dts/Bindings/clock/intc_stratix10.txt
@@ -0,0 +1,20 @@
+Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be
+ "intel,stratix10-clkmgr"
+
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
+
+- #clock-cells : from common clock binding, shall be set to 1.
+
+Example:
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,stratix10-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index f1890d0..773a522 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,7 +22,9 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +34,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
diff --git a/dts/Bindings/clock/rockchip,rk3328-cru.txt b/dts/Bindings/clock/rockchip,rk3328-cru.txt
index e71c675..904ae68 100644
--- a/dts/Bindings/clock/rockchip,rk3328-cru.txt
+++ b/dts/Bindings/clock/rockchip,rk3328-cru.txt
@@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
+ - "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:
diff --git a/dts/Bindings/clock/silabs,si544.txt b/dts/Bindings/clock/silabs,si544.txt
new file mode 100644
index 0000000..b86535b
--- /dev/null
+++ b/dts/Bindings/clock/silabs,si544.txt
@@ -0,0 +1,25 @@
+Binding for Silicon Labs 544 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si544 datasheet
+ https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
+
+Required properties:
+ - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
+ to the speed grade of the chip.
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si544".
+
+Example:
+ si544: clock-controller@55 {
+ reg = <0x55>;
+ #clock-cells = <0>;
+ compatible = "silabs,si544b";
+ };
diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.txt b/dts/Bindings/clock/st,stm32mp1-rcc.txt
new file mode 100644
index 0000000..fb9495e
--- /dev/null
+++ b/dts/Bindings/clock/st,stm32mp1-rcc.txt
@@ -0,0 +1,60 @@
+STMicroelectronics STM32 Peripheral Reset Clock Controller
+==========================================================
+
+The RCC IP is both a reset and a clock controller.
+
+RCC makes also power management (resume/supend and wakeup interrupt).
+
+Please also refer to reset.txt for common reset controller binding usage.
+
+Please also refer to clock-bindings.txt for common clock controller
+binding usage.
+
+
+Required properties:
+- compatible: "st,stm32mp1-rcc", "syscon"
+- reg: should be register base and length as documented in the datasheet
+- #clock-cells: 1, device nodes should specify the clock in their
+ "clocks" property, containing a phandle to the clock device node,
+ an index specifying the clock to use.
+- #reset-cells: Shall be 1
+- interrupts: Should contain a general interrupt line and a interrupt line
+ to the wake-up of processor (CSTOP).
+
+Example:
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp1-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
+ <GIC_SPI 145 IRQ_TYPE_NONE>;
+ };
+
+Specifying clocks
+=================
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/stm32mp1-clks.h header and can be used in device
+tree sources.
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example on STM32MP1, for LTDC reset:
+ ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
+ = 0x180 / 4 * 32 + 0 = 3072
+
+The list of valid indices for STM32MP1 is available in:
+include/dt-bindings/reset-controller/stm32mp1-resets.h
+
+This file implements defines like:
+#define LTDC_R 3072
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index 4ca21c3..460ef27 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
+For the main CCU on H6, one more clock is needed:
+- "iosc": the SoC's internal frequency oscillator
+
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt b/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt
new file mode 100644
index 0000000..1e03dce
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt
@@ -0,0 +1,93 @@
+Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
+
+TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
+registers call CFGCHIPn. Some of these registers function as clock
+gates. This document describes the bindings for those clocks.
+
+All of the clock nodes described below must be child nodes of a CFGCHIP node
+(compatible = "ti,da830-cfgchip").
+
+USB PHY clocks
+--------------
+Required properties:
+- compatible: shall be "ti,da830-usb-phy-clocks".
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "fck", "usb_refclkin", "auxclk"
+
+This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
+clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
+
+eHRPWM Time Base Clock (TBCLK)
+------------------------------
+Required properties:
+- compatible: shall be "ti,da830-tbclksync".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "fck"
+
+PLL DIV4.5 divider
+------------------
+Required properties:
+- compatible: shall be "ti,da830-div4p5ena".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "pll0_pllout"
+
+EMIFA clock source (ASYNC1)
+---------------------------
+Required properties:
+- compatible: shall be "ti,da850-async1-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk3", "div4.5"
+
+ASYNC3 clock source
+-------------------
+Required properties:
+- compatible: shall be "ti,da850-async3-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
+
+Examples:
+
+ cfgchip: syscon@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy_clk: usb-phy-clocks {
+ compatible = "ti,da830-usb-phy-clocks";
+ #clock-cells = <1>;
+ clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
+ clock-names = "fck", "usb_refclkin", "auxclk";
+ };
+ ehrpwm_tbclk: ehrpwm_tbclk {
+ compatible = "ti,da830-tbclksync";
+ #clock-cells = <0>;
+ clocks = <&psc1 17>;
+ clock-names = "fck";
+ };
+ div4p5_clk: div4.5 {
+ compatible = "ti,da830-div4p5ena";
+ #clock-cells = <0>;
+ clocks = <&pll0_pllout>;
+ clock-names = "pll0_pllout";
+ };
+ async1_clk: async1 {
+ compatible = "ti,da850-async1-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
+ clock-names = "pll0_sysclk3", "div4.5";
+ };
+ async3_clk: async3 {
+ compatible = "ti,da850-async3-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
+ clock-names = "pll0_sysclk2", "pll1_sysclk2";
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+
diff --git a/dts/Bindings/clock/ti/davinci/pll.txt b/dts/Bindings/clock/ti/davinci/pll.txt
new file mode 100644
index 0000000..36998e1
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/pll.txt
@@ -0,0 +1,96 @@
+Binding for TI DaVinci PLL Controllers
+
+The PLL provides clocks to most of the components on the SoC. In addition
+to the PLL itself, this controller also contains bypasses, gates, dividers,
+an multiplexers for various clock signals.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area.
+- clocks: phandles corresponding to the clock names
+- clock-names: names of the clock sources - depends on compatible string
+ - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
+ - for "ti,da850-pll1", shall be "clksrc"
+
+Optional properties:
+- ti,clkmode-square-wave: Indicates that the the board is supplying a square
+ wave input on the OSCIN pin instead of using a crystal oscillator.
+ This property is only valid when compatible = "ti,da850-pll0".
+
+
+Optional child nodes:
+
+pllout
+ Describes the main PLL clock output (before POSTDIV). The node name must
+ be "pllout".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+sysclk
+ Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
+ domains. The node name must be "sysclk". Consumers of this node should
+ use "n" in "SYSCLKn" as the index parameter for the clock cell.
+
+ Required properties:
+ - #clock-cells: shall be 1
+
+auxclk
+ Describes the AUXCLK output of the PLL. The node name must be "auxclk".
+ This child node is only valid when compatible = "ti,da850-pll0".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+obsclk
+ Describes the OBSCLK output of the PLL. The node name must be "obsclk".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+
+Examples:
+
+ pll0: clock-controller@11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>, <&pll1_sysclk 3>;
+ clock-names = "clksrc", "extclksrc";
+ ti,clkmode-square-wave;
+
+ pll0_pllout: pllout {
+ #clock-cells = <0>;
+ };
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_auxclk: auxclk {
+ #clock-cells = <0>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+ pll1: clock-controller@21a000 {
+ compatible = "ti,da850-pll1";
+ reg = <0x21a000 0x1000>;
+ clocks = <&ref_clk>;
+ clock-names = "clksrc";
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/dts/Bindings/clock/ti/davinci/psc.txt b/dts/Bindings/clock/ti/davinci/psc.txt
new file mode 100644
index 0000000..dae4ad8
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/psc.txt
@@ -0,0 +1,71 @@
+Binding for TI DaVinci Power Sleep Controller (PSC)
+
+The PSC provides power management, clock gating and reset functionality. It is
+primarily used for clocking.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area
+- #clock-cells: from common clock binding; shall be set to 1
+- #power-domain-cells: from generic power domain binding; shall be set to 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names - depends on compatible value
+ - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1"
+ - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
+
+Optional properties:
+- #reset-cells: from reset binding; shall be set to 1 - only applicable when
+ at least one local domain provides a local reset.
+
+Consumers:
+
+ Clock, power domain and reset consumers shall use the local power domain
+ module ID (LPSC) as the index corresponding to the clock cell. Refer to
+ the device-specific datasheet to find these numbers. NB: Most local
+ domains only provide a clock/power domain and not a reset.
+
+Examples:
+
+ psc0: clock-controller@10000 {
+ compatible = "ti,da850-psc0";
+ reg = <0x10000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
+ <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
+ clock_names = "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1";
+ };
+ psc1: clock-controller@227000 {
+ compatible = "ti,da850-psc1";
+ reg = <0x227000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
+ clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
+ };
+
+ /* consumer */
+ dsp: dsp@11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ clocks = <&psc0 15>;
+ power-domains = <&psc0 15>;
+ resets = <&psc0 15>;
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+- Documentation/devicetree/bindings/power/power_domain.txt
+- Documentation/devicetree/bindings/reset/reset.txt
diff --git a/dts/Bindings/clock/ti/divider.txt b/dts/Bindings/clock/ti/divider.txt
index 35a6f5c..9b13b32 100644
--- a/dts/Bindings/clock/ti/divider.txt
+++ b/dts/Bindings/clock/ti/divider.txt
@@ -75,6 +75,9 @@ Optional properties:
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
+- ti,latch-bit : latch the divider value to HW, only needed if the register
+ access requires this. As an example dra76x DPLL_GMAC H14 divider implements
+ such behavior.
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
diff --git a/dts/Bindings/clock/ti/mux.txt b/dts/Bindings/clock/ti/mux.txt
index 2d0d170..eec8994 100644
--- a/dts/Bindings/clock/ti/mux.txt
+++ b/dts/Bindings/clock/ti/mux.txt
@@ -48,6 +48,9 @@ Optional properties:
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
+- ti,latch-bit : latch the mux value to HW, only needed if the register
+ access requires this. As an example, dra7x DPLL_GMAC H14 muxing
+ implements such behavior.
Examples:
diff --git a/dts/Bindings/connector/samsung,usb-connector-11pin.txt b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
new file mode 100644
index 0000000..22256e2
--- /dev/null
+++ b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
@@ -0,0 +1,49 @@
+Samsung micro-USB 11-pin connector
+==================================
+
+Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
+It is present in multiple Samsung mobile devices.
+It has additional pins to route MHL traffic simultanously with USB.
+
+The bindings are superset of usb-connector bindings for micro-USB connector[1].
+
+Required properties:
+- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
+- type: must be "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS),
+ 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
+
+[1]: bindings/connector/usb-connector.txt
+
+Example
+-------
+
+Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
+connected to HDMI-MHL bridge (sii8620):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "samsung,usb-connector-11pin", "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ usb_con_mhl: endpoint {
+ remote-endpoint = <&sii8620_mhl>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/connector/usb-connector.txt b/dts/Bindings/connector/usb-connector.txt
new file mode 100644
index 0000000..e1463f1
--- /dev/null
+++ b/dts/Bindings/connector/usb-connector.txt
@@ -0,0 +1,75 @@
+USB Connector
+=============
+
+USB connector node represents physical USB connector. It should be
+a child of USB interface controller.
+
+Required properties:
+- compatible: describes type of the connector, must be one of:
+ "usb-a-connector",
+ "usb-b-connector",
+ "usb-c-connector".
+
+Optional properties:
+- label: symbolic name for the connector,
+- type: size of the connector, should be specified in case of USB-A, USB-B
+ non-fullsize connectors: "mini", "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS), present in all connectors,
+ 1: Super Speed (SS), present in SS capable connectors,
+ 2: Sideband use (SBU), present in USB-C.
+
+Examples
+--------
+
+1. Micro-USB connector with HS lines routed via controller (MUIC):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
+};
+
+2. USB-C connector attached to CC controller (s2mm005), HS lines routed
+to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
+DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
+
+ccic: s2mm005@33 {
+ ...
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&max77865_usbc_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&usbdrd_phy_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_sbu: endpoint {
+ remote-endpoint = <&dp_aux>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/cpufreq/cpufreq-dt.txt b/dts/Bindings/cpufreq/cpufreq-dt.txt
index dd3929e..332aed8 100644
--- a/dts/Bindings/cpufreq/cpufreq-dt.txt
+++ b/dts/Bindings/cpufreq/cpufreq-dt.txt
@@ -18,8 +18,6 @@ Optional properties:
in unit of nanoseconds.
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
Examples:
@@ -40,8 +38,6 @@ cpus {
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <2>;
};
cpu@1 {
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
index f640308..d36f07e 100644
--- a/dts/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -21,8 +21,6 @@ Optional properties:
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
for detail.
@@ -67,8 +65,6 @@ Example 1 (MT7623 SoC):
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
};
cpu@1 {
device_type = "cpu";
diff --git a/dts/Bindings/cris/axis.txt b/dts/Bindings/cris/axis.txt
deleted file mode 100644
index d209ca2..0000000
--- a/dts/Bindings/cris/axis.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Axis Communications AB
-ARTPEC series SoC Device Tree Bindings
-
-
-CRISv32 based SoCs are ETRAX FS and ARTPEC-3:
-
- - compatible = "axis,crisv32";
-
-
diff --git a/dts/Bindings/cris/boards.txt b/dts/Bindings/cris/boards.txt
deleted file mode 100644
index 533dd27..0000000
--- a/dts/Bindings/cris/boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Boards based on the CRIS SoCs:
-
-Required root node properties:
- - compatible = should be one or more of the following:
- - "axis,dev88" - for Axis devboard 88 with ETRAX FS
-
-Optional:
-
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt
index cec8d5d..c2598ab 100644
--- a/dts/Bindings/crypto/arm-cryptocell.txt
+++ b/dts/Bindings/crypto/arm-cryptocell.txt
@@ -1,7 +1,8 @@
Arm TrustZone CryptoCell cryptographic engine
Required properties:
-- compatible: Should be "arm,cryptocell-712-ree".
+- compatible: Should be one of: "arm,cryptocell-712-ree",
+ "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt number for the device.
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 76aec8a..3c1f3a2 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
+ - clocks
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: a clock specifier describing the clock required for
+ enabling and disabling SNVS LP RTC.
+
+ - clock-names
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <string>
+ Definition: clock name string should be "snvs-rtc".
+
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
=====================================================================
@@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 30c3ce6..5dba55c 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -8,7 +8,11 @@ Required properties:
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
Optional properties:
-- clocks: Reference to the crypto engine clock.
+- clocks: Reference to the crypto engine clocks, the second clock is
+ needed for the Armada 7K/8K SoCs.
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for
+ the second one.
Example:
diff --git a/dts/Bindings/display/bridge/renesas,lvds.txt b/dts/Bindings/display/bridge/renesas,lvds.txt
new file mode 100644
index 0000000..4f0ab3e
--- /dev/null
+++ b/dts/Bindings/display/bridge/renesas,lvds.txt
@@ -0,0 +1,58 @@
+Renesas R-Car LVDS Encoder
+==========================
+
+These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
+Gen2, R-Car Gen3 and RZ/G SoCs.
+
+Required properties:
+
+- compatible : Shall contain one of
+ - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
+ - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
+ - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
+ - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
+ - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
+ - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
+ - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
+ - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
+
+- reg: Base address and length for the memory-mapped registers
+- clocks: A phandle + clock-specifier pair for the functional clock
+- resets: A phandle + reset specifier for the module reset
+
+Required nodes:
+
+The LVDS encoder has two video ports. Their connections are modelled using the
+OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 corresponds to the parallel RGB input
+- Video port 1 corresponds to the LVDS output
+
+Each port shall have a single endpoint.
+
+
+Example:
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7790-lvds";
+ reg = <0 0xfeb90000 0 0x1c>;
+ clocks = <&cpg CPG_MOD 726>;
+ resets = <&cpg 726>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/ti,ths8135.txt b/dts/Bindings/display/bridge/ti,ths813x.txt
index 6ec1a88..df3d7c1 100644
--- a/dts/Bindings/display/bridge/ti,ths8135.txt
+++ b/dts/Bindings/display/bridge/ti,ths813x.txt
@@ -1,11 +1,16 @@
-THS8135 Video DAC
------------------
+THS8134 and THS8135 Video DAC
+-----------------------------
-This is the binding for Texas Instruments THS8135 Video DAC bridge.
+This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
+THS8135 Video DAC bridges.
Required properties:
-- compatible: Must be "ti,ths8135"
+- compatible: Must be one of
+ "ti,ths8134"
+ "ti,ths8134a," "ti,ths8134"
+ "ti,ths8134b", "ti,ths8134"
+ "ti,ths8135"
Required nodes:
diff --git a/dts/Bindings/display/connector/dvi-connector.txt b/dts/Bindings/display/connector/dvi-connector.txt
index fc53f7c..207e42e 100644
--- a/dts/Bindings/display/connector/dvi-connector.txt
+++ b/dts/Bindings/display/connector/dvi-connector.txt
@@ -10,6 +10,7 @@ Optional properties:
- analog: the connector has DVI analog pins
- digital: the connector has DVI digital pins
- dual-link: the connector has pins for DVI dual-link
+- hpd-gpios: HPD GPIO number
Required nodes:
- Video port for DVI input
diff --git a/dts/Bindings/display/etnaviv/etnaviv-drm.txt b/dts/Bindings/display/etnaviv/etnaviv-drm.txt
index 05176f1..8def11b 100644
--- a/dts/Bindings/display/etnaviv/etnaviv-drm.txt
+++ b/dts/Bindings/display/etnaviv/etnaviv-drm.txt
@@ -1,23 +1,3 @@
-Etnaviv DRM master device
-=========================
-
-The Etnaviv DRM master device is a virtual device needed to list all
-Vivante GPU cores that comprise the GPU subsystem.
-
-Required properties:
-- compatible: Should be one of
- "fsl,imx-gpu-subsystem"
- "marvell,dove-gpu-subsystem"
-- cores: Should contain a list of phandles pointing to Vivante GPU devices
-
-example:
-
-gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu_2d>, <&gpu_3d>;
-};
-
-
Vivante GPU core devices
========================
@@ -32,7 +12,9 @@ Required properties:
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- - "bus": AXI/register clock
+ - "bus": AXI/master interface clock
+ - "reg": AHB/slave interface clock
+ (only required if GPU can gate slave interface independently)
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index a6671bd..518e9cd 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -7,8 +7,6 @@ Required properties:
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
-- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
- be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
@@ -22,6 +20,8 @@ Required properties:
* "core"
For DSIv2, we need an additional clock:
* "src"
+ For DSI6G v2.0 onwards, we need also need the clock:
+ * "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
@@ -88,21 +88,35 @@ Required properties:
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
+ * "qcom,dsi-phy-14nm"
+ * "qcom,dsi-phy-10nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
+ For DSI 14nm and 10nm PHYs:
+ * "dsi_pll"
+ * "dsi_phy"
+ * "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
- be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface"
+ For 28nm HPM/LP, 28nm 8960 PHYs:
+- vddio-supply: phandle to vdd-io regulator device node
+ For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+ For 14nm PHY:
+- vcca-supply: phandle to vcca regulator device node
+ For 10nm PHY:
+- vdds-supply: phandle to vdds regulator device node
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
diff --git a/dts/Bindings/display/panel/arm,versatile-tft-panel.txt b/dts/Bindings/display/panel/arm,versatile-tft-panel.txt
new file mode 100644
index 0000000..248141c
--- /dev/null
+++ b/dts/Bindings/display/panel/arm,versatile-tft-panel.txt
@@ -0,0 +1,31 @@
+ARM Versatile TFT Panels
+
+These panels are connected to the daughterboards found on the
+ARM Versatile reference designs.
+
+This device node must appear as a child to a "syscon"-compatible
+node.
+
+Required properties:
+- compatible: should be "arm,versatile-tft-panel"
+
+Required subnodes:
+- port: see display/panel/panel-common.txt, graph.txt
+
+
+Example:
+
+sysreg@0 {
+ compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
+ reg = <0x00000 0x1000>;
+
+ panel: display@0 {
+ compatible = "arm,versatile-tft-panel";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&foo>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/display/panel/auo,g104sn02.txt b/dts/Bindings/display/panel/auo,g104sn02.txt
new file mode 100644
index 0000000..85626ed
--- /dev/null
+++ b/dts/Bindings/display/panel/auo,g104sn02.txt
@@ -0,0 +1,12 @@
+AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,g104sn02"
+- power-supply: as specified in the base binding
+
+Optional properties:
+- backlight: as specified in the base binding
+- enable-gpios: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/display-timing.txt b/dts/Bindings/display/panel/display-timing.txt
index 58fa3e4..78222ce 100644
--- a/dts/Bindings/display/panel/display-timing.txt
+++ b/dts/Bindings/display/panel/display-timing.txt
@@ -80,6 +80,11 @@ The parameters are defined as:
| | v | | |
+----------+-------------------------------------+----------+-------+
+Note: In addition to being used as subnode(s) of display-timings, the timing
+ subnode may also be used on its own. This is appropriate if only one mode
+ need be conveyed. In this case, the node should be named 'panel-timing'.
+
+
Example:
display-timings {
diff --git a/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt b/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
new file mode 100644
index 0000000..6a036ed
--- /dev/null
+++ b/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
@@ -0,0 +1,25 @@
+Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "koe,tx31d200vm0baa"
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Optional nodes:
+- Video port for LVDS panel input.
+
+Example:
+ panel {
+ compatible = "koe,tx31d200vm0baa";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.txt b/dts/Bindings/display/panel/orisetech,otm8009a.txt
index 6862028..203b03e 100644
--- a/dts/Bindings/display/panel/orisetech,otm8009a.txt
+++ b/dts/Bindings/display/panel/orisetech,otm8009a.txt
@@ -9,6 +9,7 @@ Required properties:
Optional properties:
- reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
Example:
&dsi {
@@ -17,5 +18,6 @@ Example:
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
};
};
diff --git a/dts/Bindings/display/panel/raydium,rm68200.txt b/dts/Bindings/display/panel/raydium,rm68200.txt
new file mode 100644
index 0000000..cbb79ef
--- /dev/null
+++ b/dts/Bindings/display/panel/raydium,rm68200.txt
@@ -0,0 +1,25 @@
+Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
+
+The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+panel connected using a MIPI-DSI video interface.
+
+Required properties:
+ - compatible: "raydium,rm68200"
+ - reg: the virtual channel number of a DSI peripheral
+
+Optional properties:
+ - reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
+ - backlight: phandle of the backlight device attached to the panel.
+
+Example:
+&dsi {
+ ...
+ panel@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
+ backlight = <&pwm_backlight>;
+ };
+};
diff --git a/dts/Bindings/display/panel/simple-panel.txt b/dts/Bindings/display/panel/simple-panel.txt
index 16d8ff0..45a457a 100644
--- a/dts/Bindings/display/panel/simple-panel.txt
+++ b/dts/Bindings/display/panel/simple-panel.txt
@@ -1,4 +1,8 @@
Simple display panel
+====================
+
+panel node
+----------
Required properties:
- power-supply: See panel-common.txt
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index cd48aba..c9cd17f 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -13,13 +13,10 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
+ - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
- - reg: A list of base address and length of each memory resource, one for
- each entry in the reg-names property.
- - reg-names: Name of the memory resources. The DU requires one memory
- resource for the DU core (named "du") and one memory resource for each
- LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
- index).
+ - reg: the memory-mapped I/O registers base address and length
- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifiers for the DU interrupts.
@@ -29,14 +26,13 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- - All other DU instances use one functional clock per channel and one
- clock per LVDS encoder (if available). The functional clocks must be
- named "du.x" with "x" being the channel numerical index. The LVDS clocks
- must be named "lvds.x" with "x" being the LVDS encoder numerical index.
- - In addition to the functional and encoder clocks, all DU versions also
- support externally supplied pixel clocks. Those clocks are optional.
- When supplied they must be named "dclkin.x" with "x" being the input
- clock numerical index.
+ - All other DU instances use one functional clock per channel The
+ functional clocks must be named "du.x" with "x" being the channel
+ numerical index.
+ - In addition to the functional clocks, all DU versions also support
+ externally supplied pixel clocks. Those clocks are optional. When
+ supplied they must be named "dclkin.x" with "x" being the input clock
+ numerical index.
- vsps: A list of phandle and channel index tuples to the VSPs that handle
the memory interfaces for the DU channels. The phandle identifies the VSP
@@ -63,15 +59,15 @@ corresponding to each DU output.
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
+ R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
Example: R8A7795 (R-Car H3) ES2.0 DU
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>,
- <0 0xfeb90000 0 0x14>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -79,9 +75,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
diff --git a/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt b/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 0000000..8df7d2e
--- /dev/null
+++ b/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+================================
+
+Required properties:
+- compatible: must be "rockchip,rk3399-cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+ Required elements: "core-clk" "pclk" "spdif" "grf"
+
+- resets : a list of phandle + reset specifier pairs
+- reset-names : string of reset names
+ Required elements: "apb", "core", "dptx", "spdif"
+- power-domains : power-domain property defined with a phandle
+ to respective power domain.
+- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
+- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+- extcon: extcon specifier for the Power Delivery
+
+- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
+
+-------------------------------------------------------------------------------
+
+Example:
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>;
+ reset-names = "spdif";
+ extcon = <&fusb0>, <&fusb1>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt
index 0292522..3eb1b48 100644
--- a/dts/Bindings/display/st,stm32-ltdc.txt
+++ b/dts/Bindings/display/st,stm32-ltdc.txt
@@ -98,7 +98,7 @@ Example 2: DSI panel
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "ref", "pclk";
+ clock-names = "pclk", "ref";
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index cd626ee..3346c1e 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -64,6 +64,56 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+DWC HDMI TX Encoder
+-------------------
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
+Required properties:
+
+ - compatible: value must be one of:
+ * "allwinner,sun8i-a83t-dw-hdmi"
+ - reg: base address and size of memory-mapped region
+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
+ - interrupts: HDMI interrupt number
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * iahb: the HDMI bus clock
+ * isfr: the HDMI register clock
+ * tmds: TMDS clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller
+ - reset-names: must be "ctrl"
+ - phys: phandle to the DWC HDMI PHY
+ - phy-names: must be "phy"
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
+DWC HDMI PHY
+------------
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-a83t-hdmi-phy
+ * allwinner,sun8i-h3-hdmi-phy
+ - reg: base address and size of memory-mapped region
+ - clocks: phandles to the clocks feeding the HDMI PHY
+ * bus: the HDMI PHY interface clock
+ * mod: the HDMI PHY module clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller driving the PHY
+ - reset-names: must be "phy"
+
+H3 HDMI PHY requires additional clock:
+ - pll-0: parent of phy clock
+
TV Encoder
----------
@@ -94,24 +144,29 @@ Required properties:
* allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
+ * allwinner,sun8i-a83t-tcon-tv
* allwinner,sun8i-v3s-tcon
+ * allwinner,sun9i-a80-tcon-lcd
+ * allwinner,sun9i-a80-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- - clocks: phandles to the clocks feeding the TCON. Three are needed:
+ - clocks: phandles to the clocks feeding the TCON.
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
+ - 'tcon-ch0': The clock driving the TCON channel 0, if supported
- resets: phandles to the reset controllers driving the encoder
- - "lcd": the reset line for the TCON channel 0
+ - "lcd": the reset line for the TCON
+ - "edp": the reset line for the eDP block (A80 only)
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
+ - clock-output-names: Name of the pixel clock created, if TCON supports
+ channel 0.
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, the second one the output
- The output may have multiple endpoints. The TCON has two channels,
+ The output may have multiple endpoints. TCON can have 1 or 2 channels,
usually with the first channel being used for the panels interfaces
(RGB, LVDS, etc.), and the second being used for the outputs that
require another controller (TV Encoder, HDMI, etc.). The endpoints
@@ -119,11 +174,13 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For TCONs with channel 0, there is one more clock required:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
-need one more reset line:
+When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
And on the A23, A31, A31s and A33, you need one more clock line:
@@ -134,7 +191,7 @@ DRC
---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
-(A31, A23, A33), allows to dynamically adjust pixel
+(A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.
@@ -144,6 +201,7 @@ Required properties:
* allwinner,sun6i-a31-drc
* allwinner,sun6i-a31s-drc
* allwinner,sun8i-a33-drc
+ * allwinner,sun9i-a80-drc
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC
@@ -170,6 +228,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend
* allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend
+ * allwinner,sun9i-a80-display-backend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -191,6 +250,28 @@ On the A33, some additional properties are required:
- resets and reset-names need to have a phandle to the SAT bus
resets, whose name will be "sat"
+DEU
+---
+
+The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
+can sharpen the display content in both luma and chroma channels.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun9i-a80-deu
+ - reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the DEU
+ * ahb: the DEU interface clock
+ * mod: the DEU module clock
+ * ram: the DEU DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset line driving the DEU
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the outputs
+
Display Engine Frontend
-----------------------
@@ -204,6 +285,7 @@ Required properties:
* allwinner,sun6i-a31-display-frontend
* allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend
+ * allwinner,sun9i-a80-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -226,6 +308,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-de2-mixer-0
+ * allwinner,sun8i-a83t-de2-mixer-1
+ * allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
@@ -256,7 +340,9 @@ Required properties:
* allwinner,sun7i-a20-display-engine
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-a83t-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
+ * allwinner,sun9i-a80-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
diff --git a/dts/Bindings/dma/brcm,bcm2835-dma.txt b/dts/Bindings/dma/brcm,bcm2835-dma.txt
index baf9b34..b6a8cc0 100644
--- a/dts/Bindings/dma/brcm,bcm2835-dma.txt
+++ b/dts/Bindings/dma/brcm,bcm2835-dma.txt
@@ -74,8 +74,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = < 0x7e203000 0x20>,
- < 0x7e101098 0x02>;
+ reg = < 0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
diff --git a/dts/Bindings/dma/mtk-hsdma.txt b/dts/Bindings/dma/mtk-hsdma.txt
new file mode 100644
index 0000000..4bb3173
--- /dev/null
+++ b/dts/Bindings/dma/mtk-hsdma.txt
@@ -0,0 +1,33 @@
+MediaTek High-Speed DMA Controller
+==================================
+
+This device follows the generic DMA bindings defined in dma/dma.txt.
+
+Required properties:
+
+- compatible: Must be one of
+ "mediatek,mt7622-hsdma": for MT7622 SoC
+ "mediatek,mt7623-hsdma": for MT7623 SoC
+- reg: Should contain the register's base address and length.
+- interrupts: Should contain a reference to the interrupt used by this
+ device.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "hsdma" entries.
+- power-domains: Phandle to the power domain that the device is part of
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+ hsdma: dma-controller@1b007000 {
+ compatible = "mediatek,mt7623-hsdma";
+ reg = <0 0x1b007000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ethsys CLK_ETHSYS_HSDMA>;
+ clock-names = "hsdma";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
diff --git a/dts/Bindings/dma/qcom_bam_dma.txt b/dts/Bindings/dma/qcom_bam_dma.txt
index 9cbf5d9..cf5b9e4 100644
--- a/dts/Bindings/dma/qcom_bam_dma.txt
+++ b/dts/Bindings/dma/qcom_bam_dma.txt
@@ -15,6 +15,10 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
+- num-channels : optional, indicates supported number of DMA channels in a
+ remotely controlled bam.
+- qcom,num-ees : optional, indicates supported number of Execution Environments
+ in a remotely controlled bam.
Example:
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 891db41..aadfb23 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -18,6 +18,7 @@ Required Properties:
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
+ - "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
@@ -26,6 +27,7 @@ Required Properties:
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
- "renesas,dmac-r8a77970" (R-Car V3M)
+ - "renesas,dmac-r8a77980" (R-Car V3H)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt
index f3d1f15..9dc935e 100644
--- a/dts/Bindings/dma/renesas,usb-dmac.txt
+++ b/dts/Bindings/dma/renesas,usb-dmac.txt
@@ -11,6 +11,7 @@ Required Properties:
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
+ - "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.txt b/dts/Bindings/dma/snps,dw-axi-dmac.txt
new file mode 100644
index 0000000..f237b79
--- /dev/null
+++ b/dts/Bindings/dma/snps,dw-axi-dmac.txt
@@ -0,0 +1,41 @@
+Synopsys DesignWare AXI DMA Controller
+
+Required properties:
+- compatible: "snps,axi-dma-1.01a"
+- reg: Address range of the DMAC registers. This should include
+ all of the per-channel registers.
+- interrupt: Should contain the DMAC interrupt number.
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device.
+- dma-channels: Number of channels supported by hardware.
+- snps,dma-masters: Number of AXI masters supported by the hardware.
+- snps,data-width: Maximum AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+- snps,priority: Priority of channel. Array size is equal to the number of
+ dma-channels. Priority value must be programmed within [0:dma-channels-1]
+ range. (0 - minimum priority)
+- snps,block-size: Maximum block size supported by the controller channel.
+ Array size is equal to the number of dma-channels.
+
+Optional properties:
+- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
+ in this property. If this property is missing the maximum AXI burst length
+ supported by DMAC is used. [1:256]
+
+Example:
+
+dmac: dma-controller@80000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x80000 0x400>;
+ clocks = <&core_clk>, <&cfgr_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+
+ dma-channels = <4>;
+ snps,dma-masters = <2>;
+ snps,data-width = <3>;
+ snps,block-size = <4096 4096 4096 4096>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+};
diff --git a/dts/Bindings/dma/stm32-dma.txt b/dts/Bindings/dma/stm32-dma.txt
index 0b55718..c5f5190 100644
--- a/dts/Bindings/dma/stm32-dma.txt
+++ b/dts/Bindings/dma/stm32-dma.txt
@@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
-4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
- dependent:
- -bit 0-1: Fifo threshold
+4. A 32bit bitfield value specifying DMA features which are device dependent:
+ -bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
+
Example:
usart1: serial@40011000 {
diff --git a/dts/Bindings/eeprom/at24.txt b/dts/Bindings/eeprom/at24.txt
index abfae1b..61d833a 100644
--- a/dts/Bindings/eeprom/at24.txt
+++ b/dts/Bindings/eeprom/at24.txt
@@ -41,12 +41,16 @@ Required properties:
"nxp",
"ramtron",
"renesas",
+ "rohm",
"st",
Some vendors use different model names for chips which are just
variants of the above. Known such exceptions are listed below:
+ "nxp,se97b" - the fallback is "atmel,24c02",
"renesas,r1ex24002" - the fallback is "atmel,24c02"
+ "renesas,r1ex24128" - the fallback is "atmel,24c128"
+ "rohm,br24t01" - the fallback is "atmel,24c01"
- reg: The I2C address of the EEPROM.
diff --git a/dts/Bindings/fsi/fsi.txt b/dts/Bindings/fsi/fsi.txt
new file mode 100644
index 0000000..ab516c6
--- /dev/null
+++ b/dts/Bindings/fsi/fsi.txt
@@ -0,0 +1,151 @@
+FSI bus & engine generic device tree bindings
+=============================================
+
+The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
+engines within those slaves. However, we have a facility to match devicetree
+nodes to probed engines. This allows for fsi engines to expose non-probeable
+busses, which are then exposed by the device tree. For example, an FSI engine
+that is an I2C master - the I2C bus can be described by the device tree under
+the engine's device tree node.
+
+FSI masters may require their own DT nodes (to describe the master HW itself);
+that requirement is defined by the master's implementation, and is described by
+the fsi-master-* binding specifications.
+
+Under the masters' nodes, we can describe the bus topology using nodes to
+represent the FSI slaves and their slave engines. As a basic outline:
+
+ fsi-master {
+ /* top-level of FSI bus topology, bound to an FSI master driver and
+ * exposes an FSI bus */
+
+ fsi-slave@<link,id> {
+ /* this node defines the FSI slave device, and is handled
+ * entirely with FSI core code */
+
+ fsi-slave-engine@<addr> {
+ /* this node defines the engine endpoint & address range, which
+ * is bound to the relevant fsi device driver */
+ ...
+ };
+
+ fsi-slave-engine@<addr> {
+ ...
+ };
+
+ };
+ };
+
+Note that since the bus is probe-able, some (or all) of the topology may
+not be described; this binding only provides an optional facility for
+adding subordinate device tree nodes as children of FSI engines.
+
+FSI masters
+-----------
+
+FSI master nodes declare themselves as such with the "fsi-master" compatible
+value. It's likely that an implementation-specific compatible value will
+be needed as well, for example:
+
+ compatible = "fsi-master-gpio", "fsi-master";
+
+Since the master nodes describe the top-level of the FSI topology, they also
+need to declare the FSI-standard addressing scheme. This requires two cells for
+addresses (link index and slave ID), and no size:
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+An optional boolean property can be added to indicate that a particular master
+should not scan for connected devices at initialization time. This is
+necessary in cases where a scan could cause arbitration issues with other
+masters that may be present on the bus.
+
+ no-scan-on-init;
+
+FSI slaves
+----------
+
+Slaves are identified by a (link-index, slave-id) pair, so require two cells
+for an address identifier. Since these are not a range, no size cells are
+required. For an example, a slave on link 1, with ID 2, could be represented
+as:
+
+ cfam@1,2 {
+ reg = <1 2>;
+ [...];
+ }
+
+Each slave provides an address-space, under which the engines are accessible.
+That address space has a maximum of 23 bits, so we use one cell to represent
+addresses and sizes in the slave address space:
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+FSI engines (devices)
+---------------------
+
+Engines are identified by their address under the slaves' address spaces. We
+use a single cell for address and size. Engine nodes represent the endpoint
+FSI device, and are passed to those FSI device drivers' ->probe() functions.
+
+For example, for a slave using a single 0x400-byte page starting at address
+0xc00:
+
+ engine@c00 {
+ reg = <0xc00 0x400>;
+ };
+
+
+Full example
+------------
+
+Here's an example that illustrates:
+ - an FSI master
+ - connected to an FSI slave
+ - that contains an engine that is an I2C master
+ - connected to an I2C EEPROM
+
+The FSI master may be connected to additional slaves, and slaves may have
+additional engines, but they don't necessarily need to be describe in the
+device tree if no extra platform information is required.
+
+ /* The GPIO-based FSI master node, describing the top level of the
+ * FSI bus
+ */
+ gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* A FSI slave (aka. CFAM) at link 0, ID 0. */
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* FSI engine at 0xc00, using a single page. In this example,
+ * it's an I2C master controller, so subnodes describe the
+ * I2C bus.
+ */
+ i2c-controller@c00 {
+ reg = <0xc00 0x400>;
+
+ /* Engine-specific data. In this case, we're describing an
+ * I2C bus, so we're conforming to the generic I2C binding
+ */
+ compatible = "some-vendor,fsi-i2c-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* I2C endpoint device: an Atmel EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/gpio/gpio-eic-sprd.txt b/dts/Bindings/gpio/gpio-eic-sprd.txt
new file mode 100644
index 0000000..93d98d0
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-eic-sprd.txt
@@ -0,0 +1,97 @@
+Spreadtrum EIC controller bindings
+
+The EIC is the abbreviation of external interrupt controller, which can
+be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
+one is in digital chip, and another one is in PMIC. The digital chip EIC
+controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
+EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
+module.
+
+The EIC-debounce sub-module provides up to 8 source input signal
+connections. A debounce mechanism is used to capture the input signals'
+stable status (millisecond resolution) and a single-trigger mechanism
+is introduced into this sub-module to enhance the input event detection
+reliability. In addition, this sub-module's clock can be shut off
+automatically to reduce power dissipation. Moreover the debounce range
+is from 1ms to 4s with a step size of 1ms. The input signal will be
+ignored if it is asserted for less than 1 ms.
+
+The EIC-latch sub-module is used to latch some special power down signals
+and generate interrupts, since the EIC-latch does not depend on the APB
+clock to capture signals.
+
+The EIC-async sub-module uses a 32kHz clock to capture the short signals
+(microsecond resolution) to generate interrupts by level or edge trigger.
+
+The EIC-sync is similar with GPIO's input function, which is a synchronized
+signal input register. It can generate interrupts by level or edge trigger
+when detecting input signals.
+
+Required properties:
+- compatible: Should be one of the following:
+ "sprd,sc9860-eic-debounce",
+ "sprd,sc9860-eic-latch",
+ "sprd,sc9860-eic-async",
+ "sprd,sc9860-eic-sync",
+ "sprd,sc27xx-eic".
+- reg: Define the base and range of the I/O address space containing
+ the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+ the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+ to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ eic_debounce: gpio@40210000 {
+ compatible = "sprd,sc9860-eic-debounce";
+ reg = <0 0x40210000 0 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_latch: gpio@40210080 {
+ compatible = "sprd,sc9860-eic-latch";
+ reg = <0 0x40210080 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_async: gpio@402100a0 {
+ compatible = "sprd,sc9860-eic-async";
+ reg = <0 0x402100a0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_sync: gpio@402100c0 {
+ compatible = "sprd,sc9860-eic-sync";
+ reg = <0 0x402100c0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmic_eic: gpio@300 {
+ compatible = "sprd,sc27xx-eic";
+ reg = <0x300>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/gpio/gpio-etraxfs.txt b/dts/Bindings/gpio/gpio-etraxfs.txt
deleted file mode 100644
index 170194a..0000000
--- a/dts/Bindings/gpio/gpio-etraxfs.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Axis ETRAX FS General I/O controller bindings
-
-Required properties:
-
-- compatible: one of:
- - "axis,etraxfs-gio"
- - "axis,artpec3-gio"
-- reg: Physical base address and length of the controller's registers.
-- #gpio-cells: Should be 3
- - The first cell is the gpio offset number.
- - The second cell is reserved and is currently unused.
- - The third cell is the port number (hex).
-- gpio-controller: Marks the device node as a GPIO controller.
-
-Example:
-
- gio: gpio@b001a000 {
- compatible = "axis,etraxfs-gio";
- reg = <0xb001a000 0x1000>;
- gpio-controller;
- #gpio-cells = <3>;
- };
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index 0d01587..d2a9376 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -16,6 +16,8 @@ Required properties:
nxp,pca9574
nxp,pca9575
nxp,pca9698
+ nxp,pcal6524
+ nxp,pcal9555a
maxim,max7310
maxim,max7312
maxim,max7313
diff --git a/dts/Bindings/gpio/gpio-sprd.txt b/dts/Bindings/gpio/gpio-sprd.txt
new file mode 100644
index 0000000..eca97d4
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-sprd.txt
@@ -0,0 +1,28 @@
+Spreadtrum GPIO controller bindings
+
+The controller's registers are organized as sets of sixteen 16-bit
+registers with each set controlling a bank of up to 16 pins. A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+- compatible: Should be "sprd,sc9860-gpio".
+- reg: Define the base and range of the I/O address space containing
+the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ ap_gpio: gpio@40280000 {
+ compatible = "sprd,sc9860-gpio";
+ reg = <0 0x40280000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/gpio/gpio-tz1090-pdc.txt b/dts/Bindings/gpio/gpio-tz1090-pdc.txt
deleted file mode 100644
index 528f5ef..0000000
--- a/dts/Bindings/gpio/gpio-tz1090-pdc.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-ImgTec TZ1090 PDC GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-pdc-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region. This starts at and cover the SOC_GPIO_CONTROL registers.
-
-- gpio-controller: Specifies that the node is a gpio controller.
-
-- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [PDC gpio number]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 6.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
-Optional properties:
-- gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
-- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt)
-
-
-Example:
-
- pdc_gpios: gpio-controller@2006500 {
- gpio-controller;
- #gpio-cells = <2>;
-
- compatible = "img,tz1090-pdc-gpio";
- reg = <0x02006500 0x100>;
-
- interrupt-parent = <&pdc>;
- interrupts = <8 IRQ_TYPE_NONE>, /* Syswake 0 */
- <9 IRQ_TYPE_NONE>, /* Syswake 1 */
- <10 IRQ_TYPE_NONE>; /* Syswake 2 */
- gpio-ranges = <&pdc_pinctrl 0 0 7>;
- };
diff --git a/dts/Bindings/gpio/gpio-tz1090.txt b/dts/Bindings/gpio/gpio-tz1090.txt
deleted file mode 100644
index b05a90e..0000000
--- a/dts/Bindings/gpio/gpio-tz1090.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-ImgTec TZ1090 GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region.
-
-- #address-cells: Should be 1 (for bank subnodes)
-
-- #size-cells: Should be 0 (for bank subnodes)
-
-- Each bank of GPIOs should have a subnode to represent it.
-
- Bank subnode required properties:
- - reg: Index of bank in the range 0 to 2.
-
- - gpio-controller: Specifies that the node is a gpio controller.
-
- - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [gpio number within the gpio bank]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 29.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
- Bank subnode optional properties:
- - gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
- - interrupts: Interrupt for the entire bank
-
- - interrupt-controller: Specifies that the node is an interrupt controller
-
- - #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
- client nodes should have the following values.
- <[phandle of the interurupt controller]
- [gpio number within the gpio bank]
- [irq flags]>
-
- Values for irq specifier:
- - GPIO number: a value in the range 0 to 29
- - IRQ flags: value to describe edge and level triggering, as defined in
- <dt-bindings/interrupt-controller/irq.h>. Only the following flags are
- supported:
- IRQ_TYPE_EDGE_RISING
- IRQ_TYPE_EDGE_FALLING
- IRQ_TYPE_EDGE_BOTH
- IRQ_TYPE_LEVEL_HIGH
- IRQ_TYPE_LEVEL_LOW
-
-
-
-Example:
-
- gpios: gpio-controller@2005800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "img,tz1090-gpio";
- reg = <0x02005800 0x90>;
-
- /* bank 0 with an interrupt */
- gpios0: bank@0 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <0>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 30>;
- interrupt-controller;
- };
-
- /* bank 2 without interrupt */
- gpios2: bank@2 {
- #gpio-cells = <2>;
- reg = <2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 60 30>;
- };
- };
-
-
diff --git a/dts/Bindings/gpio/gpio.txt b/dts/Bindings/gpio/gpio.txt
index b5de08e..a7c31de 100644
--- a/dts/Bindings/gpio/gpio.txt
+++ b/dts/Bindings/gpio/gpio.txt
@@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using
first 18 GPIOs, at local offset 0 .. 17, are in use.
If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
-additional bitmask is needed to specify which GPIOs are actually in use,
-and which are dummies. The bindings for this case has not yet been
-specified, but should be specified if/when such hardware appears.
+additional set of tuples is needed to specify which GPIOs are unusable, with
+the gpio-reserved-ranges binding. This property indicates the start and size
+of the GPIOs that can't be used.
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
@@ -178,6 +178,7 @@ gpio-controller@00000000 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
+ gpio-reserved-ranges = <0 4>, <12 2>;
gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
"Row A", "Row B", "Row C", "Row D", "NMI button",
diff --git a/dts/Bindings/gpio/nintendo,hollywood-gpio.txt b/dts/Bindings/gpio/nintendo,hollywood-gpio.txt
new file mode 100644
index 0000000..20fc72d
--- /dev/null
+++ b/dts/Bindings/gpio/nintendo,hollywood-gpio.txt
@@ -0,0 +1,27 @@
+Nintendo Wii (Hollywood) GPIO controller
+
+Required properties:
+- compatible: "nintendo,hollywood-gpio
+- reg: Physical base address and length of the controller's registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted).
+
+Optional properties:
+- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
+ interrupt.
+- interrupt-parent: phandle of the parent interrupt controller.
+
+Example:
+
+ GPIO: gpio@d8000c0 {
+ #gpio-cells = <2>;
+ compatible = "nintendo,hollywood-gpio";
+ reg = <0x0d8000c0 0x40>;
+ gpio-controller;
+ ngpios = <24>;
+ }
diff --git a/dts/Bindings/gpio/raspberrypi,firmware-gpio.txt b/dts/Bindings/gpio/raspberrypi,firmware-gpio.txt
new file mode 100644
index 0000000..ce97265
--- /dev/null
+++ b/dts/Bindings/gpio/raspberrypi,firmware-gpio.txt
@@ -0,0 +1,30 @@
+Raspberry Pi GPIO expander
+
+The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
+firmware exposes a mailbox interface that allows the ARM core to control the
+GPIO lines on the expander.
+
+The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi
+firmware node.
+
+Required properties:
+
+- compatible : Should be "raspberrypi,firmware-gpio"
+- gpio-controller : Marks the device node as a gpio controller
+- #gpio-cells : Should be two. The first cell is the pin number, and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+
+Example:
+
+firmware: firmware-rpi {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/dts/Bindings/gpu/arm,mali-utgard.txt b/dts/Bindings/gpu/arm,mali-utgard.txt
index ad87654..c1f65d1 100644
--- a/dts/Bindings/gpu/arm,mali-utgard.txt
+++ b/dts/Bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ + allwinner,sun8i-h3-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index a777477..4a7811e 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -13,7 +13,9 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+ "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.
diff --git a/dts/Bindings/i2c/i2c-sh_mobile.txt b/dts/Bindings/i2c/i2c-sh_mobile.txt
index 2243909..fc7e178 100644
--- a/dts/Bindings/i2c/i2c-sh_mobile.txt
+++ b/dts/Bindings/i2c/i2c-sh_mobile.txt
@@ -13,6 +13,7 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
+ - "renesas,iic-r8a77965" (R-Car M3-N)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
compatible device)
diff --git a/dts/Bindings/i2c/i2c-synquacer.txt b/dts/Bindings/i2c/i2c-synquacer.txt
new file mode 100644
index 0000000..72f4a2f
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-synquacer.txt
@@ -0,0 +1,29 @@
+Socionext SynQuacer I2C
+
+Required properties:
+- compatible : Must be "socionext,synquacer-i2c"
+- reg : Offset and length of the register set for the device
+- interrupts : A single interrupt specifier
+- #address-cells : Must be <1>;
+- #size-cells : Must be <0>;
+- clock-names : Must contain "pclk".
+- clocks : Must contain an entry for each name in clock-names.
+ (See the common clock bindings.)
+
+Optional properties:
+- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
+ Fast modes are supported, possible values are 100000 and
+ 400000.
+
+Example :
+
+ i2c@51210000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x51210000 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "pclk";
+ clocks = <&clk_i2c>;
+ clock-frequency = <400000>;
+ };
diff --git a/dts/Bindings/iio/adc/axp20x_adc.txt b/dts/Bindings/iio/adc/axp20x_adc.txt
new file mode 100644
index 0000000..7a63139
--- /dev/null
+++ b/dts/Bindings/iio/adc/axp20x_adc.txt
@@ -0,0 +1,48 @@
+* X-Powers AXP ADC bindings
+
+Required properties:
+ - compatible: should be one of:
+ - "x-powers,axp209-adc",
+ - "x-powers,axp221-adc",
+ - "x-powers,axp813-adc",
+ - #io-channel-cells: should be 1,
+
+Example:
+
+&axp22x {
+ adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+};
+
+ADC channels and their indexes per variant:
+
+AXP209
+------
+ 0 | acin_v
+ 1 | acin_i
+ 2 | vbus_v
+ 3 | vbus_i
+ 4 | pmic_temp
+ 5 | gpio0_v
+ 6 | gpio1_v
+ 7 | ipsout_v
+ 8 | batt_v
+ 9 | batt_chrg_i
+10 | batt_dischrg_i
+
+AXP22x
+------
+ 0 | pmic_temp
+ 1 | batt_v
+ 2 | batt_chrg_i
+ 3 | batt_dischrg_i
+
+AXP813
+------
+ 0 | pmic_temp
+ 1 | gpio0_v
+ 2 | batt_v
+ 3 | batt_chrg_i
+ 4 | batt_dischrg_i
diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
index 911492d..ed7520d 100644
--- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
@@ -32,6 +32,10 @@ Optional properties:
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration
+ nodes to set pins in mode of operation for dfsdm
+ on external pin.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
@@ -68,8 +72,8 @@ Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- - "MANCH_R": manchester codec, rising edge = logic 0
- - "MANCH_F": manchester codec, falling edge = logic 1
+ - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1
+ - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)
diff --git a/dts/Bindings/iio/potentiometer/ad5272.txt b/dts/Bindings/iio/potentiometer/ad5272.txt
new file mode 100644
index 0000000..f9b2eef
--- /dev/null
+++ b/dts/Bindings/iio/potentiometer/ad5272.txt
@@ -0,0 +1,27 @@
+* Analog Devices AD5272 digital potentiometer
+
+The node for this device must be a child node of a I2C controller, hence
+all mandatory properties for your controller must be specified. See directory:
+
+ Documentation/devicetree/bindings/i2c
+
+for more details.
+
+Required properties:
+ - compatible: Must be one of the following, depending on the model:
+ adi,ad5272-020
+ adi,ad5272-050
+ adi,ad5272-100
+ adi,ad5274-020
+ adi,ad5274-100
+
+Optional properties:
+ - reset-gpios: GPIO specification for the RESET input. This is an
+ active low signal to the AD5272.
+
+Example:
+ad5272: potentiometer@2f {
+ reg = <0x2F>;
+ compatible = "adi,ad5272-020";
+ reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
+};
diff --git a/dts/Bindings/iio/temperature/mlx90632.txt b/dts/Bindings/iio/temperature/mlx90632.txt
new file mode 100644
index 0000000..0b05812
--- /dev/null
+++ b/dts/Bindings/iio/temperature/mlx90632.txt
@@ -0,0 +1,28 @@
+* Melexis MLX90632 contactless Infra Red temperature sensor
+
+Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
+
+There are various applications for the Infra Red contactless temperature sensor
+and MLX90632 is most suitable for consumer applications where measured object
+temperature is in range between -20 to 200 degrees Celsius with relative error
+of measurement below 1 degree Celsius in object temperature range for
+industrial applications. Since it can operate and measure ambient temperature
+in range of -20 to 85 degrees Celsius it is suitable also for outdoor use.
+
+Be aware that electronics surrounding the sensor can increase ambient
+temperature. MLX90632 can be calibrated to reduce the housing effect via
+already existing EEPROM parameters.
+
+Since measured object emissivity effects Infra Red energy emitted, emissivity
+should be set before requesting the object temperature.
+
+Required properties:
+ - compatible: should be "melexis,mlx90632"
+ - reg: the I2C address of the sensor (default 0x3a)
+
+Example:
+
+mlx90632@3a {
+ compatible = "melexis,mlx90632";
+ reg = <0x3a>;
+};
diff --git a/dts/Bindings/input/gpio-keys.txt b/dts/Bindings/input/gpio-keys.txt
index a949404..996ce84 100644
--- a/dts/Bindings/input/gpio-keys.txt
+++ b/dts/Bindings/input/gpio-keys.txt
@@ -26,6 +26,14 @@ Optional subnode-properties:
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
(Legacy property supported: "gpio-key,wakeup")
+ - wakeup-event-action: Specifies whether the key should wake the
+ system when asserted, when deasserted, or both. This property is
+ only valid for keys that wake up the system (e.g., when the
+ "wakeup-source" property is also provided).
+ Supported values are defined in linux-event-codes.h:
+ EV_ACT_ASSERTED - asserted
+ EV_ACT_DEASSERTED - deasserted
+ EV_ACT_ANY - both asserted and deasserted
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.
diff --git a/dts/Bindings/input/zii,rave-sp-pwrbutton.txt b/dts/Bindings/input/zii,rave-sp-pwrbutton.txt
new file mode 100644
index 0000000..43ef770
--- /dev/null
+++ b/dts/Bindings/input/zii,rave-sp-pwrbutton.txt
@@ -0,0 +1,22 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings
+
+RAVE SP input device is a "MFD cell" device corresponding to power
+button functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Should be "zii,rave-sp-pwrbutton"
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ pwrbutton {
+ compatible = "zii,rave-sp-pwrbutton";
+ };
+ }
diff --git a/dts/Bindings/interrupt-controller/andestech,ativic32.txt b/dts/Bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index 0000000..f4b4193
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+ intc: interrupt-controller {
+ compatible = "andestech,ativic32";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
diff --git a/dts/Bindings/interrupt-controller/axis,crisv32-intc.txt b/dts/Bindings/interrupt-controller/axis,crisv32-intc.txt
deleted file mode 100644
index e8b123b..0000000
--- a/dts/Bindings/interrupt-controller/axis,crisv32-intc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* CRISv32 Interrupt Controller
-
-Interrupt controller for the CRISv32 SoCs.
-
-Main node required properties:
-
-- compatible : should be:
- "axis,crisv32-intc"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The type shall be a <u32> and the value shall be 1.
-- reg: physical base address and size of the intc registers map.
-
-Example:
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb001c000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
-
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
new file mode 100644
index 0000000..b47a8a0
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -0,0 +1,22 @@
+Microsemi Ocelot SoC ICPU Interrupt Controller
+
+Required properties:
+
+- compatible : should be "mscc,ocelot-icpu-intr"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+- interrupt-parent : phandle of the CPU interrupt controller.
+- interrupts : Specifies the CPU interrupt the controller is connected to.
+
+Example:
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.txt b/dts/Bindings/interrupt-controller/qcom,pdc.txt
new file mode 100644
index 0000000..0b2c97d
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/qcom,pdc.txt
@@ -0,0 +1,78 @@
+PDC interrupt controller
+
+Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
+Power Domain Controller (PDC) that is on always-on domain. In addition to
+providing power control for the power domains, the hardware also has an
+interrupt controller that can be used to help detect edge low interrupts as
+well detect interrupts when the GIC is non-operational.
+
+GIC is parent interrupt controller at the highest level. Platform interrupt
+controller PDC is next in hierarchy, followed by others. Drivers requiring
+wakeup capabilities of their device interrupts routed through the PDC, must
+specify PDC as their interrupt controller and request the PDC port associated
+with the GIC interrupt. See example below.
+
+Properties:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should contain "qcom,<soc>-pdc"
+ - "qcom,sdm845-pdc": For SDM845
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Specifies the base physical address for PDC hardware.
+
+- interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Specifies the number of cells needed to encode an interrupt
+ source.
+ Must be 2.
+ The first element of the tuple is the PDC pin for the
+ interrupt.
+ The second element is the trigger type.
+
+- interrupt-parent:
+ Usage: required
+ Value type: <phandle>
+ Definition: Specifies the interrupt parent necessary for hierarchical
+ domain to operate.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <bool>
+ Definition: Identifies the node as an interrupt controller.
+
+- qcom,pdc-ranges:
+ Usage: required
+ Value type: <u32 array>
+ Definition: Specifies the PDC pin offset and the number of PDC ports.
+ The tuples indicates the valid mapping of valid PDC ports
+ and their hwirq mapping.
+ The first element of the tuple is the starting PDC port.
+ The second element is the GIC hwirq number for the PDC port.
+ The third element is the number of interrupts in sequence.
+
+Example:
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sdm845-pdc";
+ reg = <0xb220000 0x30000>;
+ qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+DT binding of a device that wants to use the GIC SPI 514 as a wakeup
+interrupt, must do -
+
+ wake-device {
+ interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
+the qcom,pdc-ranges property.
diff --git a/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt b/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
index 1fd5d69..ffadb7c 100644
--- a/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
+++ b/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -11,6 +11,8 @@ Required Properties:
the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
+ - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
+ - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
@@ -19,7 +21,8 @@ Required Properties:
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
- - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
+ - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
+ IPMMU.
- reg: Base address and size of the IPMMU registers.
- interrupts: Specifiers for the MMU fault interrupts. For instances that
diff --git a/dts/Bindings/iommu/rockchip,iommu.txt b/dts/Bindings/iommu/rockchip,iommu.txt
index 2098f77..6ecefea 100644
--- a/dts/Bindings/iommu/rockchip,iommu.txt
+++ b/dts/Bindings/iommu/rockchip,iommu.txt
@@ -14,6 +14,11 @@ Required properties:
"single-master" device, and needs no additional information
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
+- clocks : A list of clocks required for the IOMMU to be accessible by
+ the host CPU.
+- clock-names : Should contain the following:
+ "iface" - Main peripheral bus clock (PCLK/HCL) (required)
+ "aclk" - AXI bus clock (required)
Optional properties:
- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
@@ -27,5 +32,7 @@ Example:
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
};
diff --git a/dts/Bindings/ipmi/aspeed-kcs-bmc.txt b/dts/Bindings/ipmi/aspeed-kcs-bmc.txt
new file mode 100644
index 0000000..d98a9bf
--- /dev/null
+++ b/dts/Bindings/ipmi/aspeed-kcs-bmc.txt
@@ -0,0 +1,25 @@
+* Aspeed KCS (Keyboard Controller Style) IPMI interface
+
+The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
+(Baseboard Management Controllers) and the KCS interface can be
+used to perform in-band IPMI communication with their host.
+
+Required properties:
+- compatible : should be one of
+ "aspeed,ast2400-kcs-bmc"
+ "aspeed,ast2500-kcs-bmc"
+- interrupts : interrupt generated by the controller
+- kcs_chan : The LPC channel number in the controller
+- kcs_addr : The host CPU IO map address
+
+
+Example:
+
+ kcs3: kcs3@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ kcs_chan = <3>;
+ kcs_addr = <0xCA2>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/jailhouse.txt b/dts/Bindings/jailhouse.txt
new file mode 100644
index 0000000..2901c25
--- /dev/null
+++ b/dts/Bindings/jailhouse.txt
@@ -0,0 +1,8 @@
+Jailhouse non-root cell device tree bindings
+--------------------------------------------
+
+When running in a non-root Jailhouse cell (partition), the device tree of this
+platform shall have a top-level "hypervisor" node with the following
+properties:
+
+- compatible = "jailhouse,cell"
diff --git a/dts/Bindings/mailbox/hisilicon,hi3660-mailbox.txt b/dts/Bindings/mailbox/hisilicon,hi3660-mailbox.txt
new file mode 100644
index 0000000..3e5b453
--- /dev/null
+++ b/dts/Bindings/mailbox/hisilicon,hi3660-mailbox.txt
@@ -0,0 +1,51 @@
+Hisilicon Hi3660 Mailbox Controller
+
+Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
+are passed between processors, including application & communication
+processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
+by using MMIO registers; it supports maximum to 8 words message.
+
+Controller
+----------
+
+Required properties:
+- compatible: : Shall be "hisilicon,hi3660-mbox"
+- reg: : Offset and length of the device's register set
+- #mbox-cells: : Must be 3
+ <&phandle channel dst_irq ack_irq>
+ phandle : Label name of controller
+ channel : Channel number
+ dst_irq : Remote interrupt vector
+ ack_irq : Local interrupt vector
+
+- interrupts: : Contains the two IRQ lines for mailbox.
+
+Example:
+
+mailbox: mailbox@e896b000 {
+ compatible = "hisilicon,hi3660-mbox";
+ reg = <0x0 0xe896b000 0x0 0x1000>;
+ interrupts = <0x0 0xc0 0x4>,
+ <0x0 0xc1 0x4>;
+ #mbox-cells = <3>;
+};
+
+Client
+------
+
+Required properties:
+- compatible : See the client docs
+- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
+ Cells must match 'mbox-cells' (See Controller docs above)
+
+Optional properties
+- mbox-names : Name given to channels seen in the 'mboxes' property.
+
+Example:
+
+stub_clock: stub_clock@e896b500 {
+ compatible = "hisilicon,hi3660-stub-clk";
+ reg = <0x0 0xe896b500 0x0 0x0100>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 13 3 0>;
+};
diff --git a/dts/Bindings/mailbox/mailbox.txt b/dts/Bindings/mailbox/mailbox.txt
index be05b97..af8ecee 100644
--- a/dts/Bindings/mailbox/mailbox.txt
+++ b/dts/Bindings/mailbox/mailbox.txt
@@ -23,6 +23,11 @@ Required property:
Optional property:
- mbox-names: List of identifier strings for each mailbox channel.
+- shmem : List of phandle pointing to the shared memory(SHM) area between the
+ users of these mailboxes for IPC, one for each mailbox. This shared
+ memory can be part of any memory reserved for the purpose of this
+ communication between the mailbox client and the remote.
+
Example:
pwr_cntrl: power {
@@ -30,3 +35,26 @@ Example:
mbox-names = "pwr-ctrl", "rpc";
mboxes = <&mailbox 0 &mailbox 1>;
};
+
+Example with shared memory(shmem):
+
+ sram: sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x50000000 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50000000 0x10000>;
+
+ cl_shmem: shmem@0 {
+ compatible = "client-shmem";
+ reg = <0x0 0x200>;
+ };
+ };
+
+ client@2e000000 {
+ ...
+ mboxes = <&mailbox 0>;
+ shmem = <&cl_shmem>;
+ ..
+ };
diff --git a/dts/Bindings/media/coda.txt b/dts/Bindings/media/coda.txt
index 2865d04..90eb74c 100644
--- a/dts/Bindings/media/coda.txt
+++ b/dts/Bindings/media/coda.txt
@@ -7,8 +7,9 @@ called VPU (Video Processing Unit).
Required properties:
- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
(a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
- (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
- (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+ (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
+ (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
+ (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
- reg: should be register base and length as documented in the
SoC reference manual
- interrupts : Should contain the VPU interrupt. For CODA960,
diff --git a/dts/Bindings/media/i2c/adv7604.txt b/dts/Bindings/media/i2c/adv7604.txt
index 9cbd92e..dcf57e7 100644
--- a/dts/Bindings/media/i2c/adv7604.txt
+++ b/dts/Bindings/media/i2c/adv7604.txt
@@ -13,7 +13,11 @@ Required Properties:
- "adi,adv7611" for the ADV7611
- "adi,adv7612" for the ADV7612
- - reg: I2C slave address
+ - reg: I2C slave addresses
+ The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
+ main I2C ports. Each map has it own I2C address and acts as a standard
+ slave device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
- hpd-gpios: References to the GPIOs that control the HDMI hot-plug
detection pins, one per HDMI input. The active flag indicates the GPIO
@@ -35,6 +39,11 @@ Optional Properties:
- reset-gpios: Reference to the GPIO connected to the device's reset pin.
- default-input: Select which input is selected after reset.
+ - reg-names : Names of maps with programmable addresses.
+ It can contain any map needing a non-default address.
+ Possible maps names are :
+ "main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe",
+ "rep", "edid", "hdmi", "test", "cp", "vdp"
Optional Endpoint Properties:
@@ -52,7 +61,12 @@ Example:
hdmi_receiver@4c {
compatible = "adi,adv7611";
- reg = <0x4c>;
+ /*
+ * The edid page will be accessible @ 0x66 on the I2C bus. All
+ * other maps will retain their default addresses.
+ */
+ reg = <0x4c>, <0x66>;
+ reg-names "main", "edid";
reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
diff --git a/dts/Bindings/media/i2c/ov2685.txt b/dts/Bindings/media/i2c/ov2685.txt
new file mode 100644
index 0000000..625c4a8
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov2685.txt
@@ -0,0 +1,41 @@
+* Omnivision OV2685 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: shall be "ovti,ov2685"
+- clocks: reference to the xvclk input clock
+- clock-names: shall be "xvclk"
+- avdd-supply: Analog voltage supply, 2.8 volts
+- dovdd-supply: Digital I/O voltage supply, 1.8 volts
+- dvdd-supply: Digital core voltage supply, 1.8 volts
+- reset-gpios: Low active reset gpio
+
+The device node shall contain one 'port' child node with an
+'endpoint' subnode for its digital output video port,
+in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+The endpoint optional property 'data-lanes' shall be "<1>".
+
+Example:
+&i2c7 {
+ ov2685: camera-sensor@3c {
+ compatible = "ovti,ov2685";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&cru SCLK_TESTCLKOUT1>;
+ clock-names = "xvclk";
+
+ avdd-supply = <&pp2800_cam>;
+ dovdd-supply = <&pp1800>;
+ dvdd-supply = <&pp1800>;
+ reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/ov5695.txt b/dts/Bindings/media/i2c/ov5695.txt
new file mode 100644
index 0000000..640a637
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov5695.txt
@@ -0,0 +1,41 @@
+* Omnivision OV5695 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: shall be "ovti,ov5695"
+- clocks: reference to the xvclk input clock
+- clock-names: shall be "xvclk"
+- avdd-supply: Analog voltage supply, 2.8 volts
+- dovdd-supply: Digital I/O voltage supply, 1.8 volts
+- dvdd-supply: Digital core voltage supply, 1.2 volts
+- reset-gpios: Low active reset gpio
+
+The device node shall contain one 'port' child node with an
+'endpoint' subnode for its digital output video port,
+in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+The endpoint optional property 'data-lanes' shall be "<1 2>".
+
+Example:
+&i2c7 {
+ ov5695: camera-sensor@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&cru SCLK_TESTCLKOUT1>;
+ clock-names = "xvclk";
+
+ avdd-supply = <&pp2800_cam>;
+ dovdd-supply = <&pp1800>;
+ dvdd-supply = <&pp1250_cam>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+
+ port {
+ wcam_out: endpoint {
+ remote-endpoint = <&mipi_in_wcam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/ov7670.txt b/dts/Bindings/media/i2c/ov7670.txt
index 826b656..2c972a5 100644
--- a/dts/Bindings/media/i2c/ov7670.txt
+++ b/dts/Bindings/media/i2c/ov7670.txt
@@ -9,14 +9,21 @@ Required Properties:
- clocks: reference to the xclk input clock.
- clock-names: should be "xclk".
+Required Endpoint Properties:
+- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
+- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
+
Optional Properties:
- reset-gpios: reference to the GPIO connected to the resetb pin, if any.
Active is low.
- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
Active is high.
+- ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output
+ signal during horizontal blankings.
-The device node must contain one 'port' child node for its digital output
-video port, in accordance with the video interface bindings defined in
+The device node must contain one 'port' child node with one 'endpoint' child
+sub-node for its digital output video port, in accordance with the video
+interface bindings defined in:
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
@@ -34,8 +41,13 @@ Example:
assigned-clocks = <&pck0>;
assigned-clock-rates = <25000000>;
+ ov7670,pclk-hb-disable;
+
port {
ov7670_0: endpoint {
+ hsync-active = <0>;
+ vsync-active = <0>;
+
remote-endpoint = <&isi_0>;
};
};
diff --git a/dts/Bindings/media/i2c/ov9650.txt b/dts/Bindings/media/i2c/ov9650.txt
new file mode 100644
index 0000000..506dfc5
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov9650.txt
@@ -0,0 +1,36 @@
+* Omnivision OV9650/OV9652 CMOS sensor
+
+Required Properties:
+- compatible: shall be one of
+ "ovti,ov9650"
+ "ovti,ov9652"
+- clocks: reference to the xvclk input clock.
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the resetb pin, if any.
+ Active is high.
+- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
+ Active is high.
+
+The device node shall contain one 'port' child node with one child 'endpoint'
+subnode for its digital output video port, in accordance with the video
+interface bindings defined in Documentation/devicetree/bindings/media/
+video-interfaces.txt.
+
+Example:
+
+&i2c0 {
+ ov9650: camera@30 {
+ compatible = "ovti,ov9650";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>;
+ clocks = <&xclk>;
+
+ port {
+ ov9650_0: endpoint {
+ remote-endpoint = <&vcap1_in0>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/tda1997x.txt b/dts/Bindings/media/i2c/tda1997x.txt
new file mode 100644
index 0000000..e761679
--- /dev/null
+++ b/dts/Bindings/media/i2c/tda1997x.txt
@@ -0,0 +1,178 @@
+Device-Tree bindings for the NXP TDA1997x HDMI receiver
+
+The TDA19971/73 are HDMI video receivers.
+
+The TDA19971 Video port output pins can be used as follows:
+ - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
+ - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
+ - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
+ - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
+ - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
+ - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
+ - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The TDA19973 Video port output pins can be used as follows:
+ - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
+ - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
+ - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The Video port output pins are mapped via 4-bit 'pin groups' allowing
+for a variety of connection possibilities including swapping pin order within
+pin groups. The video_portcfg device-tree property consists of register mapping
+pairs which map a chip-specific VP output register to a 4-bit pin group. If
+the pin group needs to be bit-swapped you can use the *_S pin-group defines.
+
+Required Properties:
+ - compatible :
+ - "nxp,tda19971" for the TDA19971
+ - "nxp,tda19973" for the TDA19973
+ - reg : I2C slave address
+ - interrupts : The interrupt number
+ - DOVDD-supply : Digital I/O supply
+ - DVDD-supply : Digital Core supply
+ - AVDD-supply : Analog supply
+ - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
+
+Optional Properties:
+ - nxp,audout-format : DAI bus format: "i2s" or "spdif".
+ - nxp,audout-width : width of audio output data bus (1-4).
+ - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
+ - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
+ mclk.
+
+The port node shall contain one endpoint child node for its digital
+output video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Optional Endpoint Properties:
+ The following three properties are defined in video-interfaces.txt and
+ are valid for the output parallel bus endpoint:
+ - hsync-active: Horizontal synchronization polarity. Defaults to active high.
+ - vsync-active: Vertical synchronization polarity. Defaults to active high.
+ - data-active: Data polarity. Defaults to active high.
+
+Examples:
+ - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
+ * 2 pixclk cycles.
+ */
+ nxp,vidout-portcfg =
+ /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
+ /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/rcar_vin.txt b/dts/Bindings/media/rcar_vin.txt
index 19357d0..1ce7ff9 100644
--- a/dts/Bindings/media/rcar_vin.txt
+++ b/dts/Bindings/media/rcar_vin.txt
@@ -56,7 +56,7 @@ Board setup example (vin1 composite video input)
------------------------------------------------
&i2c2 {
- status = "ok";
+ status = "okay";
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@@ -79,7 +79,7 @@ Board setup example (vin1 composite video input)
pinctrl-0 = <&vin1_pins>;
pinctrl-names = "default";
- status = "ok";
+ status = "okay";
port {
#address-cells = <1>;
diff --git a/dts/Bindings/media/renesas,ceu.txt b/dts/Bindings/media/renesas,ceu.txt
new file mode 100644
index 0000000..3fc66df
--- /dev/null
+++ b/dts/Bindings/media/renesas,ceu.txt
@@ -0,0 +1,81 @@
+Renesas Capture Engine Unit (CEU)
+----------------------------------------------
+
+The Capture Engine Unit is the image capture interface found in the Renesas
+SH Mobile and RZ SoCs.
+
+The interface supports a single parallel input with data bus width of 8 or 16
+bits.
+
+Required properties:
+- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
+ and RZ/A1M SoCs.
+- reg: Registers address base and size.
+- interrupts: The interrupt specifier.
+
+The CEU supports a single parallel input and should contain a single 'port'
+subnode with a single 'endpoint'. Connection to input devices are modeled
+according to the video interfaces OF bindings specified in:
+Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Optional endpoint properties applicable to parallel input bus described in
+the above mentioned "video-interfaces.txt" file are supported.
+
+- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
+ If property is not present, default is active high.
+- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
+ If property is not present, default is active high.
+
+Example:
+
+The example describes the connection between the Capture Engine Unit and an
+OV7670 image sensor connected to i2c1 interface.
+
+ceu: ceu@e8210000 {
+ reg = <0xe8210000 0x209c>;
+ compatible = "renesas,r7s72100-ceu";
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ status = "okay";
+
+ port {
+ ceu_in: endpoint {
+ remote-endpoint = <&ov7670_out>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+i2c1: i2c@fcfee400 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ ov7670: camera@21 {
+ compatible = "ovti,ov7670";
+ reg = <0x21>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov7670_out: endpoint {
+ remote-endpoint = <&ceu_in>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/s5p-mfc.txt b/dts/Bindings/media/s5p-mfc.txt
index d3404b5..aa54c81 100644
--- a/dts/Bindings/media/s5p-mfc.txt
+++ b/dts/Bindings/media/s5p-mfc.txt
@@ -13,6 +13,7 @@ Required properties:
(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
+ (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
diff --git a/dts/Bindings/media/spi/sony-cxd2880.txt b/dts/Bindings/media/spi/sony-cxd2880.txt
new file mode 100644
index 0000000..fc5aa26
--- /dev/null
+++ b/dts/Bindings/media/spi/sony-cxd2880.txt
@@ -0,0 +1,14 @@
+Sony CXD2880 DVB-T2/T tuner + demodulator driver SPI adapter
+
+Required properties:
+- compatible: Should be "sony,cxd2880".
+- reg: SPI chip select number for the device.
+- spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
+
+Example:
+
+cxd2880@0 {
+ compatible = "sony,cxd2880";
+ reg = <0>; /* CE0 */
+ spi-max-frequency = <55000000>; /* 55MHz */
+};
diff --git a/dts/Bindings/media/sunxi-ir.txt b/dts/Bindings/media/sunxi-ir.txt
index 91648c5..2780989 100644
--- a/dts/Bindings/media/sunxi-ir.txt
+++ b/dts/Bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+ if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <3000000>;
resets = <&apb0_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
diff --git a/dts/Bindings/memory-controllers/ti/emif.txt b/dts/Bindings/memory-controllers/ti/emif.txt
index 621b41c..44d7146 100644
--- a/dts/Bindings/memory-controllers/ti/emif.txt
+++ b/dts/Bindings/memory-controllers/ti/emif.txt
@@ -3,7 +3,9 @@
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
-of the EMIF IP and memory parts attached to it.
+of the EMIF IP and memory parts attached to it. Certain revisions
+of the EMIF controller also contain optional ECC support, which
+corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
@@ -11,6 +13,8 @@ Required properties:
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
+ "ti,emif-dra7xx"
+ "ti,emif-keystone"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@@ -22,6 +26,7 @@ Required properties:
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
+- interrupts : interrupt used by the controller
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
@@ -71,3 +76,9 @@ emif: emif@4c000000 {
sram = <&pm_sram_code
&pm_sram_data>;
};
+
+emif1: emif@4c000000 {
+ compatible = "ti,emif-dra7xx";
+ reg = <0x4c000000 0x200>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/Bindings/metag/meta.txt b/dts/Bindings/metag/meta.txt
deleted file mode 100644
index f4457f5..0000000
--- a/dts/Bindings/metag/meta.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Meta Processor Binding
-
-This binding specifies what properties must be available in the device tree
-representation of a Meta Processor Core, which is the root node in the tree.
-
-Required properties:
-
- - compatible: Specifies the compatibility list for the Meta processor.
- The type shall be <string> and the value shall include "img,meta".
-
-Optional properties:
-
- - clocks: Clock consumer specifiers as described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
- - clock-names: Clock consumer names as described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-Clocks are identified by name. Valid clocks are:
-
- - "core": The Meta core clock from which the Meta timers are derived.
-
-* Examples
-
-/ {
- compatible = "toumaz,tz1090", "img,meta";
-
- clocks = <&meta_core_clk>;
- clock-names = "core";
-};
diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt
index 514d82c..34dd890 100644
--- a/dts/Bindings/mfd/aspeed-lpc.txt
+++ b/dts/Bindings/mfd/aspeed-lpc.txt
@@ -109,9 +109,50 @@ lpc: lpc@1e789000 {
};
};
+BMC Node Children
+==================
+
+
Host Node Children
==================
+LPC Host Interface Controller
+-------------------
+
+The LPC Host Interface Controller manages functions exposed to the host such as
+LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+management and bus snoop configuration.
+
+Required properties:
+
+- compatible: One of:
+ "aspeed,ast2400-lpc-ctrl";
+ "aspeed,ast2500-lpc-ctrl";
+
+- reg: contains offset/length values of the host interface controller
+ memory regions
+
+- clocks: contains a phandle to the syscon node describing the clocks.
+ There should then be one cell representing the clock to use
+
+- memory-region: A phandle to a reserved_memory region to be used for the LPC
+ to AHB mapping
+
+- flash: A phandle to the SPI flash controller containing the flash to
+ be exposed over the LPC to AHB mapping
+
+Example:
+
+lpc-host@80 {
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+};
+
LPC Host Controller
-------------------
@@ -135,3 +176,24 @@ lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+LPC reset control
+-----------------
+
+The UARTs present in the ASPEED SoC can have their resets tied to the reset
+state of the LPC bus. Some systems may chose to modify this configuration.
+
+Required properties:
+
+ - compatible: "aspeed,ast2500-lpc-reset" or
+ "aspeed,ast2400-lpc-reset"
+ - reg: offset and length of the IP in the LHC memory region
+ - #reset-controller indicates the number of reset cells expected
+
+Example:
+
+lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+};
diff --git a/dts/Bindings/mips/mscc.txt b/dts/Bindings/mips/mscc.txt
new file mode 100644
index 0000000..ae15ec3
--- /dev/null
+++ b/dts/Bindings/mips/mscc.txt
@@ -0,0 +1,43 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianness, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
diff --git a/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt b/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt
new file mode 100644
index 0000000..a0693b7
--- /dev/null
+++ b/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt
@@ -0,0 +1,40 @@
+* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
+ Storage Host Controller
+
+Read synopsys-dw-mshc.txt for more details
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
+specific extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+- clock-names: Should contain the following:
+ "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
+ "biu" - The biu clock described in synopsys-dw-mshc.txt.
+ "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
+ "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
+
+Example:
+
+ emmc: mmc@9830000 {
+ compatible = "hisilicon,hi3798cv200-dw-mshc";
+ reg = <0x9830000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_MMC_CIU_CLK>,
+ <&crg HISTB_MMC_BIU_CLK>,
+ <&crg HISTB_MMC_SAMPLE_CLK>,
+ <&crg HISTB_MMC_DRV_CLK>;
+ clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+ fifo-depth = <256>;
+ clock-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ bus-width = <8>;
+ };
diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt
index 9b80176..f33467a 100644
--- a/dts/Bindings/mmc/mtk-sd.txt
+++ b/dts/Bindings/mmc/mtk-sd.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
+ "mediatek,mt7622-mmc": for MT7622 SoC
"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- reg: physical base address of the controller and length
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index c655878..8ce49b2 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -21,7 +21,7 @@ Required Properties:
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
Optional Properties:
-* clocks: from common clock binding: if ciu_drive and ciu_sample are
+* clocks: from common clock binding: if ciu-drive and ciu-sample are
specified in clock-names, should contain handles to these clocks.
* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt
@@ -29,7 +29,7 @@ Optional Properties:
to control the clock phases, "ciu-sample" is required for tuning high-
speed modes.
-* rockchip,default-sample-phase: The default phase to set ciu_sample at
+* rockchip,default-sample-phase: The default phase to set ciu-sample at
probing, low speeds or in case where all phases work at tuning time.
If not specified 0 deg will be used.
diff --git a/dts/Bindings/mmc/synopsys-dw-mshc.txt b/dts/Bindings/mmc/synopsys-dw-mshc.txt
index ef3e5f1..7e5e427 100644
--- a/dts/Bindings/mmc/synopsys-dw-mshc.txt
+++ b/dts/Bindings/mmc/synopsys-dw-mshc.txt
@@ -59,15 +59,6 @@ Optional properties:
is specified and the ciu clock is specified then we'll try to set the ciu
clock to this at probe time.
-* clock-freq-min-max (DEPRECATED): Minimum and Maximum clock frequency for card output
- clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
- (Use the "max-frequency" instead of "clock-freq-min-max".)
-
-* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
- The number of physical slots actually used could be equal or less than the
- value specified by num-slots. If this property is not specified, the value
- of num-slot property is assumed to be 1.
-
* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
specified, the default value of the fifo size is determined from the
controller registers.
diff --git a/dts/Bindings/mmc/tmio_mmc.txt b/dts/Bindings/mmc/tmio_mmc.txt
index d8685cb..2d5287e 100644
--- a/dts/Bindings/mmc/tmio_mmc.txt
+++ b/dts/Bindings/mmc/tmio_mmc.txt
@@ -50,7 +50,6 @@ Required properties:
2: R7S72100
Optional properties:
-- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
diff --git a/dts/Bindings/mtd/fsl-quadspi.txt b/dts/Bindings/mtd/fsl-quadspi.txt
index 63d4d62..483e9cf 100644
--- a/dts/Bindings/mtd/fsl-quadspi.txt
+++ b/dts/Bindings/mtd/fsl-quadspi.txt
@@ -39,3 +39,27 @@ qspi0: quadspi@40044000 {
....
};
};
+
+Example showing the usage of two SPI NOR devices:
+
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <0>;
+ };
+
+ flash1: n25q256a@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <1>;
+ };
+};
diff --git a/dts/Bindings/mtd/marvell-nand.txt b/dts/Bindings/mtd/marvell-nand.txt
index c08fb47..e0c7907 100644
--- a/dts/Bindings/mtd/marvell-nand.txt
+++ b/dts/Bindings/mtd/marvell-nand.txt
@@ -14,7 +14,10 @@ Required properties:
- #address-cells: shall be set to 1. Encode the NAND CS.
- #size-cells: shall be set to 0.
- interrupts: shall define the NAND controller interrupt.
-- clocks: shall reference the NAND controller clock.
+- clocks: shall reference the NAND controller clocks, the second one is
+ is only needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case there
+ should be one clock named "core" and another one named "reg"
- marvell,system-controller: Set to retrieve the syscon node that handles
NAND controller related registers (only required with the
"marvell,armada-8k-nand[-controller]" compatibles).
diff --git a/dts/Bindings/mtd/mtd-physmap.txt b/dts/Bindings/mtd/mtd-physmap.txt
index 4a0a48b..232fa12 100644
--- a/dts/Bindings/mtd/mtd-physmap.txt
+++ b/dts/Bindings/mtd/mtd-physmap.txt
@@ -41,6 +41,13 @@ additional (optional) property is defined:
- erase-size : The chip's physical erase block size in bytes.
+ The device tree may optionally contain endianness property.
+ little-endian or big-endian : It Represents the endianness that should be used
+ by the controller to properly read/write data
+ from/to the flash. If this property is missing,
+ the endianness is chosen by the system
+ (potentially based on extra configuration options).
+
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/dts/Bindings/mtd/pxa3xx-nand.txt b/dts/Bindings/mtd/pxa3xx-nand.txt
deleted file mode 100644
index d4ee4da..0000000
--- a/dts/Bindings/mtd/pxa3xx-nand.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-PXA3xx NAND DT bindings
-
-Required properties:
-
- - compatible: Should be set to one of the following:
- marvell,pxa3xx-nand
- marvell,armada370-nand
- marvell,armada-8k-nand
- - reg: The register base for the controller
- - interrupts: The interrupt to map
- - #address-cells: Set to <1> if the node includes partitions
- - marvell,system-controller: Set to retrieve the syscon node that handles
- NAND controller related registers (only required
- with marvell,armada-8k-nand compatible).
-
-Optional properties:
-
- - dmas: dma data channel, see dma.txt binding doc
- - marvell,nand-enable-arbiter: Set to enable the bus arbiter
- - marvell,nand-keep-config: Set to keep the NAND controller config as set
- by the bootloader
- - num-cs: Number of chipselect lines to use
- - nand-on-flash-bbt: boolean to enable on flash bbt option if
- not present false
- - nand-ecc-strength: number of bits to correct per ECC step
- - nand-ecc-step-size: number of data bytes covered by a single ECC step
-
-The following ECC strength and step size are currently supported:
-
- - nand-ecc-strength = <1>, nand-ecc-step-size = <512>
- - nand-ecc-strength = <4>, nand-ecc-step-size = <512>
- - nand-ecc-strength = <8>, nand-ecc-step-size = <512>
-
-Example:
-
- nand0: nand@43100000 {
- compatible = "marvell,pxa3xx-nand";
- reg = <0x43100000 90>;
- interrupts = <45>;
- dmas = <&pdma 97 0>;
- dma-names = "data";
- #address-cells = <1>;
-
- marvell,nand-enable-arbiter;
- marvell,nand-keep-config;
- num-cs = <1>;
-
- /* partitions (optional) */
- };
-
diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt
index 5e13a5c..0734f03 100644
--- a/dts/Bindings/mtd/sunxi-nand.txt
+++ b/dts/Bindings/mtd/sunxi-nand.txt
@@ -24,8 +24,8 @@ Optional properties:
- allwinner,rb : shall contain the native Ready/Busy ids.
or
- rb-gpios : shall contain the gpios used as R/B pins.
-- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
- "soft_bch" or "none")
+- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
+ "none")
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
diff --git a/dts/Bindings/nds32/andestech-boards b/dts/Bindings/nds32/andestech-boards
new file mode 100644
index 0000000..f5d7569
--- /dev/null
+++ b/dts/Bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-----------------------------------------------------------------------------
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+ compatible = "andestech,ae3xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+};
+
+Andestech(nds32) AG101P Platform
+-----------------------------------------------------------------------------
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+ compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+ compatible = "andestech,ag101p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+};
diff --git a/dts/Bindings/nds32/atl2c.txt b/dts/Bindings/nds32/atl2c.txt
new file mode 100644
index 0000000..da8ab8e
--- /dev/null
+++ b/dts/Bindings/nds32/atl2c.txt
@@ -0,0 +1,28 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: "andestech,atl2c"
+ - reg : Physical base address and size of cache controller's memory mapped
+ - cache-unified : Specifies the cache is a unified cache.
+ - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+ cache-controller@e0500000 {
+ compatible = "andestech,atl2c";
+ reg = <0xe0500000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
diff --git a/dts/Bindings/nds32/cpus.txt b/dts/Bindings/nds32/cpus.txt
new file mode 100644
index 0000000..6f9e311
--- /dev/null
+++ b/dts/Bindings/nds32/cpus.txt
@@ -0,0 +1,38 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should be "andestech,<core_name>", "andestech,nds32v3" as fallback.
+ Must contain "andestech,nds32v3" as the most generic value, in addition to
+ one of the following identifiers for a particular CPU core:
+ "andestech,n13"
+ "andestech,n15"
+ "andestech,d15"
+ "andestech,n10"
+ "andestech,d10"
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - reg: Contains CPU index.
+ - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+ cpus {
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "andestech,n13", "andestech,nds32v3";
+ reg = <0x0>;
+ clock-frequency = <60000000>
+ };
+ };
+};
diff --git a/dts/Bindings/net/dsa/marvell.txt b/dts/Bindings/net/dsa/marvell.txt
index 8c033d4..60d50a2 100644
--- a/dts/Bindings/net/dsa/marvell.txt
+++ b/dts/Bindings/net/dsa/marvell.txt
@@ -13,9 +13,18 @@ placed as a child node of an mdio device.
The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.
+The compatibility string is used only to find an identification register,
+which is at a different MDIO base address in different switch families.
+- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
+ 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
+ 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
+ 6341, 6350, 6351, 6352
+- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
+ 6190, 6190X, 6191, 6290, 6390, 6390X
+
Required properties:
- compatible : Should be one of "marvell,mv88e6085" or
- "marvell,mv88e6190"
+ "marvell,mv88e6190" as indicated above
- reg : Address on the MII bus for the switch.
Optional properties:
diff --git a/dts/Bindings/net/ethernet.txt b/dts/Bindings/net/ethernet.txt
index 2974e63..cfc376b 100644
--- a/dts/Bindings/net/ethernet.txt
+++ b/dts/Bindings/net/ethernet.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt.
the boot program; should be used in cases where the MAC address assigned to
the device by the boot program is different from the "local-mac-address"
property;
+- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
+- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
the maximum frame size (there's contradiction in the Devicetree
diff --git a/dts/Bindings/net/fsl-tsec-phy.txt b/dts/Bindings/net/fsl-tsec-phy.txt
index 594982c..79bf352 100644
--- a/dts/Bindings/net/fsl-tsec-phy.txt
+++ b/dts/Bindings/net/fsl-tsec-phy.txt
@@ -6,7 +6,11 @@ the definition of the PHY node in booting-without-of.txt for an example
of how to define a PHY.
Required properties:
- - reg : Offset and length of the register set for the device
+ - reg : Offset and length of the register set for the device, and optionally
+ the offset and length of the TBIPA register (TBI PHY address
+ register). If TBIPA register is not specified, the driver will
+ attempt to infer it from the register set specified (your mileage may
+ vary).
- compatible : Should define the compatible device type for the
mdio. Currently supported strings/devices are:
- "fsl,gianfar-tbi"
diff --git a/dts/Bindings/net/ieee802154/mcr20a.txt b/dts/Bindings/net/ieee802154/mcr20a.txt
new file mode 100644
index 0000000..2aaef56
--- /dev/null
+++ b/dts/Bindings/net/ieee802154/mcr20a.txt
@@ -0,0 +1,23 @@
+* MCR20A IEEE 802.15.4 *
+
+Required properties:
+ - compatible: should be "nxp,mcr20a"
+ - spi-max-frequency: maximal bus speed, should be set to a frequency
+ lower than 9000000 depends sync or async operation mode
+ - reg: the chipselect index
+ - interrupts: the interrupt generated by the device. Non high-level
+ can occur deadlocks while handling isr.
+
+Optional properties:
+ - rst_b-gpio: GPIO spec for the RST_B pin
+
+Example:
+
+ mcr20a@0 {
+ compatible = "nxp,mcr20a";
+ spi-max-frequency = <9000000>;
+ reg = <0>;
+ interrupts = <17 2>;
+ interrupt-parent = <&gpio>;
+ rst_b-gpio = <&gpio 27 1>
+ };
diff --git a/dts/Bindings/net/macb.txt b/dts/Bindings/net/macb.txt
index 27966ae..457d5ae 100644
--- a/dts/Bindings/net/macb.txt
+++ b/dts/Bindings/net/macb.txt
@@ -29,6 +29,7 @@ Optional properties for PHY child node:
- reset-gpios : Should specify the gpio for phy reset
- magic-packet : If present, indicates that the hardware supports waking
up via magic packet.
+- phy-handle : see ethernet.txt file in the same directory
Examples:
diff --git a/dts/Bindings/net/meson-dwmac.txt b/dts/Bindings/net/meson-dwmac.txt
index 354dd98..61cada2 100644
--- a/dts/Bindings/net/meson-dwmac.txt
+++ b/dts/Bindings/net/meson-dwmac.txt
@@ -9,6 +9,7 @@ Required properties on all platforms:
- compatible: Depending on the platform this should be one of:
- "amlogic,meson6-dwmac"
- "amlogic,meson8b-dwmac"
+ - "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
@@ -19,13 +20,13 @@ Required properties on all platforms:
configuration (for example the PRG_ETHERNET register range
on Meson8b and newer)
-Required properties on Meson8b and newer:
+Required properties on Meson8b, Meson8m2, GXBB and newer:
- clock-names: Should contain the following:
- "stmmaceth" - see stmmac.txt
- "clkin0" - first parent clock of the internal mux
- "clkin1" - second parent clock of the internal mux
-Optional properties on Meson8b and newer:
+Optional properties on Meson8b, Meson8m2, GXBB and newer:
- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
by this driver) in nanoseconds. Allowed values
are: 0ns, 2ns, 4ns, 6ns.
diff --git a/dts/Bindings/net/nixge.txt b/dts/Bindings/net/nixge.txt
new file mode 100644
index 0000000..e55af7f
--- /dev/null
+++ b/dts/Bindings/net/nixge.txt
@@ -0,0 +1,32 @@
+* NI XGE Ethernet controller
+
+Required properties:
+- compatible: Should be "ni,xge-enet-2.00"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain tx and rx interrupt
+- interrupt-names: Should be "rx" and "tx"
+- phy-mode: See ethernet.txt file in the same directory.
+- phy-handle: See ethernet.txt file in the same directory.
+- nvmem-cells: Phandle of nvmem cell containing the MAC address
+- nvmem-cell-names: Should be "address"
+
+Examples (10G generic PHY):
+ nixge0: ethernet@40000000 {
+ compatible = "ni,xge-enet-2.00";
+ reg = <0x40000000 0x6000>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&intc>;
+
+ phy-mode = "xgmii";
+ phy-handle = <&ethernet_phy1>;
+
+ ethernet_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt
index b4dc455..c306f55 100644
--- a/dts/Bindings/net/renesas,ravb.txt
+++ b/dts/Bindings/net/renesas,ravb.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
- "renesas,etheravb-r8a7745" for the R8A7745 SoC.
+ - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
- "renesas,etheravb-r8a7790" for the R8A7790 SoC.
- "renesas,etheravb-r8a7791" for the R8A7791 SoC.
- "renesas,etheravb-r8a7792" for the R8A7792 SoC.
diff --git a/dts/Bindings/net/sff,sfp.txt b/dts/Bindings/net/sff,sfp.txt
index f1c441b..929591d 100644
--- a/dts/Bindings/net/sff,sfp.txt
+++ b/dts/Bindings/net/sff,sfp.txt
@@ -33,6 +33,10 @@ Optional Properties:
Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
high Tx rate. Must not be present for SFF modules
+- maximum-power-milliwatt : Maximum module power consumption
+ Specifies the maximum power consumption allowable by a module in the
+ slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W.
+
Example #1: Direct serdes to SFP connection
sfp_eth3: sfp-eth3 {
@@ -40,6 +44,7 @@ sfp_eth3: sfp-eth3 {
i2c-bus = <&sfp_1g_i2c>;
los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <1000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
diff --git a/dts/Bindings/net/socionext,uniphier-ave4.txt b/dts/Bindings/net/socionext,uniphier-ave4.txt
index 270ea4e..96398cc 100644
--- a/dts/Bindings/net/socionext,uniphier-ave4.txt
+++ b/dts/Bindings/net/socionext,uniphier-ave4.txt
@@ -9,6 +9,7 @@ Required properties:
- "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
- "socionext,uniphier-ld11-ave4" : for LD11 SoC
- "socionext,uniphier-ld20-ave4" : for LD20 SoC
+ - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC
- reg: Address where registers are mapped and size of region.
- interrupts: Should contain the MAC interrupt.
- phy-mode: See ethernet.txt in the same directory. Allow to choose
diff --git a/dts/Bindings/net/ti,dp83867.txt b/dts/Bindings/net/ti,dp83867.txt
index 02c4353..9ef9338 100644
--- a/dts/Bindings/net/ti,dp83867.txt
+++ b/dts/Bindings/net/ti,dp83867.txt
@@ -25,6 +25,8 @@ Optional property:
software needs to take when this pin is
strapped in these modes. See data manual
for details.
+ - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
+ for applicable values.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
diff --git a/dts/Bindings/nvmem/imx-ocotp.txt b/dts/Bindings/nvmem/imx-ocotp.txt
index f162c72..729f674 100644
--- a/dts/Bindings/nvmem/imx-ocotp.txt
+++ b/dts/Bindings/nvmem/imx-ocotp.txt
@@ -11,17 +11,32 @@ Required properties:
"fsl,imx6ul-ocotp" (i.MX6UL),
"fsl,imx7d-ocotp" (i.MX7D/S),
followed by "syscon".
+- #address-cells : Should be 1
+- #size-cells : Should be 1
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
Optional properties:
- read-only: disable write access
-Example:
+Optional Child nodes:
+
+- Data cells of ocotp:
+ Detailed bindings are described in bindings/nvmem/nvmem.txt
+Example:
ocotp: ocotp@21bc000 {
- compatible = "fsl,imx6q-ocotp", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_IIM>;
- read-only;
+ clocks = <&clks IMX6SX_CLK_OCOTP>;
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
diff --git a/dts/Bindings/nvmem/snvs-lpgpr.txt b/dts/Bindings/nvmem/snvs-lpgpr.txt
index 20bc49b..3cb1708 100644
--- a/dts/Bindings/nvmem/snvs-lpgpr.txt
+++ b/dts/Bindings/nvmem/snvs-lpgpr.txt
@@ -1,5 +1,5 @@
Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
-Secure Non-Volatile Storage.
+and i.MX7 Secure Non-Volatile Storage.
This DT node should be represented as a sub-node of a "syscon",
"simple-mfd" node.
@@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the fallowing variants:
"fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
"fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
+ "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
Example:
snvs: snvs@020cc000 {
diff --git a/dts/Bindings/pci/hisilicon-histb-pcie.txt b/dts/Bindings/pci/hisilicon-histb-pcie.txt
index c84bc02..760b4d7 100644
--- a/dts/Bindings/pci/hisilicon-histb-pcie.txt
+++ b/dts/Bindings/pci/hisilicon-histb-pcie.txt
@@ -34,6 +34,7 @@ Required properties
Optional properties:
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
+- vpcie-supply: The regulator in charge of PCIe port power.
- phys: List of phandle and phy mode specifier, should be 0.
- phy-names: Must be "phy".
diff --git a/dts/Bindings/pci/mediatek-pcie.txt b/dts/Bindings/pci/mediatek-pcie.txt
index 3a6ce55..20227a8 100644
--- a/dts/Bindings/pci/mediatek-pcie.txt
+++ b/dts/Bindings/pci/mediatek-pcie.txt
@@ -78,7 +78,7 @@ Examples for MT7623:
#reset-cells = <1>;
};
- pcie: pcie-controller@1a140000 {
+ pcie: pcie@1a140000 {
compatible = "mediatek,mt7623-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
@@ -111,7 +111,6 @@ Examples for MT7623:
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -123,7 +122,6 @@ Examples for MT7623:
};
pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -135,7 +133,6 @@ Examples for MT7623:
};
pcie@2,0 {
- device_type = "pci";
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -148,6 +145,7 @@ Examples for MT7623:
};
Examples for MT2712:
+
pcie: pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
@@ -169,7 +167,6 @@ Examples for MT2712:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -189,7 +186,6 @@ Examples for MT2712:
};
pcie1: pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -210,6 +206,7 @@ Examples for MT2712:
};
Examples for MT7622:
+
pcie: pcie@1a140000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
@@ -243,7 +240,6 @@ Examples for MT7622:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -263,7 +259,6 @@ Examples for MT7622:
};
pcie1: pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt
index 3c9d321..1fd703b 100644
--- a/dts/Bindings/pci/qcom,pcie.txt
+++ b/dts/Bindings/pci/qcom,pcie.txt
@@ -189,6 +189,10 @@
Value type: <phandle>
Definition: A phandle to the analog power supply for IC which generates
reference clock
+- vddpe-3v3-supply:
+ Usage: optional
+ Value type: <phandle>
+ Definition: A phandle to the PCIe endpoint power supply
- phys:
Usage: required for apq8084
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index 76ba3a6..1fb614e 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -1,13 +1,15 @@
* Renesas R-Car PCIe interface
Required properties:
-compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
+compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
+ "renesas,pcie-r8a7779" for the R8A7779 SoC;
"renesas,pcie-r8a7790" for the R8A7790 SoC;
"renesas,pcie-r8a7791" for the R8A7791 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
"renesas,pcie-r8a7796" for the R8A7796 SoC;
- "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
+ "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
+ RZ/G1 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/arm/ccn.txt b/dts/Bindings/perf/arm-ccn.txt
index 43b5a71..43b5a71 100644
--- a/dts/Bindings/arm/ccn.txt
+++ b/dts/Bindings/perf/arm-ccn.txt
diff --git a/dts/Bindings/phy/meson-gxl-usb2-phy.txt b/dts/Bindings/phy/meson-gxl-usb2-phy.txt
index a105494..b84a02e 100644
--- a/dts/Bindings/phy/meson-gxl-usb2-phy.txt
+++ b/dts/Bindings/phy/meson-gxl-usb2-phy.txt
@@ -6,6 +6,10 @@ Required properties:
- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
Optional properties:
+- clocks: a phandle to the clock of this PHY
+- clock-names: must be "phy"
+- resets: a phandle to the reset line of this PHY
+- reset-names: must be "phy"
- phy-supply: see phy-bindings.txt in this directory
diff --git a/dts/Bindings/phy/meson-gxl-usb3-phy.txt b/dts/Bindings/phy/meson-gxl-usb3-phy.txt
new file mode 100644
index 0000000..114947e
--- /dev/null
+++ b/dts/Bindings/phy/meson-gxl-usb3-phy.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
+
+Required properties:
+- compatible: Should be "amlogic,meson-gxl-usb3-phy"
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+- reg: The base address and length of the registers
+- interrupts: the interrupt specifier for the OTG detection
+- clocks: phandles to the clocks for
+ - the USB3 PHY
+ - and peripheral mode/OTG detection
+- clock-names: must contain "phy" and "peripheral"
+- resets: phandle to the reset lines for:
+ - the USB3 PHY and
+ - peripheral mode/OTG detection
+- reset-names: must contain "phy" and "peripheral"
+
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+
+Example:
+ usb3_phy0: phy@78080 {
+ compatible = "amlogic,meson-gxl-usb3-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x78080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "phy", "peripheral";
+ resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
+ reset-names = "phy", "peripheral";
+ };
diff --git a/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt b/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt
index a9aa79f..1aa6f26 100644
--- a/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt
+++ b/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt
@@ -21,7 +21,9 @@ Required properties :
- timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi.
- - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+ - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
+ with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
+ "nvidia,function" pllp_out4).
Present if phy_type == ulpi, and ULPI link mode is in use.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
diff --git a/dts/Bindings/phy/phy-hi3798cv200-combphy.txt b/dts/Bindings/phy/phy-hi3798cv200-combphy.txt
new file mode 100644
index 0000000..17b0c76
--- /dev/null
+++ b/dts/Bindings/phy/phy-hi3798cv200-combphy.txt
@@ -0,0 +1,59 @@
+HiSilicon STB PCIE/SATA/USB3 PHY
+
+Required properties:
+- compatible: Should be "hisilicon,hi3798cv200-combphy"
+- reg: Should be the address space for COMBPHY configuration and state
+ registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
+ PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
+- #phy-cells: Should be 1. The cell number is used to select the phy mode
+ as defined in <dt-bindings/phy/phy.h>.
+- clocks: The phandle to clock provider and clock specifier pair.
+- resets: The phandle to reset controller and reset specifier pair.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Optional properties:
+- hisilicon,fixed-mode: If the phy device doesn't support mode select
+ but a fixed mode setting, the property should be present to specify
+ the particular mode.
+- hisilicon,mode-select-bits: If the phy device support mode select,
+ this property should be present to specify the register bits in
+ peripheral controller, as a 3 integers tuple:
+ <register_offset bit_shift bit_mask>.
+
+Notes:
+- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
+ one of them should be present.
+- The device node should be a child of peripheral controller that contains
+ COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
+ Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
+ bindings.
+
+Examples:
+
+perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ combphy0: phy@850 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x850 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY0_CLK>;
+ resets = <&crg 0x188 4>;
+ hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+ };
+
+ combphy1: phy@858 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x858 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY1_CLK>;
+ resets = <&crg 0x188 12>;
+ hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
+ };
+};
diff --git a/dts/Bindings/phy/phy-hisi-inno-usb2.txt b/dts/Bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 0000000..0d70c83
--- /dev/null
+++ b/dts/Bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,71 @@
+Device tree bindings for HiSilicon INNO USB2 PHY
+
+Required properties:
+- compatible: Should be one of the following strings:
+ "hisilicon,inno-usb2-phy",
+ "hisilicon,hi3798cv200-usb2-phy".
+- reg: Should be the address space for PHY configuration register in peripheral
+ controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
+- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
+ reference clock.
+- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
+ signal.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+
+The INNO USB2 PHY device should be a child node of peripheral controller that
+contains the PHY configuration register, and each device suppports up to 2 PHY
+ports which are represented as child nodes of INNO USB2 PHY device.
+
+Required properties for PHY port node:
+- reg: The PHY port instance number.
+- #phy-cells: Defined by generic PHY bindings. Must be 0.
+- resets: The phandle and reset specifier pair for PHY port reset signal.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+
+perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ usb2_phy1: usb2-phy@120 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x120 0x4>;
+ clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+ resets = <&crg 0xbc 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy1_port0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 8>;
+ };
+
+ usb2_phy1_port1: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 9>;
+ };
+ };
+
+ usb2_phy2: usb2-phy@124 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x124 0x4>;
+ clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+ resets = <&crg 0xbc 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy2_port0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 10>;
+ };
+ };
+};
diff --git a/dts/Bindings/phy/phy-mapphone-mdm6600.txt b/dts/Bindings/phy/phy-mapphone-mdm6600.txt
new file mode 100644
index 0000000..29427d4
--- /dev/null
+++ b/dts/Bindings/phy/phy-mapphone-mdm6600.txt
@@ -0,0 +1,29 @@
+Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
+
+Required properties:
+- compatible Must be "motorola,mapphone-mdm6600"
+- enable-gpios GPIO to enable the USB PHY
+- power-gpios GPIO to power on the device
+- reset-gpios GPIO to reset the device
+- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
+ normal mode versus USB flashing mode
+- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
+- motorola,status-gpios Three GPIOs to read the power state of the MDM6600
+
+Example:
+
+usb-phy {
+ compatible = "motorola,mapphone-mdm6600";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+};
diff --git a/dts/Bindings/phy/phy-mtk-tphy.txt b/dts/Bindings/phy/phy-mtk-tphy.txt
index 41e09ed..0d34b2b 100644
--- a/dts/Bindings/phy/phy-mtk-tphy.txt
+++ b/dts/Bindings/phy/phy-mtk-tphy.txt
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
- reg : offset and length of register shared by multiple ports,
exclude port's private register. It is needed on mt2701
and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef : coefficient for slew rate calibrate, depends on
+ SoC process
Required properties (port (child) node):
- reg : address and length of the register set for the port.
diff --git a/dts/Bindings/phy/phy-rockchip-typec.txt b/dts/Bindings/phy/phy-rockchip-typec.txt
index 6ea867e..960da7f 100644
--- a/dts/Bindings/phy/phy-rockchip-typec.txt
+++ b/dts/Bindings/phy/phy-rockchip-typec.txt
@@ -14,25 +14,9 @@ Required properties:
- resets : a list of phandle + reset specifier pairs
- reset-names : string reset name, must be:
"uphy", "uphy-pipe", "uphy-tcphy"
- - extcon : extcon specifier for the Power Delivery
-Note, there are 2 type-c phys for RK3399, and they are almost identical, except
-these registers(description below), every register node contains 3 sections:
-offset, enable bit, write mask bit.
- - rockchip,typec-conn-dir : the register of type-c connector direction,
- for type-c phy0, it must be <0xe580 0 16>;
- for type-c phy1, it must be <0xe58c 0 16>;
- - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable
- control.
- for type-c phy0, it must be <0xe580 3 19>;
- for type-c phy1, it must be <0xe58c 3 19>;
- - rockchip,external-psm : the register of type-c phy external psm clock
- selection.
- for type-c phy0, it must be <0xe588 14 30>;
- for type-c phy1, it must be <0xe594 14 30>;
- - rockchip,pipe-status : the register of type-c phy pipe status.
- for type-c phy0, it must be <0xe5c0 0 0>;
- for type-c phy1, it must be <0xe5c0 16 16>;
+Optional properties:
+ - extcon : extcon specifier for the Power Delivery
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify dp or usb3 port,
@@ -43,6 +27,13 @@ Required nodes : a sub-node is required for each port the phy provides.
Required properties (port (child) node):
- #phy-cells : must be 0, See ./phy-bindings.txt for details.
+Deprecated properties, do not use in new device tree sources, these
+properties are determined by the compatible value:
+ - rockchip,typec-conn-dir
+ - rockchip,usb3tousb2-en
+ - rockchip,external-psm
+ - rockchip,pipe-status
+
Example:
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
@@ -58,10 +49,6 @@ Example:
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,typec-conn-dir = <0xe580 0 16>;
- rockchip,usb3tousb2-en = <0xe580 3 19>;
- rockchip,external-psm = <0xe588 14 30>;
- rockchip,pipe-status = <0xe5c0 0 0>;
tcphy0_dp: dp-port {
#phy-cells = <0>;
@@ -86,10 +73,6 @@ Example:
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,typec-conn-dir = <0xe58c 0 16>;
- rockchip,usb3tousb2-en = <0xe58c 3 19>;
- rockchip,external-psm = <0xe594 14 30>;
- rockchip,pipe-status = <0xe5c0 16 16>;
tcphy1_dp: dp-port {
#phy-cells = <0>;
diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.txt b/dts/Bindings/phy/phy-stm32-usbphyc.txt
new file mode 100644
index 0000000..725ae71
--- /dev/null
+++ b/dts/Bindings/phy/phy-stm32-usbphyc.txt
@@ -0,0 +1,73 @@
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _________________ HOST controller
+ | _ |
+ | / 1|________________|
+ |_ PHY port#2 ----| |________________
+ | \_0| |
+ |_ UTMI switch_______| OTG controller
+
+
+Phy provider node
+=================
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- #address-cells: number of address cells for phys sub-nodes, must be <1>
+- #size-cells: number of size cells for phys sub-nodes, must be <0>
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+
+Required nodes: one sub-node per port the controller provides.
+
+Phy sub-nodes
+==============
+
+Required properties:
+- reg: phy port index
+- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
+ see phy-bindings.txt in the same directory.
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
+ port#1 and must be <1> for PHY port#2, to select USB controller
+
+
+Example:
+ usbphyc: usb-phy@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc_clk USBPHY_K>;
+ resets = <&rcc_rst USBPHY_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphyc_port0: usb-phy@0 {
+ reg = <0>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>
+ #phy-cells = <0>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ reg = <1>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/qcom-qmp-phy.txt b/dts/Bindings/phy/qcom-qmp-phy.txt
index b6a9f2b..dcf1b8f 100644
--- a/dts/Bindings/phy/qcom-qmp-phy.txt
+++ b/dts/Bindings/phy/qcom-qmp-phy.txt
@@ -8,7 +8,8 @@ Required properties:
- compatible: compatible list, contains:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
+ "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy.
- reg: offset and length of register set for PHY's common serdes block.
@@ -25,10 +26,13 @@ Required properties:
- clock-names: "cfg_ahb" for phy config clock,
"aux" for phy aux clock,
"ref" for 19.2 MHz ref clk,
+ "com_aux" for phy common block aux clock,
For "qcom,msm8996-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
+ For "qcom,qmp-v3-usb3-phy" must contain:
+ "aux", "cfg_ahb", "ref", "com_aux".
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
diff --git a/dts/Bindings/phy/qcom-qusb2-phy.txt b/dts/Bindings/phy/qcom-qusb2-phy.txt
index aa0fcb0..42c9742 100644
--- a/dts/Bindings/phy/qcom-qusb2-phy.txt
+++ b/dts/Bindings/phy/qcom-qusb2-phy.txt
@@ -4,7 +4,10 @@ Qualcomm QUSB2 phy controller
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
+ - compatible: compatible list, contains
+ "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
+ "qcom,qusb2-v2-phy" for QUSB2 V2 PHY.
+
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
diff --git a/dts/Bindings/phy/rcar-gen3-phy-usb2.txt b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
index 99b651b..dbd137c 100644
--- a/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
@@ -8,6 +8,8 @@ Required properties:
SoC.
"renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
SoC.
+ "renesas,usb2-phy-r8a77965" if the device is a part of an
+ R8A77965 SoC.
"renesas,usb2-phy-r8a77995" if the device is a part of an
R8A77995 SoC.
"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
diff --git a/dts/Bindings/phy/rcar-gen3-phy-usb3.txt b/dts/Bindings/phy/rcar-gen3-phy-usb3.txt
index f94cea4..47dd296 100644
--- a/dts/Bindings/phy/rcar-gen3-phy-usb3.txt
+++ b/dts/Bindings/phy/rcar-gen3-phy-usb3.txt
@@ -11,6 +11,8 @@ Required properties:
SoC.
"renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
SoC.
+ "renesas,r8a77965-usb3-phy" if the device is a part of an
+ R8A77965 SoC.
"renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
device.
diff --git a/dts/Bindings/phy/sun4i-usb-phy.txt b/dts/Bindings/phy/sun4i-usb-phy.txt
index c1ce5a0..07ca4ec 100644
--- a/dts/Bindings/phy/sun4i-usb-phy.txt
+++ b/dts/Bindings/phy/sun4i-usb-phy.txt
@@ -11,6 +11,7 @@ Required properties:
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun8i-r40-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
diff --git a/dts/Bindings/pinctrl/actions,s900-pinctrl.txt b/dts/Bindings/pinctrl/actions,s900-pinctrl.txt
new file mode 100644
index 0000000..fb87c7d
--- /dev/null
+++ b/dts/Bindings/pinctrl/actions,s900-pinctrl.txt
@@ -0,0 +1,178 @@
+Actions Semi S900 Pin Controller
+
+This binding describes the pin controller found in the S900 SoC.
+
+Required Properties:
+
+- compatible: Should be "actions,s900-pinctrl"
+- reg: Should contain the register base address and size of
+ the pin controller.
+- clocks: phandle of the clock feeding the pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Pinmux functions are available only for the pin groups while pinconf
+parameters are available for both pin groups and individual pins.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+Required Properties:
+
+- pins: An array of strings, each string containing the name of a pin.
+ These pins are used for selecting the pull control and schmitt
+ trigger parameters. The following are the list of pins
+ available:
+
+ eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
+ eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
+ sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
+ i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
+ pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
+ eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
+ lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
+ lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
+ lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
+ lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
+ sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
+ sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
+ spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
+ uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
+ uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
+ uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
+ i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
+ csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
+ csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
+ dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
+ csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
+ sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
+ nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
+ nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
+ nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
+ nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
+ nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
+ nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
+
+- groups: An array of strings, each string containing the name of a pin
+ group. These pin groups are used for selecting the pinmux
+ functions.
+
+ lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
+ sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
+ rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
+ rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
+ i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
+ pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
+ eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
+ eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
+ lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
+ spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
+ uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
+ sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
+ uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
+ csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
+ dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
+ nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
+ csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
+
+
+ These pin groups are used for selecting the drive strength
+ parameters.
+
+ sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
+ rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
+ rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
+ sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
+ i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
+ lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
+ sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
+ spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
+ uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
+
+ These pin groups are used for selecting the slew rate
+ parameters.
+
+ sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
+ rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
+ rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
+ i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
+ pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
+ spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
+ uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
+ sensor0_sr
+
+- function: An array of strings, each string containing the name of the
+ pinmux functions. These functions can only be selected by
+ the corresponding pin groups. The following are the list of
+ pinmux functions available:
+
+ eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
+ uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
+ pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
+ sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
+ usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
+ nand1, spdif, sirq0, sirq1, sirq2
+
+Optional Properties:
+
+- bias-bus-hold: No arguments. The specified pins should retain the previous
+ state value.
+- bias-high-impedance: No arguments. The specified pins should be configured
+ as high impedance.
+- bias-pull-down: No arguments. The specified pins should be configured as
+ pull down.
+- bias-pull-up: No arguments. The specified pins should be configured as
+ pull up.
+- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
+ pins
+- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
+ pins
+- slew-rate: Integer. Sets slew rate for the specified pins.
+ Valid values are:
+ <0> - Slow
+ <1> - Fast
+- drive-strength: Integer. Selects the drive strength for the specified
+ pins in mA.
+ Valid values are:
+ <2>
+ <4>
+ <8>
+ <12>
+
+Example:
+
+ pinctrl: pinctrl@e01b0000 {
+ compatible = "actions,s900-pinctrl";
+ reg = <0x0 0xe01b0000 0x0 0x1000>;
+ clocks = <&cmu CLK_GPIO>;
+
+ uart2-default: uart2-default {
+ pinmux {
+ groups = "lvds_oep_odn_mfp";
+ function = "uart2";
+ };
+ pinconf {
+ groups = "lvds_oep_odn_drv";
+ drive-strength = <12>;
+ };
+ };
+ };
diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 09789fd..ed5eb54 100644
--- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt b/dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt
index 47284f8..678f509 100644
--- a/dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt
+++ b/dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt
@@ -19,8 +19,10 @@ Required subnode-properties:
Available functions and groups (function: group0, group1...):
gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
- spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
+ spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
+ uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
+ uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
+ uart5nocts
cpuclkout: cpuclkoutgrp0
udlclkout: udlclkoutgrp0
i2c1: i2c1grp0
@@ -32,12 +34,12 @@ Required subnode-properties:
spi0: spi0grp0
spi1: spi1grp0
pciedebug: pciedebuggrp0
- uart0: uart0grp0, uart0grp1
- uart1: uart1grp0
- uart2: uart2grp0, uart2grp1
+ uart0: uart0grp0, uart0grp1, uart0grp2
+ uart1: uart1grp0, uart1grp1
+ uart2: uart2grp0, uart2grp1, uart2grp2
uart3: uart3grp0
- uart4: uart4grp0
- uart5: uart5grp0
+ uart4: uart4grp0, uart4grp1
+ uart5: uart5grp0, uart5grp1, uart5nocts
nand: nandgrp0
sdio0: sdio0grp0
sdio1: sdio1grp0
diff --git a/dts/Bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx6sll-pinctrl.txt
new file mode 100644
index 0000000..175e893
--- /dev/null
+++ b/dts/Bindings/pinctrl/fsl,imx6sll-pinctrl.txt
@@ -0,0 +1,40 @@
+* Freescale i.MX6 SLL IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6sll-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+ imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
+ Reference Manual for detailed CONFIG settings.
+
+CONFIG bits definition:
+PAD_CTL_LVE (1 << 22)
+PAD_CTL_HYS (1 << 16)
+PAD_CTL_PUS_100K_DOWN (0 << 14)
+PAD_CTL_PUS_47K_UP (1 << 14)
+PAD_CTL_PUS_100K_UP (2 << 14)
+PAD_CTL_PUS_22K_UP (3 << 14)
+PAD_CTL_PUE (1 << 13)
+PAD_CTL_PKE (1 << 12)
+PAD_CTL_ODE (1 << 11)
+PAD_CTL_SPEED_LOW (0 << 6)
+PAD_CTL_SPEED_MED (1 << 6)
+PAD_CTL_SPEED_HIGH (3 << 6)
+PAD_CTL_DSE_DISABLE (0 << 3)
+PAD_CTL_DSE_260ohm (1 << 3)
+PAD_CTL_DSE_130ohm (2 << 3)
+PAD_CTL_DSE_87ohm (3 << 3)
+PAD_CTL_DSE_65ohm (4 << 3)
+PAD_CTL_DSE_52ohm (5 << 3)
+PAD_CTL_DSE_43ohm (6 << 3)
+PAD_CTL_DSE_37ohm (7 << 3)
+PAD_CTL_SRE_FAST (1 << 0)
+PAD_CTL_SRE_SLOW (0 << 0)
+
+Refer to imx6sll-pinfunc.h in device tree source folder for all available
+imx6sll PIN_FUNC_ID.
diff --git a/dts/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/dts/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
deleted file mode 100644
index cf9ccdf..0000000
--- a/dts/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-ImgTec TZ1090 PDC pin controller
-
-Required properties:
-- compatible: "img,tz1090-pdc-pinctrl"
-- reg: Should contain the register physical address and length of the
- SOC_GPIO_CONTROL registers in the PDC register region.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
-of subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function. For this reason, even seemingly boolean
-values are actually tristates in this binding: unspecified, off, or on.
-Unspecified is represented as an absent property, and off/on are represented as
-integer values 0 and 1.
-
-Required subnode-properties:
-- tz1090,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- tz1090,function: A string containing the name of the function to mux to the
- pin or group. Valid values for function names are listed below, including
- which pingroups can be muxed to them.
-- supported generic pinconfig properties (for further details see
- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- - bias-disable
- - bias-high-impedance
- - bias-bus-hold
- - bias-pull-up
- - bias-pull-down
- - input-schmitt-enable
- - input-schmitt-disable
- - drive-strength: Integer, control drive strength of pins in mA.
- 2: 2mA
- 4: 4mA
- 8: 8mA
- 12: 12mA
- - low-power-enable: Flag, power-on-start weak pull-down for invalid power.
- - low-power-disable: Flag, power-on-start weak pull-down disabled.
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the TZ1090 TRM for complete details regarding which groups
-support which functionality. The Linux pinctrl driver may also be a useful
-reference.
-
-Valid values for pin and group names are:
-
- pins:
-
- These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
- bias-bus-hold (which can also be provided to any of the groups below to set
- it for all gpio pins in that group).
-
- gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
-
- mux groups:
-
- These all support function.
-
- gpio0
- pins: gpio0.
- function: ir_mod_stable_out.
- gpio1
- pins: gpio1.
- function: ir_mod_power_out.
-
- drive groups:
-
- These support input-schmitt-enable, input-schmitt-disable,
- drive-strength, low-power-enable, and low-power-disable.
-
- pdc
- pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
- ext_power.
-
-Example:
-
- pinctrl_pdc: pinctrl@2006500 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pdc-pinctrl";
- reg = <0x02006500 0x100>;
- };
-
-Example board file extracts:
-
- &pinctrl_pdc {
- pinctrl-names = "default";
- pinctrl-0 = <&syswake_default>;
-
- syswake_default: syswakes {
- syswake_cfg {
- tz1090,pins = "sys_wake0",
- "sys_wake1",
- "sys_wake2";
- pull-up;
- };
- };
- irmod_default: irmod {
- gpio0_cfg {
- tz1090,pins = "gpio0";
- tz1090,function = "ir_mod_stable_out";
- };
- gpio1_cfg {
- tz1090,pins = "gpio1";
- tz1090,function = "ir_mod_power_out";
- };
- };
- };
-
- ir: ir@2006200 {
- pinctrl-names = "default";
- pinctrl-0 = <&irmod_default>;
- };
diff --git a/dts/Bindings/pinctrl/img,tz1090-pinctrl.txt b/dts/Bindings/pinctrl/img,tz1090-pinctrl.txt
deleted file mode 100644
index 2dfd9a3..0000000
--- a/dts/Bindings/pinctrl/img,tz1090-pinctrl.txt
+++ /dev/null
@@ -1,227 +0,0 @@
-ImgTec TZ1090 pin controller
-
-Required properties:
-- compatible: "img,tz1090-pinctrl"
-- reg: Should contain the register physical address and length of the pad
- configuration registers (CR_PADS_* and CR_IF_CTL0).
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-TZ1090's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function. For this reason, even seemingly boolean
-values are actually tristates in this binding: unspecified, off, or on.
-Unspecified is represented as an absent property, and off/on are represented as
-integer values 0 and 1.
-
-Required subnode-properties:
-- tz1090,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- tz1090,function: A string containing the name of the function to mux to the
- pin or group. Valid values for function names are listed below, including
- which pingroups can be muxed to them.
-- supported generic pinconfig properties (for further details see
- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- - bias-disable
- - bias-high-impedance
- - bias-bus-hold
- - bias-pull-up
- - bias-pull-down
- - input-schmitt-enable
- - input-schmitt-disable
- - drive-strength: Integer, control drive strength of pins in mA.
- 2: 2mA
- 4: 4mA
- 8: 8mA
- 12: 12mA
-
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the TZ1090 TRM for complete details regarding which groups
-support which functionality. The Linux pinctrl driver may also be a useful
-reference.
-
-Valid values for pin and group names are:
-
- gpio pins:
-
- These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
- bias-bus-hold (which can also be provided to any of the groups below to set
- it for all pins in that group).
-
- They also all support the some form of muxing. Any pins which are contained
- in one of the mux groups (see below) can be muxed only to the functions
- supported by the mux group. All other pins can be muxed to the "perip"
- function which enables them with their intended peripheral.
-
- Different pins in the same mux group cannot be muxed to different functions,
- however it is possible to mux only a subset of the pins in a mux group to a
- particular function and leave the remaining pins unmuxed. This is useful if
- the board connects certain pins in a group to other devices to be controlled
- by GPIO, and you don't want the usual peripheral to have any control of the
- pin.
-
- ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
- i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
- i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
- scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
- sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
- spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
- spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
- tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
- tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
- tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
- tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
- tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
- uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
-
- bias-high-impediance: supported.
- bias-pull-up: supported.
- bias-pull-down: supported.
- bias-bus-hold: supported.
- function: perip or those supported by pin's mux group.
-
- other pins:
-
- These other pins are part of various pin groups below, but can't be
- controlled as GPIOs. They do however support bias-high-impediance,
- bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
- to any of the groups below to set it for all pins in that group).
-
- clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
-
- bias-high-impediance: supported.
- bias-pull-up: supported.
- bias-pull-down: supported.
- bias-bus-hold: supported.
-
- mux groups:
-
- These all support function, and some support drive configs.
-
- afe
- pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
- ant_sel1, gain0, gain1, gain2, gain3, gain4,
- gain5, gain6, gain7.
- function: afe, ts_out_0.
- input-schmitt-enable: supported.
- input-schmitt-disable: supported.
- drive-strength: supported.
- pdm_d
- pins: pdm_d.
- function: pdm_dac, usb_vbus.
- sdh
- pins: sdh_cd, sdh_wp, sdh_clk_in.
- function: sdh, sdio.
- sdio
- pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
- sdio_d3.
- function: sdio, sdh.
- spi1_cs2
- pins: spi1_cs2.
- function: spi1_cs2, usb_vbus.
- tft
- pins: tft_red0, tft_red1, tft_red2, tft_red3,
- tft_red4, tft_red5, tft_red6, tft_red7,
- tft_green0, tft_green1, tft_green2, tft_green3,
- tft_green4, tft_green5, tft_green6, tft_green7,
- tft_blue0, tft_blue1, tft_blue2, tft_blue3,
- tft_blue4, tft_blue5, tft_blue6, tft_blue7,
- tft_vdden_gd, tft_panelclk, tft_blank_ls,
- tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
- tft_pwrsave.
- function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
- lcd_trace, phy_ringosc.
- input-schmitt-enable: supported.
- input-schmitt-disable: supported.
- drive-strength: supported.
-
- drive groups:
-
- These all support input-schmitt-enable, input-schmitt-disable,
- and drive-strength.
-
- jtag
- pins: tck, trst, tdi, tdo, tms.
- scb1
- pins: scb1_sdat, scb1_sclk.
- scb2
- pins: scb2_sdat, scb2_sclk.
- spi0
- pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
- spi1
- pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
- uart
- pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
- uart1_txd, uart1_rxd.
- drive_i2s
- pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
- i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
- drive_pdm
- pins: clk_out0, pdm_b, pdm_a.
- drive_scb0
- pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
- drive_sdio
- pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
- sdh_wp, sdh_cd, sdh_clk_in.
-
- convenience groups:
-
- These are just convenient groupings of pins and don't support any drive
- configs.
-
- uart0
- pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
- uart1
- pins: uart1_rxd, uart1_txd.
- scb0
- pins: scb0_sclk, scb0_sdat.
- i2s
- pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
- i2s_lrclk_out, i2s_mclk.
-
-Example:
-
- pinctrl: pinctrl@2005800 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pinctrl";
- reg = <0x02005800 0xe4>;
- };
-
-Example board file extract:
-
- &pinctrl {
- uart0_default: uart0 {
- uart0_cfg {
- tz1090,pins = "uart0_rxd",
- "uart0_txd";
- tz1090,function = "perip";
- };
- };
- tft_default: tft {
- tft_cfg {
- tz1090,pins = "tft";
- tz1090,function = "tft";
- };
- };
- };
-
- uart@2004b00 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_default>;
- };
diff --git a/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt b/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
index 9c451c2..a5a8322 100644
--- a/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -45,6 +45,8 @@ Optional properties:
- first cell is the pin number
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as a interrupt controller.
+- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
+ the IRQ output as open drain active low.
Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
diff --git a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
index afa8a18..e7d6f81 100644
--- a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
@@ -76,12 +76,12 @@ Examples:
...
{
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
- syscfg_pctl_b: syscfg_pctl_b@1020c020 {
+ syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
diff --git a/dts/Bindings/pinctrl/qcom,sdm845-pinctrl.txt b/dts/Bindings/pinctrl/qcom,sdm845-pinctrl.txt
new file mode 100644
index 0000000..665aadb
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,sdm845-pinctrl.txt
@@ -0,0 +1,176 @@
+Qualcomm SDM845 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+SDM845 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode.
+
+ Valid pins are:
+ gpio0-gpio149
+ Supports mux, bias and drive-strength
+
+ sdc2_clk, sdc2_cmd, sdc2_data
+ Supports bias and drive-strength
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+
+ gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
+ atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
+ atest_usb12, atest_usb13, atest_usb2, atest_usb20,
+ atest_usb21, atest_usb22, atest_usb23, audio_ref,
+ btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
+ cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+ ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
+ gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
+ lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
+ mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
+ pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
+ pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
+ qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
+ qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
+ qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
+ qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
+ sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
+ tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
+ tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
+ tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
+ uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
+ uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
+ vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
+ wlan2_adc1,
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@3400000 {
+ compatible = "qcom,sdm845-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <GIC_SPI 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ qup9_active: qup9-active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup9";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index bb1790e..892d8fd 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -15,7 +15,7 @@ Required Properties:
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
+ - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
@@ -24,7 +24,9 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
+ - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
+ - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
index 2c46f30..9a06e1f 100644
--- a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -11,6 +11,7 @@ Required properies:
"st,stm32f429-pinctrl"
"st,stm32f469-pinctrl"
"st,stm32f746-pinctrl"
+ "st,stm32f769-pinctrl"
"st,stm32h743-pinctrl"
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
diff --git a/dts/Bindings/pmem/pmem-region.txt b/dts/Bindings/pmem/pmem-region.txt
new file mode 100644
index 0000000..5cfa4f0
--- /dev/null
+++ b/dts/Bindings/pmem/pmem-region.txt
@@ -0,0 +1,65 @@
+Device-tree bindings for persistent memory regions
+-----------------------------------------------------
+
+Persistent memory refers to a class of memory devices that are:
+
+ a) Usable as main system memory (i.e. cacheable), and
+ b) Retain their contents across power failure.
+
+Given b) it is best to think of persistent memory as a kind of memory mapped
+storage device. To ensure data integrity the operating system needs to manage
+persistent regions separately to the normal memory pool. To aid with that this
+binding provides a standardised interface for discovering where persistent
+memory regions exist inside the physical address space.
+
+Bindings for the region nodes:
+-----------------------------
+
+Required properties:
+ - compatible = "pmem-region"
+
+ - reg = <base, size>;
+ The reg property should specificy an address range that is
+ translatable to a system physical address range. This address
+ range should be mappable as normal system memory would be
+ (i.e cacheable).
+
+ If the reg property contains multiple address ranges
+ each address range will be treated as though it was specified
+ in a separate device node. Having multiple address ranges in a
+ node implies no special relationship between the two ranges.
+
+Optional properties:
+ - Any relevant NUMA assocativity properties for the target platform.
+
+ - volatile; This property indicates that this region is actually
+ backed by non-persistent memory. This lets the OS know that it
+ may skip the cache flushes required to ensure data is made
+ persistent after a write.
+
+ If this property is absent then the OS must assume that the region
+ is backed by non-volatile memory.
+
+Examples:
+--------------------
+
+ /*
+ * This node specifies one 4KB region spanning from
+ * 0x5000 to 0x5fff that is backed by non-volatile memory.
+ */
+ pmem@5000 {
+ compatible = "pmem-region";
+ reg = <0x00005000 0x00001000>;
+ };
+
+ /*
+ * This node specifies two 4KB regions that are backed by
+ * volatile (normal) memory.
+ */
+ pmem@6000 {
+ compatible = "pmem-region";
+ reg = < 0x00006000 0x00001000
+ 0x00008000 0x00001000 >;
+ volatile;
+ };
+
diff --git a/dts/Bindings/power/renesas,rcar-sysc.txt b/dts/Bindings/power/renesas,rcar-sysc.txt
index 8690f10..ab399e5 100644
--- a/dts/Bindings/power/renesas,rcar-sysc.txt
+++ b/dts/Bindings/power/renesas,rcar-sysc.txt
@@ -17,7 +17,9 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
+ - "renesas,r8a77965-sysc" (R-Car M3-N)
- "renesas,r8a77970-sysc" (R-Car V3M)
+ - "renesas,r8a77980-sysc" (R-Car V3H)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/dts/Bindings/power/reset/gpio-poweroff.txt b/dts/Bindings/power/reset/gpio-poweroff.txt
index e62d53d..6d8980c 100644
--- a/dts/Bindings/power/reset/gpio-poweroff.txt
+++ b/dts/Bindings/power/reset/gpio-poweroff.txt
@@ -27,10 +27,13 @@ Optional properties:
it to an output when the power-off handler is called. If this optional
property is not specified, the GPIO is initialized as an output in its
inactive state.
+- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is
+ specified, 3000 ms is used.
Examples:
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 4 0>;
+ timeout-ms = <3000>;
};
diff --git a/dts/Bindings/power/reset/ocelot-reset.txt b/dts/Bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 0000000..1b4213e
--- /dev/null
+++ b/dts/Bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,14 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
diff --git a/dts/Bindings/power/supply/axp20x_battery.txt b/dts/Bindings/power/supply/axp20x_battery.txt
index c248866..41916f6 100644
--- a/dts/Bindings/power/supply/axp20x_battery.txt
+++ b/dts/Bindings/power/supply/axp20x_battery.txt
@@ -4,12 +4,12 @@ Required Properties:
- compatible, one of:
"x-powers,axp209-battery-power-supply"
"x-powers,axp221-battery-power-supply"
+ "x-powers,axp813-battery-power-supply"
-This node is a subnode of the axp20x/axp22x PMIC.
+This node is a subnode of its respective PMIC DT node.
-The AXP20X and AXP22X can read the battery voltage, charge and discharge
-currents of the battery by reading ADC channels from the AXP20X/AXP22X
-ADC.
+The supported devices can read the battery voltage, charge and discharge
+currents of the battery by reading ADC channels from the ADC.
Example:
diff --git a/dts/Bindings/powerpc/nintendo/wii.txt b/dts/Bindings/powerpc/nintendo/wii.txt
index 36afa32..a3dc4b9 100644
--- a/dts/Bindings/powerpc/nintendo/wii.txt
+++ b/dts/Bindings/powerpc/nintendo/wii.txt
@@ -152,14 +152,7 @@ Nintendo Wii device tree
1.l) The General Purpose I/O (GPIO) controller node
- Represents the dual access 32 GPIO controller interface.
-
- Required properties:
-
- - #gpio-cells : <2>
- - compatible : should be "nintendo,hollywood-gpio"
- - reg : should contain the IPC registers location and length
- - gpio-controller
+ see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
1.m) The control node
diff --git a/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt b/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt
new file mode 100644
index 0000000..7d9d3f9
--- /dev/null
+++ b/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt
@@ -0,0 +1,25 @@
+Ingenic JZ47xx PWM Controller
+=============================
+
+Required properties:
+- compatible: One of:
+ * "ingenic,jz4740-pwm"
+ * "ingenic,jz4770-pwm"
+ * "ingenic,jz4780-pwm"
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
+ of the cells format.
+- clocks : phandle to the external clock.
+- clock-names : Should be "ext".
+
+
+Example:
+
+ pwm: pwm@10002000 {
+ compatible = "ingenic,jz4740-pwm";
+ reg = <0x10002000 0x1000>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&ext>;
+ clock-names = "ext";
+ };
diff --git a/dts/Bindings/pwm/pwm-stm32-lp.txt b/dts/Bindings/pwm/pwm-stm32-lp.txt
index f8338d1..bd23302 100644
--- a/dts/Bindings/pwm/pwm-stm32-lp.txt
+++ b/dts/Bindings/pwm/pwm-stm32-lp.txt
@@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
Required parameters:
- compatible: Must be "st,stm32-pwm-lp".
+- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
+ bindings defined in pwm.txt.
Optional properties:
- pinctrl-names: Set to "default".
@@ -18,6 +20,7 @@ Example:
...
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&lppwm1_pins>;
};
diff --git a/dts/Bindings/pwm/pwm-sun4i.txt b/dts/Bindings/pwm/pwm-sun4i.txt
index 51ff54c..2a1affb 100644
--- a/dts/Bindings/pwm/pwm-sun4i.txt
+++ b/dts/Bindings/pwm/pwm-sun4i.txt
@@ -7,6 +7,8 @@ Required properties:
- "allwinner,sun5i-a13-pwm"
- "allwinner,sun7i-a20-pwm"
- "allwinner,sun8i-h3-pwm"
+ - "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"
+ - "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/pwm/renesas,pwm-rcar.txt b/dts/Bindings/pwm/renesas,pwm-rcar.txt
index 74c1180..35a3b97 100644
--- a/dts/Bindings/pwm/renesas,pwm-rcar.txt
+++ b/dts/Bindings/pwm/renesas,pwm-rcar.txt
@@ -2,6 +2,8 @@
Required Properties:
- compatible: should be "renesas,pwm-rcar" and one of the following.
+ - "renesas,pwm-r8a7743": for RZ/G1M
+ - "renesas,pwm-r8a7745": for RZ/G1E
- "renesas,pwm-r8a7778": for R-Car M1A
- "renesas,pwm-r8a7779": for R-Car H1
- "renesas,pwm-r8a7790": for R-Car H2
@@ -9,6 +11,7 @@ Required Properties:
- "renesas,pwm-r8a7794": for R-Car E2
- "renesas,pwm-r8a7795": for R-Car H3
- "renesas,pwm-r8a7796": for R-Car M3-W
+ - "renesas,pwm-r8a77965": for R-Car M3-N
- "renesas,pwm-r8a77995": for R-Car D3
- reg: base address and length of the registers block for the PWM.
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
@@ -17,13 +20,15 @@ Required Properties:
- pinctrl-0: phandle, referring to a default pin configuration node.
- pinctrl-names: Set to "default".
-Example: R8A7790 (R-Car H2) PWM Timer node
+Example: R8A7743 (RZ/G1M) PWM Timer node
pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
#pwm-cells = <2>;
- clocks = <&mstp5_clks R8A7790_CLK_PWM>;
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
};
diff --git a/dts/Bindings/pwm/renesas,tpu-pwm.txt b/dts/Bindings/pwm/renesas,tpu-pwm.txt
index 1aadc80..d53a167 100644
--- a/dts/Bindings/pwm/renesas,tpu-pwm.txt
+++ b/dts/Bindings/pwm/renesas,tpu-pwm.txt
@@ -3,10 +3,12 @@
Required Properties:
- compatible: should be one of the following.
- - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
+ - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller.
- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
+ - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
+ - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
- - "renesas,tpu": for generic R-Car TPU PWM controller.
+ - "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller.
- reg: Base address and length of each memory resource used by the PWM
controller hardware module.
@@ -18,10 +20,10 @@ Required Properties:
Please refer to pwm.txt in this directory for details of the common PWM bindings
used by client devices.
-Example: R8A7740 (R-Car A1) TPU controller node
+Example: R8A7740 (R-Mobile A1) TPU controller node
tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
- reg = <0xe6600000 0x100>;
+ reg = <0xe6600000 0x148>;
#pwm-cells = <3>;
};
diff --git a/dts/Bindings/regulator/88pg86x.txt b/dts/Bindings/regulator/88pg86x.txt
new file mode 100644
index 0000000..13b7f49
--- /dev/null
+++ b/dts/Bindings/regulator/88pg86x.txt
@@ -0,0 +1,22 @@
+Marvell 88PG867/88PG868 voltage regulators
+
+Required properties:
+- compatible: one of "marvell,88pg867", "marvell,88pg868";
+- reg: I2C slave address.
+
+Optional subnodes for regulators: "buck1", "buck2", using common regulator
+bindings given in <Documentation/devicetree/bindings/regulator/regulator.txt>.
+
+Example:
+
+ pg868@19 {
+ compatible = "marvell,88pg868";
+ reg = <0x19>;
+
+ vcpu: buck1 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ };
diff --git a/dts/Bindings/regulator/fixed-regulator.txt b/dts/Bindings/regulator/fixed-regulator.txt
index 4fae41d..0c2a6c8 100644
--- a/dts/Bindings/regulator/fixed-regulator.txt
+++ b/dts/Bindings/regulator/fixed-regulator.txt
@@ -2,6 +2,7 @@ Fixed Voltage regulators
Required properties:
- compatible: Must be "regulator-fixed";
+- regulator-name: Defined in regulator.txt as optional, but required here.
Optional properties:
- gpio: gpio to use for enable control
diff --git a/dts/Bindings/regulator/gpio-regulator.txt b/dts/Bindings/regulator/gpio-regulator.txt
index dd1ed78..1f49615 100644
--- a/dts/Bindings/regulator/gpio-regulator.txt
+++ b/dts/Bindings/regulator/gpio-regulator.txt
@@ -2,6 +2,8 @@ GPIO controlled regulators
Required properties:
- compatible : Must be "regulator-gpio".
+- regulator-name : Defined in regulator.txt as optional, but required
+ here.
- states : Selection of available voltages and GPIO configs.
if there are no states, then use a fixed regulator
diff --git a/dts/Bindings/regulator/qcom,smd-rpm-regulator.txt b/dts/Bindings/regulator/qcom,smd-rpm-regulator.txt
index 4e3dfb5..58a1d97 100644
--- a/dts/Bindings/regulator/qcom,smd-rpm-regulator.txt
+++ b/dts/Bindings/regulator/qcom,smd-rpm-regulator.txt
@@ -23,7 +23,9 @@ Regulator nodes are identified by their compatible:
"qcom,rpm-pm8916-regulators"
"qcom,rpm-pm8941-regulators"
"qcom,rpm-pm8994-regulators"
+ "qcom,rpm-pm8998-regulators"
"qcom,rpm-pma8084-regulators"
+ "qcom,rpm-pmi8998-regulators"
- vdd_s1-supply:
- vdd_s2-supply:
@@ -131,6 +133,38 @@ Regulator nodes are identified by their compatible:
- vdd_s10-supply:
- vdd_s11-supply:
- vdd_s12-supply:
+- vdd_s13-supply:
+- vdd_l1_l27-supply:
+- vdd_l20_l24-supply:
+- vdd_l26-supply:
+- vdd_l2_l8_l17-supply:
+- vdd_l3_l11-supply:
+- vdd_l4_l5-supply:
+- vdd_l6-supply:
+- vdd_l7_l12_l14_l15-supply:
+- vdd_l9-supply:
+- vdd_l10_l23_l25-supply:
+- vdd_l13_l19_l21-supply:
+- vdd_l16_l28-supply:
+- vdd_l18_l22-supply:
+- vdd_lvs1_lvs2-supply:
+ Usage: optional (pmi8998 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
+- vdd_s1-supply:
+- vdd_s2-supply:
+- vdd_s3-supply:
+- vdd_s4-supply:
+- vdd_s5-supply:
+- vdd_s6-supply:
+- vdd_s7-supply:
+- vdd_s8-supply:
+- vdd_s9-supply:
+- vdd_s10-supply:
+- vdd_s11-supply:
+- vdd_s12-supply:
- vdd_l1_l11-supply:
- vdd_l2_l3_l4_l27-supply:
- vdd_l5_l7-supply:
@@ -148,6 +182,12 @@ Regulator nodes are identified by their compatible:
Definition: reference to regulator supplying the input pin, as
described in the data sheet
+- vdd_bob-supply:
+ Usage: optional (pmi8998 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
The regulator node houses sub-nodes for each regulator within the device. Each
sub-node is identified using the node's name, with valid values listed for each
of the pmics below.
@@ -169,11 +209,19 @@ pm8994:
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2
+pm8998:
+ s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4,
+ l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
+ l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2
+
pma8084:
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
+pmi8998:
+ bob
+
The content of each sub-node is defined by the standard binding for regulators -
see regulator.txt.
diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt
index a8014f3..294a0da 100644
--- a/dts/Bindings/reset/renesas,rst.txt
+++ b/dts/Bindings/reset/renesas,rst.txt
@@ -26,7 +26,9 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77965-rst" (R-Car M3-N)
- "renesas,r8a77970-rst" (R-Car V3M)
+ - "renesas,r8a77980-rst" (R-Car V3H)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/dts/Bindings/reset/st,stm32mp1-rcc.txt b/dts/Bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 0000000..b4edaf7
--- /dev/null
+++ b/dts/Bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+=======================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/dts/Bindings/rng/imx-rngc.txt b/dts/Bindings/rng/imx-rng.txt
index 93c7174..405c2b0 100644
--- a/dts/Bindings/rng/imx-rngc.txt
+++ b/dts/Bindings/rng/imx-rng.txt
@@ -1,15 +1,14 @@
-Freescale RNGC (Random Number Generator Version C)
-
-The driver also supports version B, which is mostly compatible
-to version C.
+Freescale RNGA/RNGB/RNGC (Random Number Generator Versions A, B and C)
Required properties:
- compatible : should be one of
+ "fsl,imx21-rnga"
+ "fsl,imx31-rnga" (backward compatible with "fsl,imx21-rnga")
"fsl,imx25-rngb"
"fsl,imx35-rngc"
- reg : offset and length of the register set of this block
-- interrupts : the interrupt number for the RNGC block
-- clocks : the RNGC clk source
+- interrupts : the interrupt number for the RNG block
+- clocks : the RNG clk source
Example:
diff --git a/dts/Bindings/rng/ks-sa-rng.txt b/dts/Bindings/rng/ks-sa-rng.txt
new file mode 100644
index 0000000..b7a65b4
--- /dev/null
+++ b/dts/Bindings/rng/ks-sa-rng.txt
@@ -0,0 +1,21 @@
+Keystone SoC Hardware Random Number Generator(HWRNG) Module
+
+On Keystone SoCs HWRNG module is a submodule of the Security Accelerator.
+
+- compatible: should be "ti,keystone-rng"
+- ti,syscon-sa-cfg: phandle to syscon node of the SA configuration registers.
+ This registers are shared between hwrng and crypto drivers.
+- clocks: phandle to the reference clocks for the subsystem
+- clock-names: functional clock name. Should be set to "fck"
+- reg: HWRNG module register space
+
+Example:
+/* K2HK */
+
+rng@24000 {
+ compatible = "ti,keystone-rng";
+ ti,syscon-sa-cfg = <&sa_config>;
+ clocks = <&clksa>;
+ clock-names = "fck";
+ reg = <0x24000 0x1000>;
+};
diff --git a/dts/Bindings/rng/omap_rng.txt b/dts/Bindings/rng/omap_rng.txt
index 9cf7876..ea434ce 100644
--- a/dts/Bindings/rng/omap_rng.txt
+++ b/dts/Bindings/rng/omap_rng.txt
@@ -13,7 +13,12 @@ Required properties:
- interrupts : the interrupt number for the RNG module.
Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
- clocks: the trng clock source. Only mandatory for the
- "inside-secure,safexcel-eip76" compatible.
+ "inside-secure,safexcel-eip76" compatible, the second clock is
+ needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for the second
+ one
+
Example:
/* AM335x */
diff --git a/dts/Bindings/rng/st,stm32-rng.txt b/dts/Bindings/rng/st,stm32-rng.txt
index 47f0417..1dfa7d5 100644
--- a/dts/Bindings/rng/st,stm32-rng.txt
+++ b/dts/Bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,10 @@ Required properties:
- interrupts : The designated IRQ line for the RNG
- clocks : The clock needed to enable the RNG
+Optional properties:
+- resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
+
Example:
rng: rng@50060800 {
diff --git a/dts/Bindings/rtc/isil,isl12026.txt b/dts/Bindings/rtc/isil,isl12026.txt
new file mode 100644
index 0000000..2e0be45
--- /dev/null
+++ b/dts/Bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device. The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57. The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+ value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+ value for proper operation.
+
+
+Example:
+
+ rtc@6f {
+ compatible = "isil,isl12026";
+ reg = <0x6f>;
+ isil,pwr-bsw = <0>;
+ isil,pwr-sbib = <1>;
+ }
diff --git a/dts/Bindings/scsi/hisilicon-sas.txt b/dts/Bindings/scsi/hisilicon-sas.txt
index df3bef7..8c6659e 100644
--- a/dts/Bindings/scsi/hisilicon-sas.txt
+++ b/dts/Bindings/scsi/hisilicon-sas.txt
@@ -53,6 +53,13 @@ Main node required properties:
Optional main node properties:
- hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
"am-max-transmissions" limitation.
+ - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis,
+ preshoot, and boost attenuation readings for the board. They
+ are used to describe the signal attenuation of the board. These
+ values' range is 7600 to 12400, and used to represent -24dB to
+ 24dB.
+ The formula is "y = (x-10000)/10000". For example, 10478
+ means 4.78dB.
Example:
sas0: sas@c1000000 {
diff --git a/dts/Bindings/serial/8250.txt b/dts/Bindings/serial/8250.txt
index dad3b2e..aeb6db4 100644
--- a/dts/Bindings/serial/8250.txt
+++ b/dts/Bindings/serial/8250.txt
@@ -24,6 +24,7 @@ Required properties:
- "ti,da830-uart"
- "aspeed,ast2400-vuart"
- "aspeed,ast2500-vuart"
+ - "nuvoton,npcm750-uart"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
diff --git a/dts/Bindings/serial/axis,etraxfs-uart.txt b/dts/Bindings/serial/axis,etraxfs-uart.txt
deleted file mode 100644
index 048c381..0000000
--- a/dts/Bindings/serial/axis,etraxfs-uart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-ETRAX FS UART
-
-Required properties:
-- compatible : "axis,etraxfs-uart"
-- reg: offset and length of the register set for the device.
-- interrupts: device interrupt
-
-Optional properties:
-- {dtr,dsr,rng,dcd}-gpios: specify a GPIO for DTR/DSR/RI/DCD
- line respectively.
-
-Example:
-
-serial@b00260000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb0026000 0x1000>;
- interrupts = <68>;
- dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
- rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&sysgpio 3 GPIO_ACTIVE_LOW>;
-};
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index cf504d0..ad962f4 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -43,6 +43,8 @@ Required properties:
- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
- "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
- "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
+ - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
+ - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART.
- "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
- "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
diff --git a/dts/Bindings/serial/st,stm32-usart.txt b/dts/Bindings/serial/st,stm32-usart.txt
index d150b04..9d3efed 100644
--- a/dts/Bindings/serial/st,stm32-usart.txt
+++ b/dts/Bindings/serial/st,stm32-usart.txt
@@ -15,6 +15,8 @@ Required properties:
Optional properties:
- pinctrl: The reference on the pins configuration
- st,hw-flow-ctrl: bool flag to enable hardware flow control.
+- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low,
+ linux,rs485-enabled-at-boot-time: see rs485.txt.
- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt
- dma-names: "rx" and/or "tx"
diff --git a/dts/Bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/dts/Bindings/soc/bcm/brcm,bcm2835-vchiq.txt
new file mode 100644
index 0000000..8dd7b3a
--- /dev/null
+++ b/dts/Bindings/soc/bcm/brcm,bcm2835-vchiq.txt
@@ -0,0 +1,16 @@
+Broadcom VCHIQ firmware services
+
+Required properties:
+
+- compatible: Should be "brcm,bcm2835-vchiq"
+- reg: Physical base address and length of the doorbell register pair
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Example:
+
+mailbox@7e00b840 {
+ compatible = "brcm,bcm2835-vchiq";
+ reg = <0x7e00b840 0xf>;
+ interrupts = <0 2>;
+};
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
index 76bf45b..d6fe16f 100644
--- a/dts/Bindings/soc/mediatek/scpsys.txt
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -21,6 +21,8 @@ Required properties:
- "mediatek,mt2712-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
+ - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
+ - "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@@ -28,10 +30,11 @@ Required properties:
- clock, clock-names: clocks according to the common clock binding.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
- Required clocks for MT2701: "mm", "mfg", "ethif"
+ Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
+ Required clocks for MT7622A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
diff --git a/dts/Bindings/sound/ak4458.txt b/dts/Bindings/sound/ak4458.txt
new file mode 100644
index 0000000..7839be7
--- /dev/null
+++ b/dts/Bindings/sound/ak4458.txt
@@ -0,0 +1,23 @@
+AK4458 audio DAC
+
+This device supports I2C mode.
+
+Required properties:
+
+- compatible : "asahi-kasei,ak4458"
+- reg : The I2C address of the device for I2C
+
+Optional properties:
+- reset-gpios: A GPIO specifier for the power down & reset pin
+- mute-gpios: A GPIO specifier for the soft mute pin
+
+Example:
+
+&i2c {
+ ak4458: dac@10 {
+ compatible = "asahi-kasei,ak4458";
+ reg = <0x10>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>
+ mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>
+ };
+};
diff --git a/dts/Bindings/sound/ak5558.txt b/dts/Bindings/sound/ak5558.txt
new file mode 100644
index 0000000..7d67ca6
--- /dev/null
+++ b/dts/Bindings/sound/ak5558.txt
@@ -0,0 +1,22 @@
+AK5558 8 channel differential 32-bit delta-sigma ADC
+
+This device supports I2C mode only.
+
+Required properties:
+
+- compatible : "asahi-kasei,ak5558"
+- reg : The I2C address of the device.
+
+Optional properties:
+
+- reset-gpios: A GPIO specifier for the power down & reset pin.
+
+Example:
+
+&i2c {
+ ak5558: adc@10 {
+ compatible = "asahi-kasei,ak5558";
+ reg = <0x10>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/dts/Bindings/sound/brcm,bcm2835-i2s.txt b/dts/Bindings/sound/brcm,bcm2835-i2s.txt
index 65783de..7bb0362 100644
--- a/dts/Bindings/sound/brcm,bcm2835-i2s.txt
+++ b/dts/Bindings/sound/brcm,bcm2835-i2s.txt
@@ -2,9 +2,8 @@
Required properties:
- compatible: "brcm,bcm2835-i2s"
-- reg: A list of base address and size entries:
- * The first entry should cover the PCM registers
- * The second entry should cover the PCM clock registers
+- reg: Should contain PCM registers location and length.
+- clocks: the (PCM) clock to use
- dmas: List of DMA controller phandle and DMA request line ordered pairs.
- dma-names: Identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
@@ -16,8 +15,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x20>,
- <0x7e101098 0x02>;
+ reg = <0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
diff --git a/dts/Bindings/sound/da7219.txt b/dts/Bindings/sound/da7219.txt
index 5b54d2d..c3df92d 100644
--- a/dts/Bindings/sound/da7219.txt
+++ b/dts/Bindings/sound/da7219.txt
@@ -25,6 +25,9 @@ Optional properties:
interrupt is to be used to wake system, otherwise "irq" should be used.
- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
+- #clock-cells : Should be set to '<0>', only one clock source provided;
+- clock-output-names : Name given for DAI clocks output;
+
- clocks : phandle and clock specifier for codec MCLK.
- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
@@ -83,6 +86,9 @@ Example:
VDDMIC-supply = <&reg_audio>;
VDDIO-supply = <&reg_audio>;
+ #clock-cells = <0>;
+ clock-output-names = "dai-clks";
+
clocks = <&clks 201>;
clock-names = "mclk";
diff --git a/dts/Bindings/sound/dmic.txt b/dts/Bindings/sound/dmic.txt
index f7bf656..e957b41 100644
--- a/dts/Bindings/sound/dmic.txt
+++ b/dts/Bindings/sound/dmic.txt
@@ -8,6 +8,7 @@ Required properties:
Optional properties:
- dmicen-gpios: GPIO specifier for dmic to control start and stop
- num-channels: Number of microphones on this DAI
+ - wakeup-delay-ms: Delay (in ms) after enabling the DMIC
Example node:
@@ -15,4 +16,5 @@ Example node:
compatible = "dmic-codec";
dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
num-channels = <1>;
+ wakeup-delay-ms <50>;
};
diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt
index f749e27..c60a573 100644
--- a/dts/Bindings/sound/fsl-asoc-card.txt
+++ b/dts/Bindings/sound/fsl-asoc-card.txt
@@ -28,7 +28,6 @@ The compatible list for this generic sound card currently:
(compatible with CS4271 and CS4272)
"fsl,imx-audio-wm8962"
- (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt)
"fsl,imx-audio-sgtl5000"
(compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
diff --git a/dts/Bindings/sound/imx-audio-wm8962.txt b/dts/Bindings/sound/imx-audio-wm8962.txt
deleted file mode 100644
index acea71b..0000000
--- a/dts/Bindings/sound/imx-audio-wm8962.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-Freescale i.MX audio complex with WM8962 codec
-
-Required properties:
-
- - compatible : "fsl,imx-audio-wm8962"
-
- - model : The user-visible name of this sound complex
-
- - ssi-controller : The phandle of the i.MX SSI controller
-
- - audio-codec : The phandle of the WM8962 audio codec
-
- - audio-routing : A list of the connections between audio components.
- Each entry is a pair of strings, the first being the
- connection's sink, the second being the connection's
- source. Valid names could be power supplies, WM8962
- pins, and the jacks on the board:
-
- Power supplies:
- * Mic Bias
-
- Board connectors:
- * Mic Jack
- * Headphone Jack
- * Ext Spk
-
- - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
-
- - mux-ext-port : The external port of the i.MX audio muxer
-
-Note: The AUDMUX port numbering should start at 1, which is consistent with
-hardware manual.
-
-Example:
-
-sound {
- compatible = "fsl,imx6q-sabresd-wm8962",
- "fsl,imx-audio-wm8962";
- model = "wm8962-audio";
- ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
- audio-routing =
- "Headphone Jack", "HPOUTL",
- "Headphone Jack", "HPOUTR",
- "Ext Spk", "SPKOUTL",
- "Ext Spk", "SPKOUTR",
- "MICBIAS", "AMIC",
- "IN3R", "MICBIAS",
- "DMIC", "MICBIAS",
- "DMICDAT", "DMIC";
- mux-int-port = <2>;
- mux-ext-port = <3>;
-};
diff --git a/dts/Bindings/sound/max98090.txt b/dts/Bindings/sound/max98090.txt
index 4e3be66..7e1bbd5 100644
--- a/dts/Bindings/sound/max98090.txt
+++ b/dts/Bindings/sound/max98090.txt
@@ -16,6 +16,8 @@ Optional properties:
- clock-names: Should be "mclk"
+- #sound-dai-cells : should be 0.
+
- maxim,dmic-freq: Frequency at which to clock DMIC
- maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are:
diff --git a/dts/Bindings/sound/maxim,max9759.txt b/dts/Bindings/sound/maxim,max9759.txt
new file mode 100644
index 0000000..737a996
--- /dev/null
+++ b/dts/Bindings/sound/maxim,max9759.txt
@@ -0,0 +1,18 @@
+Maxim MAX9759 Speaker Amplifier
+===============================
+
+Required properties:
+- compatible : "maxim,max9759"
+- shutdown-gpios : the gpio connected to the shutdown pin
+- mute-gpios : the gpio connected to the mute pin
+- gain-gpios : the 2 gpios connected to the g1 and g2 pins
+
+Example:
+
+max9759: analog-amplifier {
+ compatible = "maxim,max9759";
+ shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ mute-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ gain-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>,
+ <&gpio3 25 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/Bindings/sound/mt2701-afe-pcm.txt b/dts/Bindings/sound/mt2701-afe-pcm.txt
index 6df87b9..e2f7f49 100644
--- a/dts/Bindings/sound/mt2701-afe-pcm.txt
+++ b/dts/Bindings/sound/mt2701-afe-pcm.txt
@@ -53,7 +53,7 @@ See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
Example:
audsys: audio-subsystem@11220000 {
- compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+ compatible = "mediatek,mt2701-audsys", "syscon";
...
afe: audio-controller {
diff --git a/dts/Bindings/sound/pcm1789.txt b/dts/Bindings/sound/pcm1789.txt
new file mode 100644
index 0000000..3c74ed2
--- /dev/null
+++ b/dts/Bindings/sound/pcm1789.txt
@@ -0,0 +1,22 @@
+Texas Instruments pcm1789 DT bindings
+
+PCM1789 is a simple audio codec that can be connected via
+I2C or SPI. Currently, only I2C bus is supported.
+
+Required properties:
+
+ - compatible: "ti,pcm1789"
+
+Required properties on I2C:
+
+ - reg: the I2C address
+ - reset-gpios: GPIO to control the RESET pin
+
+Examples:
+
+ audio-codec@4c {
+ compatible = "ti,pcm1789";
+ reg = <0x4c>;
+ reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ };
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index 5bed9a5..b86d790 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -351,6 +351,7 @@ Required properties:
- "renesas,rcar_sound-r8a7793" (R-Car M2-N)
- "renesas,rcar_sound-r8a7794" (R-Car E2)
- "renesas,rcar_sound-r8a7795" (R-Car H3)
+ - "renesas,rcar_sound-r8a7796" (R-Car M3-W)
- reg : Should contain the register physical address.
required register is
SRU/ADG/SSI if generation1
diff --git a/dts/Bindings/sound/rockchip,rk3288-hdmi-analog.txt b/dts/Bindings/sound/rockchip,rk3288-hdmi-analog.txt
index 2539e1d..e5430d1 100644
--- a/dts/Bindings/sound/rockchip,rk3288-hdmi-analog.txt
+++ b/dts/Bindings/sound/rockchip,rk3288-hdmi-analog.txt
@@ -22,7 +22,7 @@ Optionnal properties:
Example:
sound {
- compatible = "rockchip,rockchip-audio-es8388";
+ compatible = "rockchip,rk3288-hdmi-analog";
rockchip,model = "Analog audio output";
rockchip,i2s-controller = <&i2s>;
rockchip,audio-codec = <&es8388>;
diff --git a/dts/Bindings/sound/rohm,bd28623.txt b/dts/Bindings/sound/rohm,bd28623.txt
new file mode 100644
index 0000000..d84557c
--- /dev/null
+++ b/dts/Bindings/sound/rohm,bd28623.txt
@@ -0,0 +1,29 @@
+ROHM BD28623MUV Class D speaker amplifier for digital input
+
+This codec does not have any control buses such as I2C, it detect format and
+rate of I2S signal automatically. It has two signals that can be connected
+to GPIOs: reset and mute.
+
+Required properties:
+- compatible : should be "rohm,bd28623"
+- #sound-dai-cells: should be 0.
+- VCCA-supply : regulator phandle for the VCCA supply
+- VCCP1-supply : regulator phandle for the VCCP1 supply
+- VCCP2-supply : regulator phandle for the VCCP2 supply
+
+Optional properties:
+- reset-gpios : GPIO specifier for the active low reset line
+- mute-gpios : GPIO specifier for the active low mute line
+
+Example:
+
+ codec {
+ compatible = "rohm,bd28623";
+ #sound-dai-cells = <0>;
+
+ VCCA-supply = <&vcc_reg>;
+ VCCP1-supply = <&vcc_reg>;
+ VCCP2-supply = <&vcc_reg>;
+ reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ mute-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/sound/rt5651.txt b/dts/Bindings/sound/rt5651.txt
index 3875233..b852218 100644
--- a/dts/Bindings/sound/rt5651.txt
+++ b/dts/Bindings/sound/rt5651.txt
@@ -16,6 +16,23 @@ Optional properties:
- realtek,dmic-en
Boolean. true if dmic is used.
+- realtek,jack-detect-source
+ u32. Valid values:
+ 1: Use JD1_1 pin for jack-detect
+ 2: Use JD1_2 pin for jack-detect
+ 3: Use JD2 pin for jack-detect
+
+- realtek,over-current-threshold-microamp
+ u32, micbias over-current detection threshold in µA, valid values are
+ 600, 1500 and 2000µA.
+
+- realtek,over-current-scale-factor
+ u32, micbias over-current detection scale-factor, valid values are:
+ 0: Scale current by 0.5
+ 1: Scale current by 0.75
+ 2: Scale current by 1.0
+ 3: Scale current by 1.5
+
Pins on the device (for linking into audio routes) for RT5651:
* DMIC L1
diff --git a/dts/Bindings/sound/rt5665.txt b/dts/Bindings/sound/rt5665.txt
index 419c892..8df1705 100644
--- a/dts/Bindings/sound/rt5665.txt
+++ b/dts/Bindings/sound/rt5665.txt
@@ -1,10 +1,10 @@
-RT5665/RT5666/RT5668 audio CODEC
+RT5665/RT5666 audio CODEC
This device supports I2C only.
Required properties:
-- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668".
+- compatible : One of "realtek,rt5665", "realtek,rt5666".
- reg : The I2C address of the device.
diff --git a/dts/Bindings/sound/samsung,odroid.txt b/dts/Bindings/sound/samsung,odroid.txt
index 625b1b1..e9da220 100644
--- a/dts/Bindings/sound/samsung,odroid.txt
+++ b/dts/Bindings/sound/samsung,odroid.txt
@@ -2,8 +2,10 @@ Samsung Exynos Odroid XU3/XU4 audio complex with MAX98090 codec
Required properties:
- - compatible - "samsung,odroidxu3-audio" - for Odroid XU3 board,
- "samsung,odroidxu4-audio" - for Odroid XU4 board
+ - compatible - "hardkernel,odroid-xu3-audio" - for Odroid XU3 board,
+ "hardkernel,odroid-xu4-audio" - for Odroid XU4 board (deprecated),
+ "samsung,odroid-xu3-audio" - for Odroid XU3 board (deprecated),
+ "samsung,odroid-xu4-audio" - for Odroid XU4 board (deprecated)
- model - the user-visible name of this sound complex
- clocks - should contain entries matching clock names in the clock-names
property
@@ -35,7 +37,7 @@ Required sub-nodes:
Example:
sound {
- compatible = "samsung,odroidxu3-audio";
+ compatible = "hardkernel,odroid-xu3-audio";
model = "Odroid-XU3";
samsung,audio-routing =
"Headphone Jack", "HPL",
diff --git a/dts/Bindings/sound/samsung,tm2-audio.txt b/dts/Bindings/sound/samsung,tm2-audio.txt
index 94442e5..f5ccc12 100644
--- a/dts/Bindings/sound/samsung,tm2-audio.txt
+++ b/dts/Bindings/sound/samsung,tm2-audio.txt
@@ -4,9 +4,13 @@ Required properties:
- compatible : "samsung,tm2-audio"
- model : the user-visible name of this sound complex
- - audio-codec : the phandle of the wm5110 audio codec node,
- as described in ../mfd/arizona.txt
- - i2s-controller : the phandle of the I2S controller
+ - audio-codec : the first entry should be phandle of the wm5110 audio
+ codec node, as described in ../mfd/arizona.txt;
+ the second entry should be phandle of the HDMI
+ transmitter node
+ - i2s-controller : the list of phandle and argument tuples pointing to
+ I2S controllers, the first entry should be I2S0 and
+ the second one I2S1
- audio-amplifier : the phandle of the MAX98504 amplifier
- samsung,audio-routing : a list of the connections between audio components;
each entry is a pair of strings, the first being the
@@ -22,8 +26,8 @@ Example:
sound {
compatible = "samsung,tm2-audio";
- audio-codec = <&wm5110>;
- i2s-controller = <&i2s0>;
+ audio-codec = <&wm5110>, <&hdmi>;
+ i2s-controller = <&i2s0 0>, <&i2s1 0>;
audio-amplifier = <&max98504>;
mic-bias-gpios = <&gpr3 2 0>;
model = "wm5110";
diff --git a/dts/Bindings/sound/samsung-i2s.txt b/dts/Bindings/sound/samsung-i2s.txt
index bf100cd..a88cb00 100644
--- a/dts/Bindings/sound/samsung-i2s.txt
+++ b/dts/Bindings/sound/samsung-i2s.txt
@@ -7,7 +7,7 @@ Required SoC Specific Properties:
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
- samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
- playback, sterio channel capture, secondary fifo using internal
+ playback, stereo channel capture, secondary fifo using internal
or external dma, s/w reset control, internal mux for root clk src
and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
is to allow transfer of multiple channel audio data on single data line.
@@ -25,7 +25,7 @@ Required SoC Specific Properties:
These strings correspond 1:1 with the ordered pairs in dmas.
- clocks: Handle to iis clock and RCLK source clk.
- clock-names:
- i2s0 uses some base clks from CMU and some are from audio subsystem internal
+ i2s0 uses some base clocks from CMU and some are from audio subsystem internal
clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
"i2s_opclk1" as shown in the example below.
i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
@@ -36,9 +36,9 @@ Required SoC Specific Properties:
- #clock-cells: should be 1, this property must be present if the I2S device
is a clock provider in terms of the common clock bindings, described in
../clock/clock-bindings.txt.
-- clock-output-names: from the common clock bindings, names of the CDCLK
- I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
- "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively.
+- clock-output-names (deprecated): from the common clock bindings, names of
+ the CDCLK I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
+ "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices respectively.
There are following clocks available at the I2S device nodes:
CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock,
@@ -49,9 +49,10 @@ There are following clocks available at the I2S device nodes:
Refer to the SoC datasheet for availability of the above clocks.
The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
-in the IIS Multi Audio Interface (I2S0).
-Note: Old DTs may not have the #clock-cells, clock-output-names properties
-and then not use the I2S node as a clock supplier.
+in the IIS Multi Audio Interface.
+
+Note: Old DTs may not have the #clock-cells property and then not use the I2S
+node as a clock supplier.
Optional SoC Specific Properties:
@@ -59,6 +60,7 @@ Optional SoC Specific Properties:
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".
+- #sound-dai-cells: should be 1.
Example:
@@ -74,9 +76,9 @@ i2s0: i2s@3830000 {
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
- #clock-cells;
- clock-output-names = "i2s_cdclk0";
+ #clock-cells = <1>;
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
+ #sound-dai-cells = <1>;
};
diff --git a/dts/Bindings/sound/sgtl5000.txt b/dts/Bindings/sound/sgtl5000.txt
index 060cb4a..9a36c7e 100644
--- a/dts/Bindings/sound/sgtl5000.txt
+++ b/dts/Bindings/sound/sgtl5000.txt
@@ -5,6 +5,8 @@ Required properties:
- reg : the I2C address of the device
+- #sound-dai-cells: must be equal to 0
+
- clocks : the clock provider of SYS_MCLK
- VDDA-supply : the regulator provider of VDDA
@@ -40,6 +42,7 @@ Example:
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks 150>;
micbias-resistor-k-ohms = <2>;
micbias-voltage-m-volts = <2250>;
diff --git a/dts/Bindings/sound/snow.txt b/dts/Bindings/sound/snow.txt
index 6df74f1..80fd9a8 100644
--- a/dts/Bindings/sound/snow.txt
+++ b/dts/Bindings/sound/snow.txt
@@ -5,8 +5,17 @@ Required properties:
"google,snow-audio-max98090" or
"google,snow-audio-max98091" or
"google,snow-audio-max98095"
-- samsung,i2s-controller: The phandle of the Samsung I2S controller
-- samsung,audio-codec: The phandle of the audio codec
+- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller
+- samsung,audio-codec (deprecated): The phandle of the audio codec
+
+Required sub-nodes:
+
+ - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
+ controller
+ - 'codec' subnode with a 'sound-dai' property containing list of phandles
+ to the CODEC nodes, first entry must be the phandle of the MAX98090,
+ MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible
+ string) and the second entry must be the phandle of the HDMI IP block node
Optional:
- samsung,model: The name of the sound-card
diff --git a/dts/Bindings/sound/st,stm32-sai.txt b/dts/Bindings/sound/st,stm32-sai.txt
index b1acc1a..f301cdf 100644
--- a/dts/Bindings/sound/st,stm32-sai.txt
+++ b/dts/Bindings/sound/st,stm32-sai.txt
@@ -45,6 +45,12 @@ SAI subnodes Optional properties:
This property sets SAI sub-block as slave of another SAI sub-block.
Must contain the phandle and index of the sai sub-block providing
the synchronization.
+ - st,iec60958: support S/PDIF IEC6958 protocol for playback
+ IEC60958 protocol is not available for capture.
+ By default, custom protocol is assumed, meaning that protocol is
+ configured according to protocol defined in related DAI link node,
+ such as i2s, left justified, right justified, dsp and pdm protocols.
+ Note: ac97 protocol is not supported by SAI driver
The device node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in Documentation/devicetree/bindings/
diff --git a/dts/Bindings/sound/tda7419.txt b/dts/Bindings/sound/tda7419.txt
new file mode 100644
index 0000000..6b85ec3
--- /dev/null
+++ b/dts/Bindings/sound/tda7419.txt
@@ -0,0 +1,38 @@
+TDA7419 audio processor
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : "st,tda7419"
+- reg : the I2C address of the device.
+- vdd-supply : a regulator spec for the common power supply (8-10V)
+
+Optional properties:
+
+- st,mute-gpios : a GPIO spec for the MUTE pin.
+
+Pins on the device (for linking into audio routes):
+
+ * SE3L
+ * SE3R
+ * SE2L
+ * SE2R
+ * SE1L
+ * SE1R
+ * DIFFL
+ * DIFFR
+ * MIX
+ * OUTLF
+ * OUTRF
+ * OUTLR
+ * OUTRR
+ * OUTSW
+
+Example:
+
+ap: tda7419@44 {
+ compatible = "st,tda7419";
+ reg = <0x44>;
+ vdd-supply = <&vdd_9v0_reg>;
+};
diff --git a/dts/Bindings/sound/uniphier,aio.txt b/dts/Bindings/sound/uniphier,aio.txt
new file mode 100644
index 0000000..4ce68ed
--- /dev/null
+++ b/dts/Bindings/sound/uniphier,aio.txt
@@ -0,0 +1,45 @@
+Socionext UniPhier SoC audio driver
+
+The Socionext UniPhier audio subsystem consists of I2S and S/PDIF blocks in
+the same register space.
+
+Required properties:
+- compatible : should be one of the following:
+ "socionext,uniphier-ld11-aio"
+ "socionext,uniphier-ld20-aio"
+ "socionext,uniphier-pxs2-aio"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain I2S or S/PDIF interrupt.
+- pinctrl-names : should be "default".
+- pinctrl-0 : defined I2S signal pins for an external codec chip.
+- clock-names : should include following entries:
+ "aio"
+- clocks : a list of phandle, should contain an entry for each
+ entry in clock-names.
+- reset-names : should include following entries:
+ "aio"
+- resets : a list of phandle, should contain an entry for each
+ entry in reset-names.
+- #sound-dai-cells: should be 1.
+
+Optional properties:
+- socionext,syscon: a phandle, should contain soc-glue.
+ The soc-glue is used for changing mode of S/PDIF signal pin
+ to Output from Hi-Z. This property is optional if you use
+ I2S signal pins only.
+
+Example:
+ audio {
+ compatible = "socionext,uniphier-ld20-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_aout>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+
+ socionext,syscon = <&sg>;
+ };
diff --git a/dts/Bindings/sound/wm8524.txt b/dts/Bindings/sound/wm8524.txt
index 20c6200..0f05535 100644
--- a/dts/Bindings/sound/wm8524.txt
+++ b/dts/Bindings/sound/wm8524.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8524@0 {
+codec: wm8524 {
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
index 80710f0..3980632 100644
--- a/dts/Bindings/spi/sh-msiof.txt
+++ b/dts/Bindings/spi/sh-msiof.txt
@@ -10,6 +10,7 @@ Required properties:
"renesas,msiof-r8a7794" (R-Car E2)
"renesas,msiof-r8a7795" (R-Car H3)
"renesas,msiof-r8a7796" (R-Car M3-W)
+ "renesas,msiof-r8a77965" (R-Car M3-N)
"renesas,msiof-sh73a0" (SH-Mobile AG5)
"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
"renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
diff --git a/dts/Bindings/spi/spi-gpio.txt b/dts/Bindings/spi/spi-gpio.txt
index a95603b..52db562 100644
--- a/dts/Bindings/spi/spi-gpio.txt
+++ b/dts/Bindings/spi/spi-gpio.txt
@@ -1,18 +1,30 @@
SPI-GPIO devicetree bindings
+This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated
+GPIO lines.
+
Required properties:
- compatible: should be set to "spi-gpio"
- #address-cells: should be set to <0x1>
- ranges
- - gpio-sck: GPIO spec for the SCK line to use
- - gpio-miso: GPIO spec for the MISO line to use
- - gpio-mosi: GPIO spec for the MOSI line to use
+ - sck-gpios: GPIO spec for the SCK line to use
+ - miso-gpios: GPIO spec for the MISO line to use
+ - mosi-gpios: GPIO spec for the MOSI line to use
- cs-gpios: GPIOs to use for chipselect lines.
Not needed if num-chipselects = <0>.
- num-chipselects: Number of chipselect lines. Should be <0> if a single device
with no chip select is connected.
+Deprecated bindings:
+
+These legacy GPIO line bindings can alternatively be used to define the
+GPIO lines used, they should not be used in new device trees.
+
+ - gpio-sck: GPIO spec for the SCK line to use
+ - gpio-miso: GPIO spec for the MISO line to use
+ - gpio-mosi: GPIO spec for the MOSI line to use
+
Example:
spi {
@@ -20,9 +32,9 @@ Example:
#address-cells = <0x1>;
ranges;
- gpio-sck = <&gpio 95 0>;
- gpio-miso = <&gpio 98 0>;
- gpio-mosi = <&gpio 97 0>;
+ sck-gpios = <&gpio 95 0>;
+ miso-gpios = <&gpio 98 0>;
+ mosi-gpios = <&gpio 97 0>;
cs-gpios = <&gpio 125 0>;
num-chipselects = <1>;
diff --git a/dts/Bindings/timer/andestech,atcpit100-timer.txt b/dts/Bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 0000000..4c9ea59
--- /dev/null
+++ b/dts/Bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+------------------------------------------------------------------
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible : Should be "andestech,atcpit100"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+- clocks : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2>;
+ clocks = <&apb>;
+ clock-names = "PCLK";
+};
diff --git a/dts/Bindings/trivial-devices.txt b/dts/Bindings/trivial-devices.txt
index 2e3740f..763a280 100644
--- a/dts/Bindings/trivial-devices.txt
+++ b/dts/Bindings/trivial-devices.txt
@@ -75,6 +75,18 @@ maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
mcube,mc3230 mCube 3-axis 8-bit digital accelerometer
memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer
+microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k)
+microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k)
+microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k)
microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
diff --git a/dts/Bindings/usb/amlogic,dwc3.txt b/dts/Bindings/usb/amlogic,dwc3.txt
new file mode 100644
index 0000000..9a8b631
--- /dev/null
+++ b/dts/Bindings/usb/amlogic,dwc3.txt
@@ -0,0 +1,42 @@
+Amlogic Meson GX DWC3 USB SoC controller
+
+Required properties:
+- compatible: depending on the SoC this should contain one of:
+ * amlogic,meson-axg-dwc3
+ * amlogic,meson-gxl-dwc3
+- clocks: a handle for the "USB general" clock
+- clock-names: must be "usb_general"
+- resets: a handle for the shared "USB OTG" reset line
+- reset-names: must be "usb_otg"
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+PHY documentation is provided in the following places:
+- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
+- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
+
+Example device nodes:
+ usb0: usb@ff500000 {
+ compatible = "amlogic,meson-axg-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>;
+ clock-names = "usb_general";
+ resets = <&reset RESET_USB_OTG>;
+ reset-names = "usb_otg";
+
+ dwc3: dwc3@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+ phys = <&usb3_phy>, <&usb2_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt
index 44e8bab..0dbd308 100644
--- a/dts/Bindings/usb/dwc3.txt
+++ b/dts/Bindings/usb/dwc3.txt
@@ -57,6 +57,22 @@ Optional properties:
- snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
register for post-silicon frame length adjustment when the
fladj_30mhz_sdbnd signal is invalid or incorrect.
+ - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode
+ only. Set this and rx-max-burst-prd to a valid,
+ non-zero value 1-16 (DWC_usb31 programming guide
+ section 1.2.4) to enable periodic ESS RX threshold.
+ - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set
+ this and rx-thr-num-pkt-prd to a valid, non-zero value
+ 1-16 (DWC_usb31 programming guide section 1.2.4) to
+ enable periodic ESS RX threshold.
+ - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode
+ only. Set this and tx-max-burst-prd to a valid,
+ non-zero value 1-16 (DWC_usb31 programming guide
+ section 1.2.3) to enable periodic ESS TX threshold.
+ - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set
+ this and tx-thr-num-pkt-prd to a valid, non-zero value
+ 1-16 (DWC_usb31 programming guide section 1.2.3) to
+ enable periodic ESS TX threshold.
- <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
diff --git a/dts/Bindings/usb/mediatek,mtk-xhci.txt b/dts/Bindings/usb/mediatek,mtk-xhci.txt
index 88d9f4a..266c2d9 100644
--- a/dts/Bindings/usb/mediatek,mtk-xhci.txt
+++ b/dts/Bindings/usb/mediatek,mtk-xhci.txt
@@ -32,7 +32,7 @@ Required properties:
"mcu_ck": mcu_bus clock for register access,
"dma_ck": dma_bus clock for data transfer by DMA
- - phys : a list of phandle + phy specifier pairs
+ - phys : see usb-hcd.txt in the current directory
Optional properties:
- wakeup-source : enable USB remote wakeup;
@@ -52,6 +52,9 @@ Optional properties:
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- imod-interval-ns: default interrupt moderation interval is 5000ns
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
usb30: usb@11270000 {
compatible = "mediatek,mt8173-xhci";
diff --git a/dts/Bindings/usb/mediatek,mtu3.txt b/dts/Bindings/usb/mediatek,mtu3.txt
index d589a1e..3382b5c 100644
--- a/dts/Bindings/usb/mediatek,mtu3.txt
+++ b/dts/Bindings/usb/mediatek,mtu3.txt
@@ -17,7 +17,7 @@ Required properties:
- clock-names : must contain "sys_ck" for clock of controller,
the following clocks are optional:
"ref_ck", "mcu_ck" and "dam_ck";
- - phys : a list of phandle + phy specifier pairs
+ - phys : see usb-hcd.txt in the current directory
- dr_mode : should be one of "host", "peripheral" or "otg",
refer to usb/generic.txt
@@ -53,6 +53,9 @@ Optional properties:
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
bit1 for u3port1, ... etc;
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Sub-nodes:
The xhci should be added as subnode to mtu3 as shown in the following example
if host mode is enabled. The DT binding details of xhci can be found in:
diff --git a/dts/Bindings/usb/usb-ehci.txt b/dts/Bindings/usb/usb-ehci.txt
index 3efde12..0f1b753 100644
--- a/dts/Bindings/usb/usb-ehci.txt
+++ b/dts/Bindings/usb/usb-ehci.txt
@@ -16,10 +16,12 @@ Optional properties:
- has-transaction-translator : boolean, set this if EHCI have a Transaction
Translator built into the root hub.
- clocks : a list of phandle + clock specifier pairs
- - phys : phandle + phy specifier pair
- - phy-names : "usb"
+ - phys : see usb-hcd.txt in the current directory
- resets : phandle + reset specifier pair
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example (Sequoia 440EPx):
ehci@e0000300 {
compatible = "ibm,usb-ehci-440epx", "usb-ehci";
diff --git a/dts/Bindings/usb/usb-hcd.txt b/dts/Bindings/usb/usb-hcd.txt
new file mode 100644
index 0000000..50529b8
--- /dev/null
+++ b/dts/Bindings/usb/usb-hcd.txt
@@ -0,0 +1,9 @@
+Generic USB HCD (Host Controller Device) Properties
+
+Optional properties:
+- phys: a list of all USB PHYs on this HCD
+
+Example:
+ &usb1 {
+ phys = <&usb2_phy1>, <&usb3_phy1>;
+ };
diff --git a/dts/Bindings/usb/usb-ohci.txt b/dts/Bindings/usb/usb-ohci.txt
index 09e70c8..a8d2103 100644
--- a/dts/Bindings/usb/usb-ohci.txt
+++ b/dts/Bindings/usb/usb-ohci.txt
@@ -13,10 +13,12 @@ Optional properties:
- remote-wakeup-connected: remote wakeup is wired on the platform
- num-ports : u32, to override the detected port count
- clocks : a list of phandle + clock specifier pairs
-- phys : phandle + phy specifier pair
-- phy-names : "usb"
+- phys : see usb-hcd.txt in the current directory
- resets : a list of phandle + reset specifier pairs
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
ohci0: usb@1c14400 {
diff --git a/dts/Bindings/usb/usb-uhci.txt b/dts/Bindings/usb/usb-uhci.txt
index 2981334..cc2e6f7 100644
--- a/dts/Bindings/usb/usb-uhci.txt
+++ b/dts/Bindings/usb/usb-uhci.txt
@@ -6,6 +6,9 @@ Required properties:
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
uhci@d8007b00 {
diff --git a/dts/Bindings/usb/usb-xhci.txt b/dts/Bindings/usb/usb-xhci.txt
index 1651483..c4c00df 100644
--- a/dts/Bindings/usb/usb-xhci.txt
+++ b/dts/Bindings/usb/usb-xhci.txt
@@ -33,6 +33,11 @@ Optional properties:
- usb3-lpm-capable: determines if platform is USB3 LPM capable
- quirk-broken-port-ped: set if the controller has broken port disable mechanism
- imod-interval-ns: default interrupt moderation interval is 5000ns
+ - phys : see usb-hcd.txt in the current directory
+
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
usb@f0931000 {
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index ae850d6..b5f978a 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -104,6 +104,7 @@ eeti eGalax_eMPIA Technology Inc
elan Elan Microelectronic Corp.
embest Shenzhen Embest Technology Co., Ltd.
emmicro EM Microelectronic
+emtrion emtrion GmbH
energymicro Silicon Laboratories (formerly Energy Micro AS)
engicam Engicam S.r.l.
epcos EPCOS AG
@@ -224,6 +225,7 @@ motorola Motorola, Inc.
moxa Moxa Inc.
mpl MPL AG
mqmaker mqmaker Inc.
+mscc Microsemi Corporation
msi Micro-Star International Co. Ltd.
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
multi-inno Multi-Inno Technology Co.,Ltd
diff --git a/dts/Bindings/watchdog/fsl-imx-wdt.txt b/dts/Bindings/watchdog/fsl-imx-wdt.txt
index 107280e..adc6b76 100644
--- a/dts/Bindings/watchdog/fsl-imx-wdt.txt
+++ b/dts/Bindings/watchdog/fsl-imx-wdt.txt
@@ -11,6 +11,7 @@ Optional properties:
detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
- fsl,ext-reset-output: If present the watchdog device is configured to
assert its external reset (WDOG_B) instead of issuing a software reset.
+- timeout-sec : Contains the watchdog timeout in seconds
Examples:
@@ -19,4 +20,5 @@ wdt@73f98000 {
reg = <0x73f98000 0x4000>;
interrupts = <58>;
big-endian;
+ timeout-sec = <20>;
};
diff --git a/dts/Bindings/watchdog/meson-wdt.txt b/dts/Bindings/watchdog/meson-wdt.txt
index 8a6d84c..7588cc3 100644
--- a/dts/Bindings/watchdog/meson-wdt.txt
+++ b/dts/Bindings/watchdog/meson-wdt.txt
@@ -9,9 +9,13 @@ Required properties:
"amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
Example:
wdt: watchdog@c1109900 {
compatible = "amlogic,meson6-wdt";
reg = <0xc1109900 0x8>;
+ timeout-sec = <10>;
};
diff --git a/dts/Bindings/watchdog/mtk-wdt.txt b/dts/Bindings/watchdog/mtk-wdt.txt
index 5b38a30..859dee1 100644
--- a/dts/Bindings/watchdog/mtk-wdt.txt
+++ b/dts/Bindings/watchdog/mtk-wdt.txt
@@ -11,9 +11,13 @@ Required properties:
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
Example:
wdt: watchdog@10000000 {
compatible = "mediatek,mt6589-wdt";
reg = <0x10000000 0x18>;
+ timeout-sec = <10>;
};
diff --git a/dts/Bindings/watchdog/nuvoton,npcm-wdt.txt b/dts/Bindings/watchdog/nuvoton,npcm-wdt.txt
new file mode 100644
index 0000000..6d59300
--- /dev/null
+++ b/dts/Bindings/watchdog/nuvoton,npcm-wdt.txt
@@ -0,0 +1,28 @@
+Nuvoton NPCM Watchdog
+
+Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
+The watchdog supports a pre-timeout interrupt that fires 10ms before the
+expiry.
+
+Required properties:
+- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg).
+- reg : Offset and length of the register set for the device.
+- interrupts : Contain the timer interrupt with flags for
+ falling edge.
+
+Required clocking property, have to be one of:
+- clocks : phandle of timer reference clock.
+- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
+ timer (usually 25000000).
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
+Example:
+
+timer@f000801c {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf000801c 0x4>;
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+};
diff --git a/dts/Bindings/watchdog/sirfsoc_wdt.txt b/dts/Bindings/watchdog/sirfsoc_wdt.txt
index 9cbc76c..0dce5e3 100644
--- a/dts/Bindings/watchdog/sirfsoc_wdt.txt
+++ b/dts/Bindings/watchdog/sirfsoc_wdt.txt
@@ -5,10 +5,14 @@ Required properties:
- reg: Address range of tick timer/WDT register set
- interrupts: interrupt number to the cpu
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Example:
timer@b0020000 {
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
+ timeout-sec = <30>;
};
diff --git a/dts/Bindings/watchdog/sunxi-wdt.txt b/dts/Bindings/watchdog/sunxi-wdt.txt
index 62dd5ba..ed11ce0 100644
--- a/dts/Bindings/watchdog/sunxi-wdt.txt
+++ b/dts/Bindings/watchdog/sunxi-wdt.txt
@@ -2,13 +2,19 @@ Allwinner SoCs Watchdog timer
Required properties:
-- compatible : should be either "allwinner,sun4i-a10-wdt" or
- "allwinner,sun6i-a31-wdt"
+- compatible : should be one of
+ "allwinner,sun4i-a10-wdt"
+ "allwinner,sun6i-a31-wdt"
+ "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Example:
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ timeout-sec = <10>;
};
diff --git a/dts/Bindings/x86/ce4100.txt b/dts/Bindings/x86/ce4100.txt
index b49ae59..cd1221b 100644
--- a/dts/Bindings/x86/ce4100.txt
+++ b/dts/Bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-------------
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <&lapic0>;
+The CPU nodes
+-------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
------------