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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-27 11:22:53 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-28 15:31:59 +0100 |
commit | 5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08 (patch) | |
tree | 0634f20e5f75f3d44242af47eebd9ea1ce0163f6 /dts/Bindings/display/msm | |
parent | db35548372eaee835fbf9bae68c08362ba59d49d (diff) | |
download | barebox-5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08.tar.gz barebox-5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08.tar.xz |
dts: update to v5.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/display/msm')
-rw-r--r-- | dts/Bindings/display/msm/dp-controller.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/display/msm/dpu-sdm845.yaml | 5 | ||||
-rw-r--r-- | dts/Bindings/display/msm/edp.txt | 56 |
3 files changed, 3 insertions, 60 deletions
diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml index 63e585f487..5457612ab1 100644 --- a/dts/Bindings/display/msm/dp-controller.yaml +++ b/dts/Bindings/display/msm/dp-controller.yaml @@ -17,6 +17,8 @@ properties: compatible: enum: - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp diff --git a/dts/Bindings/display/msm/dpu-sdm845.yaml b/dts/Bindings/display/msm/dpu-sdm845.yaml index b4ea7c92fb..0dca4b3d66 100644 --- a/dts/Bindings/display/msm/dpu-sdm845.yaml +++ b/dts/Bindings/display/msm/dpu-sdm845.yaml @@ -31,13 +31,11 @@ properties: clocks: items: - description: Display AHB clock from gcc - - description: Display AXI clock - description: Display core clock clock-names: items: - const: iface - - const: bus - const: core interrupts: @@ -160,9 +158,8 @@ examples: power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; + clock-names = "iface", "core"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; diff --git a/dts/Bindings/display/msm/edp.txt b/dts/Bindings/display/msm/edp.txt deleted file mode 100644 index eff9daff41..0000000000 --- a/dts/Bindings/display/msm/edp.txt +++ /dev/null @@ -1,56 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon eDP output - -Required properties: -- compatible: - * "qcom,mdss-edp" -- reg: Physical base address and length of the registers of controller and PLL -- reg-names: The names of register regions. The following regions are required: - * "edp" - * "pll_base" -- interrupts: The interrupt signal from the eDP block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core" - * "iface" - * "mdp_core" - * "pixel" - * "link" -- #clock-cells: The value should be 1. -- vdda-supply: phandle to vdda regulator device node -- lvl-vdd-supply: phandle to regulator device node which is used to supply power - to HPD receiving chip -- panel-en-gpios: GPIO pin to supply power to panel. -- panel-hpd-gpios: GPIO pin used for eDP hpd. - - -Example: - mdss_edp: qcom,mdss_edp@fd923400 { - compatible = "qcom,mdss-edp"; - reg-names = - "edp", - "pll_base"; - reg = <0xfd923400 0x700>, - <0xfd923a00 0xd4>; - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "pixel", - "iface", - "link", - "mdp_core"; - clocks = - <&mmcc MDSS_EDPAUX_CLK>, - <&mmcc MDSS_EDPPIXEL_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_EDPLINK_CLK>, - <&mmcc MDSS_MDP_CLK>; - #clock-cells = <1>; - vdda-supply = <&pma8084_l12>; - lvl-vdd-supply = <&lvl_vreg>; - panel-en-gpios = <&tlmm 137 0>; - panel-hpd-gpios = <&tlmm 103 0>; - }; |