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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:33:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:39 +0100 |
commit | a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch) | |
tree | 69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/Bindings/dma/arm-pl08x.txt | |
parent | 48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff) | |
download | barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.xz |
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/dma/arm-pl08x.txt')
-rw-r--r-- | dts/Bindings/dma/arm-pl08x.txt | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/dts/Bindings/dma/arm-pl08x.txt b/dts/Bindings/dma/arm-pl08x.txt new file mode 100644 index 0000000000..8a0097a029 --- /dev/null +++ b/dts/Bindings/dma/arm-pl08x.txt @@ -0,0 +1,54 @@ +* ARM PrimeCells PL080 and PL081 and derivatives DMA controller + +Required properties: +- compatible: "arm,pl080", "arm,primecell"; + "arm,pl081", "arm,primecell"; +- reg: Address range of the PL08x registers +- interrupt: The PL08x interrupt number +- clocks: The clock running the IP core clock +- clock-names: Must contain "apb_pclk" +- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs +- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs +- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents +- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents +- #dma-cells: must be <2>. First cell should contain the DMA request, + second cell should contain either 1 or 2 depending on + which AHB master that is used. + +Optional properties: +- dma-channels: contains the total number of DMA channels supported by the DMAC +- dma-requests: contains the total number of DMA requests supported by the DMAC +- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 + 64, 128 or 256 bytes are legal values +- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal + values + +Clients +Required properties: +- dmas: List of DMA controller phandle, request channel and AHB master id +- dma-names: Names of the aforementioned requested channels + +Example: + +dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; +}; + +device@40008000 { + ... + dmas = <&dmac0 0 2 + &dmac0 1 2>; + dma-names = "tx", "rx"; + ... +}; |