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authorSascha Hauer <s.hauer@pengutronix.de>2015-03-03 08:11:01 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-03-03 08:11:01 +0100
commiteaa819409db6ac80fbd7c3d36450b2d1bec93576 (patch)
tree6cd5e0c7f8abe121af237b701ee9e0e1b6f7e40d /dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt
parent0c9aadb6185e1d84746b632284bc89e4e4c80cd3 (diff)
downloadbarebox-eaa819409db6ac80fbd7c3d36450b2d1bec93576.tar.gz
dts: update to v4.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt')
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diff --git a/dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt b/dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt
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+Omap2/3 intc controller
+
+On TI omap2 and 3 the intc interrupt controller can provide
+96 or 128 IRQ signals to the ARM host depending on the SoC.
+
+Required Properties:
+- compatible: should be one of
+ "ti,omap2-intc"
+ "ti,omap3-intc"
+ "ti,dm814-intc"
+ "ti,dm816-intc"
+ "ti,am33xx-intc"
+
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+ source, should be 1 for intc
+- interrupts: interrupt reference to primary interrupt controller
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,omap3-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x48200000 0x1000>;
+ };