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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-12 10:22:44 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-14 09:33:24 +0200 |
commit | b01786baa849369ff2345c51e63857c952a01130 (patch) | |
tree | 43970a0ff46d32b8cad45b1dc3f3ca638e04fc5e /dts/Bindings/mailbox/mtk,adsp-mbox.yaml | |
parent | 610797b376e65475f7aed1218a085ff8701da474 (diff) | |
download | barebox-b01786baa849369ff2345c51e63857c952a01130.tar.gz barebox-b01786baa849369ff2345c51e63857c952a01130.tar.xz |
dts: update to v5.18-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mailbox/mtk,adsp-mbox.yaml')
-rw-r--r-- | dts/Bindings/mailbox/mtk,adsp-mbox.yaml | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/dts/Bindings/mailbox/mtk,adsp-mbox.yaml b/dts/Bindings/mailbox/mtk,adsp-mbox.yaml new file mode 100644 index 0000000000..fe454a1fba --- /dev/null +++ b/dts/Bindings/mailbox/mtk,adsp-mbox.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ADSP mailbox + +maintainers: + - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> + +description: | + The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC + to ommunicate with ADSP by passing messages through two mailbox channels. + The MTK ADSP mailbox IPC also provides the ability for one processor to + signal the other processor using interrupts. + +properties: + compatible: + items: + - const: mediatek,mt8195-adsp-mbox + + "#mbox-cells": + const: 0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - "#mbox-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + adsp_mailbox0:mailbox@10816000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0x10816000 0x1000>; + interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; + }; |