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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-21 09:53:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-21 09:53:29 +0200 |
| commit | 80700ad5bfd490f86b3e49ed8675e96218bbcd4c (patch) | |
| tree | 9d9e7d81c29d021eed65be978450d05727d5aae5 /dts/Bindings/memory-controllers/ddr | |
| parent | 4eefe44b3dea5b8eb778938e8f75c339ac5119fc (diff) | |
| download | barebox-80700ad5bfd490f86b3e49ed8675e96218bbcd4c.tar.gz barebox-80700ad5bfd490f86b3e49ed8675e96218bbcd4c.tar.xz | |
dts: update to v5.18-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers/ddr')
4 files changed, 4 insertions, 4 deletions
diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml index f3e62ee071..1daa665924 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR2 SDRAM AC timing parameters for a given speed-bin maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml index dd2141cad8..9d78f14060 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml index 97c3e988af..5c6512c1e1 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR3 SDRAM AC timing parameters for a given speed-bin maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml index c542f32c39..48908a1947 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: |