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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-02-27 09:40:19 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-01 14:29:51 +0100 |
commit | a9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch) | |
tree | 35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/Bindings/pci/cdns,cdns-pcie-host.txt | |
parent | 5ba0e42cb24afdf59d48930daf495c148312fc67 (diff) | |
download | barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.xz |
dts: update to v4.16-rc1
Also includeded:
ARM: dts: am33xx: do not delete no longer existing clocks
Several clocks are removed from the am33xx dts files with v4.16-rc1.
Remove the corresponding /delete-node/ directives aswell to avoid
dtc breakage.
Also included:
ARM: dts: imx6qdl: SolidRun: Fix upstream include
Upstream dts file way renamed, so change include name accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pci/cdns,cdns-pcie-host.txt')
-rw-r--r-- | dts/Bindings/pci/cdns,cdns-pcie-host.txt | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/dts/Bindings/pci/cdns,cdns-pcie-host.txt b/dts/Bindings/pci/cdns,cdns-pcie-host.txt new file mode 100644 index 0000000000..20a33f38f6 --- /dev/null +++ b/dts/Bindings/pci/cdns,cdns-pcie-host.txt @@ -0,0 +1,60 @@ +* Cadence PCIe host controller + +This PCIe controller inherits the base properties defined in +host-generic-pci.txt. + +Required properties: +- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. +- reg: Should contain the controller register base address, PCIe configuration + window base address, and AXI interface region base address respectively. +- reg-names: Must be "reg", "cfg" and "mem" respectively. +- #address-cells: Set to <3> +- #size-cells: Set to <2> +- device_type: Set to "pci" +- ranges: Ranges for the PCI memory and I/O regions +- #interrupt-cells: Set to <1> +- interrupt-map-mask and interrupt-map: Standard PCI properties to define the + mapping of the PCIe interface to interrupt numbers. + +Optional properties: +- cdns,max-outbound-regions: Set to maximum number of outbound regions + (default 32) +- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the + number of least significant bits kept during inbound (PCIe -> AXI) address + translations (default 32) +- vendor-id: The PCI vendor ID (16 bits, default is design dependent) +- device-id: The PCI device ID (16 bits, default is design dependent) + +Example: + +pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; +}; |