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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
commit | 2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch) | |
tree | 468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/Bindings/pwm | |
parent | 785f926d4527184194b6424bc39ce367e2cea7d8 (diff) | |
download | barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz |
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
-rw-r--r-- | dts/Bindings/pwm/ingenic,jz47xx-pwm.txt | 22 | ||||
-rw-r--r-- | dts/Bindings/pwm/pwm-mediatek.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/pwm/pwm-sprd.txt | 40 |
3 files changed, 42 insertions, 22 deletions
diff --git a/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt b/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt deleted file mode 100644 index 493bec80d5..0000000000 --- a/dts/Bindings/pwm/ingenic,jz47xx-pwm.txt +++ /dev/null @@ -1,22 +0,0 @@ -Ingenic JZ47xx PWM Controller -============================= - -Required properties: -- compatible: Should be "ingenic,jz4740-pwm" -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description - of the cells format. -- clocks : phandle to the external clock. -- clock-names : Should be "ext". - - -Example: - - pwm: pwm@10002000 { - compatible = "ingenic,jz4740-pwm"; - reg = <0x10002000 0x1000>; - - #pwm-cells = <3>; - - clocks = <&ext>; - clock-names = "ext"; - }; diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt index 991728cb46..c850153017 100644 --- a/dts/Bindings/pwm/pwm-mediatek.txt +++ b/dts/Bindings/pwm/pwm-mediatek.txt @@ -6,6 +6,8 @@ Required properties: - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. + - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC. + - "mediatek,mt8516-pwm": found on mt8516 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format. diff --git a/dts/Bindings/pwm/pwm-sprd.txt b/dts/Bindings/pwm/pwm-sprd.txt new file mode 100644 index 0000000000..16fa5a0962 --- /dev/null +++ b/dts/Bindings/pwm/pwm-sprd.txt @@ -0,0 +1,40 @@ +Spreadtrum PWM controller + +Spreadtrum SoCs PWM controller provides 4 PWM channels. + +Required properties: +- compatible : Should be "sprd,ums512-pwm". +- reg: Physical base address and length of the controller's registers. +- clocks: The phandle and specifier referencing the controller's clocks. +- clock-names: Should contain following entries: + "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3). + "enablen": for PWM channel n enable clock (n range: 0 ~ 3). +- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of + the cells format. + +Optional properties: +- assigned-clocks: Reference to the PWM clock entries. +- assigned-clock-parents: The phandle of the parent clock of PWM clock. + +Example: + pwms: pwm@32260000 { + compatible = "sprd,ums512-pwm"; + reg = <0 0x32260000 0 0x10000>; + clock-names = "pwm0", "enable0", + "pwm1", "enable1", + "pwm2", "enable2", + "pwm3", "enable3"; + clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, + <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, + <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, + <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; + assigned-clocks = <&aon_clk CLK_PWM0>, + <&aon_clk CLK_PWM1>, + <&aon_clk CLK_PWM2>, + <&aon_clk CLK_PWM3>; + assigned-clock-parents = <&ext_26m>, + <&ext_26m>, + <&ext_26m>, + <&ext_26m>; + #pwm-cells = <2>; + }; |