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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-05 12:56:25 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-07 11:41:05 +0100 |
commit | 6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef (patch) | |
tree | 5d16ca525c12dddb21d9c4750dfd1a1e354eb731 /dts/Bindings/pwm | |
parent | 93c4690b4921d3149db3fcf5b62a8aa5010a4ae7 (diff) | |
download | barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.gz barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.xz |
dts: update to v5.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
-rw-r--r-- | dts/Bindings/pwm/atmel-tcb-pwm.txt | 16 | ||||
-rw-r--r-- | dts/Bindings/pwm/intel,keembay-pwm.yaml | 47 | ||||
-rw-r--r-- | dts/Bindings/pwm/intel,lgm-pwm.yaml | 44 | ||||
-rw-r--r-- | dts/Bindings/pwm/pwm-mediatek.txt | 1 | ||||
-rw-r--r-- | dts/Bindings/pwm/pwm-mtk-disp.txt | 1 |
5 files changed, 93 insertions, 16 deletions
diff --git a/dts/Bindings/pwm/atmel-tcb-pwm.txt b/dts/Bindings/pwm/atmel-tcb-pwm.txt deleted file mode 100644 index 985fcc65f8..0000000000 --- a/dts/Bindings/pwm/atmel-tcb-pwm.txt +++ /dev/null @@ -1,16 +0,0 @@ -Atmel TCB PWM controller - -Required properties: -- compatible: should be "atmel,tcb-pwm" -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- tc-block: The Timer Counter block to use as a PWM chip. - -Example: - -pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; -}; diff --git a/dts/Bindings/pwm/intel,keembay-pwm.yaml b/dts/Bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 0000000000..ff6880a02c --- /dev/null +++ b/dts/Bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + }; diff --git a/dts/Bindings/pwm/intel,lgm-pwm.yaml b/dts/Bindings/pwm/intel,lgm-pwm.yaml new file mode 100644 index 0000000000..11a6065361 --- /dev/null +++ b/dts/Bindings/pwm/intel,lgm-pwm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LGM SoC PWM fan controller + +maintainers: + - Rahul Tanwar <rtanwar@maxlinear.com> + +properties: + compatible: + const: intel,lgm-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm: pwm@e0d00000 { + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + #pwm-cells = <2>; + clocks = <&cgu0 126>; + resets = <&rcu0 0x30 21>; + }; diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt index 29adff59c4..25ed214473 100644 --- a/dts/Bindings/pwm/pwm-mediatek.txt +++ b/dts/Bindings/pwm/pwm-mediatek.txt @@ -7,6 +7,7 @@ Required properties: - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. - "mediatek,mt7629-pwm": found on mt7629 SoC. + - "mediatek,mt8183-pwm": found on mt8183 SoC. - "mediatek,mt8516-pwm": found on mt8516 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of diff --git a/dts/Bindings/pwm/pwm-mtk-disp.txt b/dts/Bindings/pwm/pwm-mtk-disp.txt index 0521957c25..902b271891 100644 --- a/dts/Bindings/pwm/pwm-mtk-disp.txt +++ b/dts/Bindings/pwm/pwm-mtk-disp.txt @@ -4,6 +4,7 @@ Required properties: - compatible: should be "mediatek,<name>-disp-pwm": - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. + - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of |