diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-03-18 07:17:49 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-03-18 07:17:49 +0100 |
| commit | 65984ba7aa462ec08d9828774c3c29386c425472 (patch) | |
| tree | 773bf4958944d9410453bee0371096f4cf5b9ece /dts/Bindings/reset | |
| parent | 3cc8238ef792f4681eff28d408166f14552b0a03 (diff) | |
| download | barebox-65984ba7aa462ec08d9828774c3c29386c425472.tar.gz barebox-65984ba7aa462ec08d9828774c3c29386c425472.tar.xz | |
dts: update to v5.6-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/reset')
| -rw-r--r-- | dts/Bindings/reset/intel,rcu-gw.yaml | 6 | ||||
| -rw-r--r-- | dts/Bindings/reset/st,stm32mp1-rcc.txt | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/dts/Bindings/reset/intel,rcu-gw.yaml b/dts/Bindings/reset/intel,rcu-gw.yaml index 246dea8a2e..8ac4372826 100644 --- a/dts/Bindings/reset/intel,rcu-gw.yaml +++ b/dts/Bindings/reset/intel,rcu-gw.yaml @@ -23,7 +23,11 @@ properties: description: Global reset register offset and bit offset. allOf: - $ref: /schemas/types.yaml#/definitions/uint32-array - - maxItems: 2 + items: + - description: Register offset + - description: Register bit offset + minimum: 0 + maximum: 31 "#reset-cells": minimum: 2 diff --git a/dts/Bindings/reset/st,stm32mp1-rcc.txt b/dts/Bindings/reset/st,stm32mp1-rcc.txt index b4edaf7c7f..2880d5dda9 100644 --- a/dts/Bindings/reset/st,stm32mp1-rcc.txt +++ b/dts/Bindings/reset/st,stm32mp1-rcc.txt @@ -3,4 +3,4 @@ STMicroelectronics STM32MP1 Peripheral Reset Controller The RCC IP is both a reset and a clock controller. -Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml |