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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 13:27:45 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 16:23:06 +0200 |
| commit | a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1 (patch) | |
| tree | fe87198c6cc02e54d3131d087d2b9f7c3e96c689 /dts/Bindings/riscv | |
| parent | ba9de18c5f211678f5d0f67a0758c632ab774cca (diff) | |
| download | barebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.gz barebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.xz | |
dts: update to v5.13-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/riscv')
| -rw-r--r-- | dts/Bindings/riscv/microchip.yaml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/dts/Bindings/riscv/microchip.yaml b/dts/Bindings/riscv/microchip.yaml new file mode 100644 index 0000000000..3f981e8971 --- /dev/null +++ b/dts/Bindings/riscv/microchip.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/microchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC-based boards device tree bindings + +maintainers: + - Cyril Jean <Cyril.Jean@microchip.com> + - Lewis Hanly <lewis.hanly@microchip.com> + +description: + Microchip PolarFire SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,mpfs + +additionalProperties: true + +... |