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authorSascha Hauer <s.hauer@pengutronix.de>2019-10-15 10:55:58 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-10-15 10:55:58 +0200
commit2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch)
tree468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/src/arm/am3517.dtsi
parent785f926d4527184194b6424bc39ce367e2cea7d8 (diff)
downloadbarebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz
barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/am3517.dtsi')
-rw-r--r--dts/src/arm/am3517.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/dts/src/arm/am3517.dtsi b/dts/src/arm/am3517.dtsi
index 23ea381d36..bf3002009b 100644
--- a/dts/src/arm/am3517.dtsi
+++ b/dts/src/arm/am3517.dtsi
@@ -88,6 +88,30 @@
interrupts = <24>;
clocks = <&hecc_ck>;
};
+
+ /*
+ * On am3517 the OCP registers do not seem to be accessible
+ * similar to the omap34xx. Maybe SGX is permanently set to
+ * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
+ * write-only at 0x50000e10. We detect SGX based on the SGX
+ * revision register instead of the unreadable OCP revision
+ * register.
+ */
+ sgx_module: target-module@50000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x50000014 0x4>;
+ reg-names = "rev";
+ clocks = <&sgx_fck>, <&sgx_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50000000 0x4000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
};
};