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author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-25 11:22:32 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-28 09:08:46 +0200 |
commit | 00ce25c6dcdae5582ae4be37147ab33678adc995 (patch) | |
tree | 41c93102ae304a61738c31353e3cb5336ef0b297 /dts/src/arm/highbank.dts | |
parent | 0af79fbb6779921d3f1962773adb7fb57d3c89d4 (diff) | |
download | barebox-00ce25c6dcdae5582ae4be37147ab33678adc995.tar.gz barebox-00ce25c6dcdae5582ae4be37147ab33678adc995.tar.xz |
Add devicetree source files as of Linux-3.15-rc2
This adds the Linux dts files to barebox. The dts files are
generated from Ian Campbells device-tree-rebasing.git:
git://xenbits.xen.org/people/ianc/device-tree-rebasing.git
The dts are found in dts/ in the barebox repository and
will be updated from upstream regularly, probably for each upstream
-rc.
To keep the synchronization with upstream easy no changes to
the original files are allowed under dts/. Instead changes to
upstream dts files will be done using overlays in arch/$ARCH/dts/.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/highbank.dts')
-rw-r--r-- | dts/src/arm/highbank.dts | 142 |
1 files changed, 142 insertions, 0 deletions
diff --git a/dts/src/arm/highbank.dts b/dts/src/arm/highbank.dts new file mode 100644 index 0000000000..ed14aeac05 --- /dev/null +++ b/dts/src/arm/highbank.dts @@ -0,0 +1,142 @@ +/* + * Copyright 2011-2012 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + clock-ranges; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x900>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; + }; + + cpu@901 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x901>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + + cpu@902 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x902>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + + cpu@903 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x903>; + next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + soc { + ranges = <0x00000000 0x00000000 0xffffffff>; + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; + + timer@fff10600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfff10600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&a9periphclk>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xfff10620 0x20>; + interrupts = <1 14 0xf01>; + clocks = <&a9periphclk>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <0 70 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + }; + + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4 0 72 4>; + }; + + }; +}; + +/include/ "ecx-common.dtsi" |