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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-07 09:48:28 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-08 08:57:14 +0100 |
commit | 646d1a09f05689a3a4781112a3b3e4747d0ba231 (patch) | |
tree | fe48ab82140e06e495051098fde1d97a4b1e56d5 /dts/src/arm/r9a06g032.dtsi | |
parent | ebc406c1ab2be0e6002e1d8ccbc5c1377a882895 (diff) | |
download | barebox-646d1a09f05689a3a4781112a3b3e4747d0ba231.tar.gz barebox-646d1a09f05689a3a4781112a3b3e4747d0ba231.tar.xz |
dts: update to v4.20-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/r9a06g032.dtsi')
-rw-r--r-- | dts/src/arm/r9a06g032.dtsi | 88 |
1 files changed, 83 insertions, 5 deletions
diff --git a/dts/src/arm/r9a06g032.dtsi b/dts/src/arm/r9a06g032.dtsi index afe29c95a0..eaf94976ed 100644 --- a/dts/src/arm/r9a06g032.dtsi +++ b/dts/src/arm/r9a06g032.dtsi @@ -7,6 +7,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a06g032-sysctrl.h> / { compatible = "renesas,r9a06g032"; @@ -21,14 +22,14 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0>; - clocks = <&sysctrl 84>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <1>; - clocks = <&sysctrl 84>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; enable-method = "renesas,r9a06g032-smp"; cpu-release-addr = <0 0x4000c204>; }; @@ -77,13 +78,90 @@ }; uart0: serial@40060000 { - compatible = "snps,dw-apb-uart"; + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&sysctrl 146>; - clock-names = "baudclk"; + clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@40061000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40061000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@40062000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40062000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@50000000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50000000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@50001000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50001000 0x400>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart5: serial@50002000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50002000 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart6: serial@50003000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50003000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart7: serial@50004000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50004000 0x400>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; status = "disabled"; }; |