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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:33:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:39 +0100 |
commit | a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch) | |
tree | 69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/src/arm/stih410-clock.dtsi | |
parent | 48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff) | |
download | barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.xz |
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/stih410-clock.dtsi')
-rw-r--r-- | dts/src/arm/stih410-clock.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dts/src/arm/stih410-clock.dtsi b/dts/src/arm/stih410-clock.dtsi index 6b5803a300..d1f2acafc9 100644 --- a/dts/src/arm/stih410-clock.dtsi +++ b/dts/src/arm/stih410-clock.dtsi @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; |