diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-05 12:56:25 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-07 11:41:05 +0100 |
| commit | 6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef (patch) | |
| tree | 5d16ca525c12dddb21d9c4750dfd1a1e354eb731 /dts/src/arm/tegra20.dtsi | |
| parent | 93c4690b4921d3149db3fcf5b62a8aa5010a4ae7 (diff) | |
| download | barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.gz barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.xz | |
dts: update to v5.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/tegra20.dtsi')
| -rw-r--r-- | dts/src/arm/tegra20.dtsi | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/dts/src/arm/tegra20.dtsi b/dts/src/arm/tegra20.dtsi index 72a4211a61..6ce4981781 100644 --- a/dts/src/arm/tegra20.dtsi +++ b/dts/src/arm/tegra20.dtsi @@ -6,6 +6,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/tegra-pmc.h> +#include "tegra20-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; @@ -111,6 +113,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +141,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +654,20 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; + + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + nvidia,memory-controller = <&mc>; }; fuse@7000f800 { |