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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-01-04 13:38:22 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-01-05 14:34:10 +0100 |
| commit | 2cd77a9163504498827eda901d0cb975c04423b9 (patch) | |
| tree | 12f9cd4a2e5e54c5a1a44f293ff114896fcf3bc5 /dts/src/arm64/hisilicon | |
| parent | 9dfcb35ec75d263cbe8967d220934125525198ae (diff) | |
| download | barebox-2cd77a9163504498827eda901d0cb975c04423b9.tar.gz barebox-2cd77a9163504498827eda901d0cb975c04423b9.tar.xz | |
dts: update to v6.2-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/hisilicon')
| -rw-r--r-- | dts/src/arm64/hisilicon/hi3660.dtsi | 2 | ||||
| -rw-r--r-- | dts/src/arm64/hisilicon/hi6220.dtsi | 2 | ||||
| -rw-r--r-- | dts/src/arm64/hisilicon/hip05.dtsi | 4 | ||||
| -rw-r--r-- | dts/src/arm64/hisilicon/hip06.dtsi | 4 | ||||
| -rw-r--r-- | dts/src/arm64/hisilicon/hip07.dtsi | 16 |
5 files changed, 28 insertions, 0 deletions
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi index 8343d0cedd..a57f35eb5e 100644 --- a/dts/src/arm64/hisilicon/hi3660.dtsi +++ b/dts/src/arm64/hisilicon/hi3660.dtsi @@ -203,10 +203,12 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; A73_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi index ae0a7cfeeb..f6d3202b0d 100644 --- a/dts/src/arm64/hisilicon/hi6220.dtsi +++ b/dts/src/arm64/hisilicon/hi6220.dtsi @@ -186,10 +186,12 @@ CLUSTER0_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/dts/src/arm64/hisilicon/hip05.dtsi b/dts/src/arm64/hisilicon/hip05.dtsi index 7b2abd10d3..5b2b1bfd0d 100644 --- a/dts/src/arm64/hisilicon/hip05.dtsi +++ b/dts/src/arm64/hisilicon/hip05.dtsi @@ -211,18 +211,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/dts/src/arm64/hisilicon/hip06.dtsi b/dts/src/arm64/hisilicon/hip06.dtsi index 2f8b03b0d3..291c2ee382 100644 --- a/dts/src/arm64/hisilicon/hip06.dtsi +++ b/dts/src/arm64/hisilicon/hip06.dtsi @@ -211,18 +211,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/dts/src/arm64/hisilicon/hip07.dtsi b/dts/src/arm64/hisilicon/hip07.dtsi index 1a16662f88..b8746fb959 100644 --- a/dts/src/arm64/hisilicon/hip07.dtsi +++ b/dts/src/arm64/hisilicon/hip07.dtsi @@ -842,66 +842,82 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; cluster4_l2: l2-cache4 { compatible = "cache"; + cache-level = <2>; }; cluster5_l2: l2-cache5 { compatible = "cache"; + cache-level = <2>; }; cluster6_l2: l2-cache6 { compatible = "cache"; + cache-level = <2>; }; cluster7_l2: l2-cache7 { compatible = "cache"; + cache-level = <2>; }; cluster8_l2: l2-cache8 { compatible = "cache"; + cache-level = <2>; }; cluster9_l2: l2-cache9 { compatible = "cache"; + cache-level = <2>; }; cluster10_l2: l2-cache10 { compatible = "cache"; + cache-level = <2>; }; cluster11_l2: l2-cache11 { compatible = "cache"; + cache-level = <2>; }; cluster12_l2: l2-cache12 { compatible = "cache"; + cache-level = <2>; }; cluster13_l2: l2-cache13 { compatible = "cache"; + cache-level = <2>; }; cluster14_l2: l2-cache14 { compatible = "cache"; + cache-level = <2>; }; cluster15_l2: l2-cache15 { compatible = "cache"; + cache-level = <2>; }; }; |