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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-05 14:51:56 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-08 10:16:55 +0200 |
| commit | 085594d8fd51379afd94f9b89fcce05ecab02d8d (patch) | |
| tree | f8007ac06ed951cf8c63b9cedf067264ebac3256 /dts/src/arm64/renesas | |
| parent | 6cec968f559cc22939dbe90ebbde245a7e8a85f4 (diff) | |
| download | barebox-085594d8fd51379afd94f9b89fcce05ecab02d8d.tar.gz barebox-085594d8fd51379afd94f9b89fcce05ecab02d8d.tar.xz | |
dts: update to v5.1-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/renesas')
| -rw-r--r-- | dts/src/arm64/renesas/r8a774c0.dtsi | 7 | ||||
| -rw-r--r-- | dts/src/arm64/renesas/r8a77990.dtsi | 7 |
2 files changed, 6 insertions, 8 deletions
diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index 61a0afb74e..1ea684af99 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the RZ/G2E (R8A774C0) SoC * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> @@ -1150,9 +1150,8 @@ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi index a69faa60ea..d2ad665fe2 100644 --- a/dts/src/arm64/renesas/r8a77990.dtsi +++ b/dts/src/arm64/renesas/r8a77990.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the R-Car E3 (R8A77990) SoC * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a77990-cpg-mssr.h> @@ -1067,9 +1067,8 @@ <&cpg CPG_CORE R8A77990_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; |