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authorSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:26:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-10 08:48:45 +0100
commita40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch)
tree35f886d87a77df7bac8a587a04647691db541a2e /dts/src/arm
parent81462901ce3d677ce318150f7027e2ce1cf97c41 (diff)
downloadbarebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm')
-rw-r--r--dts/src/arm/am335x-baltos-ir2110.dts10
-rw-r--r--dts/src/arm/am335x-baltos-ir3220.dts2
-rw-r--r--dts/src/arm/am335x-baltos-ir5221.dts4
-rw-r--r--dts/src/arm/am335x-baltos.dtsi9
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi22
-rw-r--r--dts/src/arm/am335x-boneblack.dts11
-rw-r--r--dts/src/arm/am335x-evm.dts5
-rw-r--r--dts/src/arm/am335x-evmsk.dts5
-rw-r--r--dts/src/arm/am335x-icev2.dts47
-rw-r--r--dts/src/arm/am33xx.dtsi6
-rw-r--r--dts/src/arm/am3517.dtsi1
-rw-r--r--dts/src/arm/am4372.dtsi3
-rw-r--r--dts/src/arm/am437x-idk-evm.dts101
-rw-r--r--dts/src/arm/am571x-idk.dts81
-rw-r--r--dts/src/arm/am572x-idk.dts4
-rw-r--r--dts/src/arm/am57xx-beagle-x15-common.dtsi1
-rw-r--r--dts/src/arm/am57xx-idk-common.dtsi75
-rw-r--r--dts/src/arm/armada-370-db.dts63
-rw-r--r--dts/src/arm/armada-370-dlink-dns327l.dts30
-rw-r--r--dts/src/arm/armada-370-mirabox.dts57
-rw-r--r--dts/src/arm/armada-370-netgear-rn102.dts55
-rw-r--r--dts/src/arm/armada-370-netgear-rn104.dts63
-rw-r--r--dts/src/arm/armada-370-rd.dts57
-rw-r--r--dts/src/arm/armada-370-seagate-nas-4bay.dts27
-rw-r--r--dts/src/arm/armada-370-seagate-nas-xbay.dtsi45
-rw-r--r--dts/src/arm/armada-370-seagate-personal-cloud.dtsi44
-rw-r--r--dts/src/arm/armada-370-synology-ds213j.dts18
-rw-r--r--dts/src/arm/armada-370-xp.dtsi39
-rw-r--r--dts/src/arm/armada-370.dtsi136
-rw-r--r--dts/src/arm/armada-375-db.dts271
-rw-r--r--dts/src/arm/armada-375.dtsi72
-rw-r--r--dts/src/arm/armada-385-turris-omnia.dts340
-rw-r--r--dts/src/arm/armada-38x.dtsi2
-rw-r--r--dts/src/arm/armada-39x.dtsi2
-rw-r--r--dts/src/arm/armada-xp-axpwifiap.dts68
-rw-r--r--dts/src/arm/armada-xp-db.dts104
-rw-r--r--dts/src/arm/armada-xp-gp.dts80
-rw-r--r--dts/src/arm/armada-xp-lenovo-ix4-300d.dts53
-rw-r--r--dts/src/arm/armada-xp-linksys-mamba.dts52
-rw-r--r--dts/src/arm/armada-xp-matrix.dts20
-rw-r--r--dts/src/arm/armada-xp-mv78230.dtsi12
-rw-r--r--dts/src/arm/armada-xp-mv78260.dtsi20
-rw-r--r--dts/src/arm/armada-xp-mv78460.dtsi22
-rw-r--r--dts/src/arm/armada-xp-netgear-rn2120.dts74
-rw-r--r--dts/src/arm/armada-xp-openblocks-ax3-4.dts58
-rw-r--r--dts/src/arm/armada-xp-synology-ds414.dts75
-rw-r--r--dts/src/arm/armada-xp.dtsi94
-rw-r--r--dts/src/arm/artpec6-devboard.dts4
-rw-r--r--dts/src/arm/artpec6.dtsi29
-rw-r--r--dts/src/arm/at91-sama5d4_ma5d4.dtsi4
-rw-r--r--dts/src/arm/at91-sama5d4_ma5d4evk.dts4
-rw-r--r--dts/src/arm/at91rm9200.dtsi4
-rw-r--r--dts/src/arm/at91sam9260.dtsi4
-rw-r--r--dts/src/arm/at91sam9260ek.dts4
-rw-r--r--dts/src/arm/at91sam9261.dtsi4
-rw-r--r--dts/src/arm/at91sam9263.dtsi4
-rw-r--r--dts/src/arm/at91sam9g45.dtsi4
-rw-r--r--dts/src/arm/at91sam9n12.dtsi4
-rw-r--r--dts/src/arm/at91sam9rl.dtsi4
-rw-r--r--dts/src/arm/at91sam9x5.dtsi4
-rw-r--r--dts/src/arm/bcm-cygnus.dtsi21
-rw-r--r--dts/src/arm/bcm-nsp.dtsi41
-rw-r--r--dts/src/arm/bcm2835-rpi-a-plus.dts67
-rw-r--r--dts/src/arm/bcm2835-rpi-a.dts69
-rw-r--r--dts/src/arm/bcm2835-rpi-b-plus.dts68
-rw-r--r--dts/src/arm/bcm2835-rpi-b-rev2.dts68
-rw-r--r--dts/src/arm/bcm2835-rpi-b.dts69
-rw-r--r--dts/src/arm/bcm2835-rpi-zero.dts67
-rw-r--r--dts/src/arm/bcm2835-rpi.dtsi15
-rw-r--r--dts/src/arm/bcm2835.dtsi6
-rw-r--r--dts/src/arm/bcm2836-rpi-2-b.dts2
-rw-r--r--dts/src/arm/bcm2836.dtsi6
-rw-r--r--dts/src/arm/bcm283x.dtsi212
-rw-r--r--dts/src/arm/bcm4708-luxul-xap-1510.dts64
-rw-r--r--dts/src/arm/bcm4709-asus-rt-ac87u.dts2
-rw-r--r--dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts2
-rw-r--r--dts/src/arm/bcm4709-netgear-r7000.dts2
-rw-r--r--dts/src/arm/bcm4709-netgear-r8000.dts6
-rw-r--r--dts/src/arm/bcm4709-tplink-archer-c9-v1.dts114
-rw-r--r--dts/src/arm/bcm4709.dtsi11
-rw-r--r--dts/src/arm/bcm47094-dlink-dir-885l.dts3
-rw-r--r--dts/src/arm/bcm47094-luxul-xwr-3100.dts111
-rw-r--r--dts/src/arm/bcm47094-netgear-r8500.dts103
-rw-r--r--dts/src/arm/bcm47094.dtsi17
-rw-r--r--dts/src/arm/bcm47189-tenda-ac9.dts74
-rw-r--r--dts/src/arm/bcm5301x-nand-cs0-bch4.dtsi13
-rw-r--r--dts/src/arm/bcm5301x.dtsi7
-rw-r--r--dts/src/arm/bcm53573.dtsi159
-rw-r--r--dts/src/arm/bcm958625k.dts34
-rw-r--r--dts/src/arm/berlin2q-marvell-dmp.dts12
-rw-r--r--dts/src/arm/cloudengines-pogoplug-series-3.dts94
-rw-r--r--dts/src/arm/da850-lcdk.dts19
-rw-r--r--dts/src/arm/da850.dtsi70
-rw-r--r--dts/src/arm/dm814x.dtsi1
-rw-r--r--dts/src/arm/dm816x.dtsi2
-rw-r--r--dts/src/arm/dra7.dtsi1
-rw-r--r--dts/src/arm/dra71-evm.dts230
-rw-r--r--dts/src/arm/dra72-evm-common.dtsi348
-rw-r--r--dts/src/arm/dra72-evm-revc.dts31
-rw-r--r--dts/src/arm/dra72-evm-tps65917.dtsi134
-rw-r--r--dts/src/arm/dra72-evm.dts14
-rw-r--r--dts/src/arm/emev2.dtsi3
-rw-r--r--dts/src/arm/exynos3250-artik5-eval.dts2
-rw-r--r--dts/src/arm/exynos3250-artik5.dtsi2
-rw-r--r--dts/src/arm/exynos3250-monk.dts2
-rw-r--r--dts/src/arm/exynos3250-pinctrl.dtsi20
-rw-r--r--dts/src/arm/exynos3250-rinato.dts2
-rw-r--r--dts/src/arm/exynos3250.dtsi97
-rw-r--r--dts/src/arm/exynos4.dtsi100
-rw-r--r--dts/src/arm/exynos4210-pinctrl.dtsi20
-rw-r--r--dts/src/arm/exynos4210.dtsi36
-rw-r--r--dts/src/arm/exynos4412-itop-elite.dts240
-rw-r--r--dts/src/arm/exynos4412-itop-scp-core.dtsi501
-rw-r--r--dts/src/arm/exynos4412-odroidx.dts5
-rw-r--r--dts/src/arm/exynos4415-pinctrl.dtsi575
-rw-r--r--dts/src/arm/exynos4415.dtsi650
-rw-r--r--dts/src/arm/exynos4x12-pinctrl.dtsi20
-rw-r--r--dts/src/arm/exynos4x12.dtsi50
-rw-r--r--dts/src/arm/exynos5.dtsi64
-rw-r--r--dts/src/arm/exynos5250-snow-common.dtsi4
-rw-r--r--dts/src/arm/exynos5250.dtsi80
-rw-r--r--dts/src/arm/exynos5260.dtsi43
-rw-r--r--dts/src/arm/exynos5410-odroidxu.dts69
-rw-r--r--dts/src/arm/exynos5410-pinctrl.dtsi9
-rw-r--r--dts/src/arm/exynos5410.dtsi85
-rw-r--r--dts/src/arm/exynos5420-peach-pit.dts3
-rw-r--r--dts/src/arm/exynos5420.dtsi78
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-common.dtsi12
-rw-r--r--dts/src/arm/exynos5440.dtsi72
-rw-r--r--dts/src/arm/exynos54xx.dtsi34
-rw-r--r--dts/src/arm/exynos5800-peach-pi.dts3
-rw-r--r--dts/src/arm/hi3620.dtsi6
-rw-r--r--dts/src/arm/hip01.dtsi2
-rw-r--r--dts/src/arm/hisi-x5hd2.dtsi10
-rw-r--r--dts/src/arm/imx1.dtsi4
-rw-r--r--dts/src/arm/imx23.dtsi6
-rw-r--r--dts/src/arm/imx25.dtsi4
-rw-r--r--dts/src/arm/imx27.dtsi4
-rw-r--r--dts/src/arm/imx28-m28.dtsi4
-rw-r--r--dts/src/arm/imx28-m28evk.dts4
-rw-r--r--dts/src/arm/imx28.dtsi4
-rw-r--r--dts/src/arm/imx31.dtsi19
-rw-r--r--dts/src/arm/imx35.dtsi4
-rw-r--r--dts/src/arm/imx50.dtsi48
-rw-r--r--dts/src/arm/imx51.dtsi48
-rw-r--r--dts/src/arm/imx53-m53.dtsi4
-rw-r--r--dts/src/arm/imx53-m53evk.dts4
-rw-r--r--dts/src/arm/imx53.dtsi72
-rw-r--r--dts/src/arm/imx6dl-colibri-eval-v3.dts253
-rw-r--r--dts/src/arm/imx6dl-icore.dts59
-rw-r--r--dts/src/arm/imx6dl-riotboard.dts2
-rw-r--r--dts/src/arm/imx6dl-tx6dl-comtft.dts2
-rw-r--r--dts/src/arm/imx6dl-tx6u-801x.dts2
-rw-r--r--dts/src/arm/imx6q-apalis-ixora.dts22
-rw-r--r--dts/src/arm/imx6q-b650v3.dts6
-rw-r--r--dts/src/arm/imx6q-cm-fx6.dts1
-rw-r--r--dts/src/arm/imx6q-evi.dts3
-rw-r--r--dts/src/arm/imx6q-icore.dts59
-rw-r--r--dts/src/arm/imx6q-nitrogen6_som2.dts53
-rw-r--r--dts/src/arm/imx6q-novena.dts4
-rw-r--r--dts/src/arm/imx6q-phytec-pbab01.dts2
-rw-r--r--dts/src/arm/imx6q-tx6q-1010-comtft.dts2
-rw-r--r--dts/src/arm/imx6q-tx6q-1010.dts2
-rw-r--r--dts/src/arm/imx6q-tx6q-1020-comtft.dts2
-rw-r--r--dts/src/arm/imx6q-tx6q-1020.dts2
-rw-r--r--dts/src/arm/imx6q-utilite-pro.dts53
-rw-r--r--dts/src/arm/imx6qdl-apalis.dtsi9
-rw-r--r--dts/src/arm/imx6qdl-apf6dev.dtsi14
-rw-r--r--dts/src/arm/imx6qdl-colibri.dtsi890
-rw-r--r--dts/src/arm/imx6qdl-gw52xx.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-gw53xx.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-gw54xx.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-gw552x.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-icore.dtsi265
-rw-r--r--dts/src/arm/imx6qdl-nit6xlite.dtsi32
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6_max.dtsi18
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6_som2.dtsi770
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6x.dtsi12
-rw-r--r--dts/src/arm/imx6qdl-phytec-pfla02.dtsi6
-rw-r--r--dts/src/arm/imx6qdl-sabreauto.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-sabrelite.dtsi10
-rw-r--r--dts/src/arm/imx6qdl-sabresd.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-tx6.dtsi32
-rw-r--r--dts/src/arm/imx6qdl-wandboard-revb1.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-wandboard.dtsi4
-rw-r--r--dts/src/arm/imx6qdl.dtsi14
-rw-r--r--dts/src/arm/imx6qp.dtsi17
-rw-r--r--dts/src/arm/imx6sl.dtsi7
-rw-r--r--dts/src/arm/imx6sx-sdb.dtsi16
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-basic.dts69
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-extended.dts54
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-full.dts69
-rw-r--r--dts/src/arm/imx6sx-udoo-neo.dtsi293
-rw-r--r--dts/src/arm/imx6sx.dtsi17
-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dts10
-rw-r--r--dts/src/arm/imx6ul-liteboard.dts147
-rw-r--r--dts/src/arm/imx6ul-litesom.dtsi82
-rw-r--r--dts/src/arm/imx6ul.dtsi4
-rw-r--r--dts/src/arm/imx6ull-14x14-evk.dts52
-rw-r--r--dts/src/arm/imx6ull-pinfunc.h56
-rw-r--r--dts/src/arm/imx6ull.dtsi43
-rw-r--r--dts/src/arm/imx7d-pinfunc.h12
-rw-r--r--dts/src/arm/imx7s.dtsi4
-rw-r--r--dts/src/arm/integratorap.dts35
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-rw-r--r--dts/src/arm/keystone-k2l.dtsi1
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-rw-r--r--dts/src/arm/mt2701.dtsi50
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-rw-r--r--dts/src/arm/rk3288-firefly-reload-core.dtsi2
-rw-r--r--dts/src/arm/rk3288-firefly.dtsi2
-rw-r--r--dts/src/arm/rk3288-miqi.dts2
-rw-r--r--dts/src/arm/rk3288-popmetal.dts34
-rw-r--r--dts/src/arm/rk3288-r89.dts2
-rw-r--r--dts/src/arm/rk3288-rock2-som.dtsi2
-rw-r--r--dts/src/arm/rk3288-veyron.dtsi2
-rw-r--r--dts/src/arm/rk3288.dtsi15
-rw-r--r--dts/src/arm/rk3xxx.dtsi5
-rw-r--r--dts/src/arm/sama5d2.dtsi47
-rw-r--r--dts/src/arm/sama5d3.dtsi4
-rw-r--r--dts/src/arm/sama5d4.dtsi31
-rw-r--r--dts/src/arm/sh73a0.dtsi4
-rw-r--r--dts/src/arm/socfpga.dtsi33
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi32
-rw-r--r--dts/src/arm/socfpga_arria10_socdk.dtsi49
-rw-r--r--dts/src/arm/socfpga_arria10_socdk_qspi.dts49
-rw-r--r--dts/src/arm/socfpga_arria5_socdk.dts33
-rw-r--r--dts/src/arm/socfpga_cyclone5_de0_sockit.dts2
-rw-r--r--dts/src/arm/socfpga_cyclone5_mcv.dtsi2
-rw-r--r--dts/src/arm/socfpga_cyclone5_mcvevk.dts4
-rw-r--r--dts/src/arm/socfpga_cyclone5_socdk.dts35
-rw-r--r--dts/src/arm/socfpga_cyclone5_sockit.dts23
-rw-r--r--dts/src/arm/socfpga_cyclone5_socrates.dts19
-rw-r--r--dts/src/arm/socfpga_cyclone5_sodia.dts123
-rw-r--r--dts/src/arm/socfpga_cyclone5_vining_fpga.dts2
-rw-r--r--dts/src/arm/spear13xx.dtsi2
-rw-r--r--dts/src/arm/stih407-clock.dtsi10
-rw-r--r--dts/src/arm/stih407-family.dtsi32
-rw-r--r--dts/src/arm/stih407-pinctrl.dtsi2
-rw-r--r--dts/src/arm/stih407.dtsi2
-rw-r--r--dts/src/arm/stih410-b2260.dts22
-rw-r--r--dts/src/arm/stih410-clock.dtsi3
-rw-r--r--dts/src/arm/stih410.dtsi2
-rw-r--r--dts/src/arm/stih415-b2000.dts15
-rw-r--r--dts/src/arm/stih415-b2020.dts15
-rw-r--r--dts/src/arm/stih415-clock.dtsi533
-rw-r--r--dts/src/arm/stih415-pinctrl.dtsi545
-rw-r--r--dts/src/arm/stih415.dtsi234
-rw-r--r--dts/src/arm/stih416-b2000.dts15
-rw-r--r--dts/src/arm/stih416-b2020.dts37
-rw-r--r--dts/src/arm/stih416-b2020e.dts65
-rw-r--r--dts/src/arm/stih416-clock.dtsi756
-rw-r--r--dts/src/arm/stih416-pinctrl.dtsi692
-rw-r--r--dts/src/arm/stih416.dtsi517
-rw-r--r--dts/src/arm/stih41x-b2000.dtsi96
-rw-r--r--dts/src/arm/stih41x-b2020.dtsi82
-rw-r--r--dts/src/arm/stih41x-b2020x.dtsi32
-rw-r--r--dts/src/arm/stih41x.dtsi47
-rw-r--r--dts/src/arm/stihxxx-b2120.dtsi21
-rw-r--r--dts/src/arm/stm32429i-eval.dts29
-rw-r--r--dts/src/arm/stm32746g-eval.dts96
-rw-r--r--dts/src/arm/stm32f429-disco.dts13
-rw-r--r--dts/src/arm/stm32f429.dtsi40
-rw-r--r--dts/src/arm/stm32f469-disco.dts8
-rw-r--r--dts/src/arm/stm32f746.dtsi304
-rw-r--r--dts/src/arm/sun4i-a10.dtsi3
-rw-r--r--dts/src/arm/sun5i-a10s-olinuxino-micro.dts4
-rw-r--r--dts/src/arm/sun5i-a10s.dtsi4
-rw-r--r--dts/src/arm/sun5i-a13-olinuxino.dts54
-rw-r--r--dts/src/arm/sun5i-a13-utoo-p66.dts38
-rw-r--r--dts/src/arm/sun5i-gr8-chip-pro.dts266
-rw-r--r--dts/src/arm/sun5i-gr8-evb.dts33
-rw-r--r--dts/src/arm/sun5i-gr8.dtsi47
-rw-r--r--dts/src/arm/sun5i-r8-chip.dts69
-rw-r--r--dts/src/arm/sun5i-reference-design-tablet.dtsi25
-rw-r--r--dts/src/arm/sun5i.dtsi27
-rw-r--r--dts/src/arm/sun6i-a31-hummingbird.dts80
-rw-r--r--dts/src/arm/sun6i-a31.dtsi266
-rw-r--r--dts/src/arm/sun6i-a31s-sina31s.dts8
-rw-r--r--dts/src/arm/sun6i-a31s.dtsi8
-rw-r--r--dts/src/arm/sun7i-a20-bananapi-m1-plus.dts62
-rw-r--r--dts/src/arm/sun7i-a20-olimex-som-evb.dts4
-rw-r--r--dts/src/arm/sun7i-a20.dtsi3
-rw-r--r--dts/src/arm/sun8i-a23-a33.dtsi6
-rw-r--r--dts/src/arm/sun8i-a23-polaroid-mid2407pxe03.dts7
-rw-r--r--dts/src/arm/sun8i-a33-sinlinx-sina33.dts5
-rw-r--r--dts/src/arm/sun8i-h3-nanopi-m1.dts64
-rw-r--r--dts/src/arm/sun8i-h3-nanopi-neo.dts79
-rw-r--r--dts/src/arm/sun8i-h3-nanopi.dtsi144
-rw-r--r--dts/src/arm/sun8i-h3.dtsi52
-rw-r--r--dts/src/arm/sun8i-reference-design-tablet.dtsi7
-rw-r--r--dts/src/arm/sun9i-a80-cubieboard4.dts32
-rw-r--r--dts/src/arm/sun9i-a80-optimus.dts30
-rw-r--r--dts/src/arm/sun9i-a80.dtsi14
-rw-r--r--dts/src/arm/tegra124-apalis.dtsi2
-rw-r--r--dts/src/arm/tegra124-nyan.dtsi8
-rw-r--r--dts/src/arm/tegra20.dtsi13
-rw-r--r--dts/src/arm/tegra30-apalis.dtsi49
-rw-r--r--dts/src/arm/tegra30-colibri.dtsi49
-rw-r--r--dts/src/arm/tegra30.dtsi13
-rw-r--r--dts/src/arm/tps65217.dtsi12
-rw-r--r--dts/src/arm/uniphier-common32.dtsi199
-rw-r--r--dts/src/arm/uniphier-ld4.dtsi358
-rw-r--r--dts/src/arm/uniphier-pro4.dtsi378
-rw-r--r--dts/src/arm/uniphier-pro5.dtsi432
-rw-r--r--dts/src/arm/uniphier-pxs2.dtsi399
-rw-r--r--dts/src/arm/uniphier-sld3.dtsi21
-rw-r--r--dts/src/arm/uniphier-sld8.dtsi359
-rw-r--r--dts/src/arm/vexpress-v2p-ca15_a7.dts5
-rw-r--r--dts/src/arm/vf-colibri.dtsi4
-rw-r--r--dts/src/arm/vf610-zii-dev-rev-b.dts65
-rw-r--r--dts/src/arm/vfxxx.dtsi18
-rw-r--r--dts/src/arm/zynq-7000.dtsi10
-rw-r--r--dts/src/arm/zynq-microzed.dts96
-rw-r--r--dts/src/arm/zynq-parallella.dts2
-rw-r--r--dts/src/arm/zynq-zc702.dts2
-rw-r--r--dts/src/arm/zynq-zc706.dts2
-rw-r--r--dts/src/arm/zynq-zed.dts2
-rw-r--r--dts/src/arm/zynq-zybo.dts2
389 files changed, 18166 insertions, 7975 deletions
diff --git a/dts/src/arm/am335x-baltos-ir2110.dts b/dts/src/arm/am335x-baltos-ir2110.dts
index a9a9730..501c752 100644
--- a/dts/src/arm/am335x-baltos-ir2110.dts
+++ b/dts/src/arm/am335x-baltos-ir2110.dts
@@ -54,16 +54,22 @@
dr_mode = "host";
};
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/dts/src/arm/am335x-baltos-ir3220.dts b/dts/src/arm/am335x-baltos-ir3220.dts
index fe002a1..19f53b8 100644
--- a/dts/src/arm/am335x-baltos-ir3220.dts
+++ b/dts/src/arm/am335x-baltos-ir3220.dts
@@ -109,9 +109,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/dts/src/arm/am335x-baltos-ir5221.dts b/dts/src/arm/am335x-baltos-ir5221.dts
index d0faa7b..2b9d7f4 100644
--- a/dts/src/arm/am335x-baltos-ir5221.dts
+++ b/dts/src/arm/am335x-baltos-ir5221.dts
@@ -114,7 +114,7 @@
&usb1 {
status = "okay";
- dr_mode = "otg";
+ dr_mode = "host";
};
&cpsw_emac0 {
@@ -127,9 +127,9 @@
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
};
&phy_sel {
diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi
index dd45d17..efb5eae 100644
--- a/dts/src/arm/am335x-baltos.dtsi
+++ b/dts/src/arm/am335x-baltos.dtsi
@@ -364,11 +364,14 @@
};
&davinci_mdio {
+ status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <7>;
+ };
};
&mmc1 {
@@ -406,3 +409,7 @@
&gpio0 {
ti,no-reset-on-init;
};
+
+&gpio3 {
+ ti,no-reset-on-init;
+};
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index 007b5e5..dc561d5 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -6,6 +6,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/mfd/tps65217.h>
+
/ {
cpus {
cpu@0 {
@@ -310,8 +312,23 @@
* by the hardware problems. (Tip: double-check by performing a current
* measurement after shutdown: it should be less than 1 mA.)
*/
+
+ interrupts = <7>; /* NMI */
+ interrupt-parent = <&intc>;
+
ti,pmic-shutdown-controller;
+ charger {
+ interrupts = <TPS65217_IRQ_AC>, <TPS65217_IRQ_USB>;
+ interrupts-names = "AC", "USB";
+ status = "okay";
+ };
+
+ pwrbutton {
+ interrupts = <TPS65217_IRQ_PB>;
+ status = "okay";
+ };
+
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
@@ -393,3 +410,8 @@
&sham {
status = "okay";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/dts/src/arm/am335x-boneblack.dts b/dts/src/arm/am335x-boneblack.dts
index 6bbb1fe..db00d8e 100644
--- a/dts/src/arm/am335x-boneblack.dts
+++ b/dts/src/arm/am335x-boneblack.dts
@@ -79,6 +79,14 @@
&lcdc {
status = "okay";
+
+ /* If you want to get 24 bit RGB and 16 BGR mode instead of
+ * current 16 bit RGB and 24 BGR modes, set the propety
+ * below to "crossed" and uncomment the video-ports -property
+ * in tda19988 node.
+ */
+ blue-and-red-wiring = "straight";
+
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
@@ -95,6 +103,9 @@
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+ /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
+ /* video-ports = <0x234501>; */
+
#sound-dai-cells = <0>;
audio-ports = < TDA998x_I2S 0x03>;
diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts
index e82432c..c2186ec 100644
--- a/dts/src/arm/am335x-evm.dts
+++ b/dts/src/arm/am335x-evm.dts
@@ -783,3 +783,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts
index 975c36e..e2548d1 100644
--- a/dts/src/arm/am335x-evmsk.dts
+++ b/dts/src/arm/am335x-evmsk.dts
@@ -715,3 +715,8 @@
blue-and-red-wiring = "crossed";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/dts/src/arm/am335x-icev2.dts b/dts/src/arm/am335x-icev2.dts
index 85e04c2..1463df3 100644
--- a/dts/src/arm/am335x-icev2.dts
+++ b/dts/src/arm/am335x-icev2.dts
@@ -43,52 +43,52 @@
enable-active-high;
};
- leds0 {
+ leds-iio {
+ status = "disabled";
compatible = "gpio-leds";
-
- led0 {
+ led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led1 {
+ led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led2 {
+ led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led3 {
+ led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led4 {
+ led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led5 {
+ led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led6 {
+ led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- led7 {
+ led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
@@ -187,6 +187,8 @@
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
+ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
>;
};
@@ -224,6 +226,31 @@
};
};
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_default>;
+
+ sn65hvs882@1 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
+&tscadc {
+ status = "okay";
+ adc {
+ ti,adc-channels = <1 2 3 4 5 6 7>;
+ };
+};
+
#include "tps65910.dtsi"
&tps {
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index 194d884..64c8aa9 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -130,6 +130,7 @@
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
@@ -137,6 +138,7 @@
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
@@ -505,6 +507,8 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
+ clocks = <&clkdiv32k_ick>;
+ clock-names = "int-clk";
};
spi0: spi@48030000 {
@@ -855,6 +859,8 @@
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
diff --git a/dts/src/arm/am3517.dtsi b/dts/src/arm/am3517.dtsi
index 0db19d3..9fe545d 100644
--- a/dts/src/arm/am3517.dtsi
+++ b/dts/src/arm/am3517.dtsi
@@ -66,6 +66,7 @@
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi
index a275fa9..ac55f93 100644
--- a/dts/src/arm/am4372.dtsi
+++ b/dts/src/arm/am4372.dtsi
@@ -189,6 +189,7 @@
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
@@ -871,6 +872,8 @@
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts
index 25ce611..b76a7c0 100644
--- a/dts/src/arm/am437x-idk-evm.dts
+++ b/dts/src/arm/am437x-idk-evm.dts
@@ -117,6 +117,58 @@
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+
+ leds-iio {
+ status = "disabled";
+ compatible = "gpio-leds";
+ led-out0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&am43xx_pinmux {
@@ -178,6 +230,24 @@
>;
};
+ spi1_pins_default: spi1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */
+ AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */
+ AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */
+ AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */
+ >;
+ };
+
+ spi1_pins_sleep: spi1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
ecap0_pins_default: backlight_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
@@ -290,6 +360,33 @@
pinctrl-0 = <&i2c2_pins_default>;
pinctrl-1 = <&i2c2_pins_sleep>;
clock-frequency = <100000>;
+
+ tpic2810: tpic2810@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_default>;
+ pinctrl-1 = <&spi1_pins_sleep>;
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
};
&epwmss0 {
@@ -310,6 +407,10 @@
status = "okay";
};
+&gpio3 {
+ status = "okay";
+};
+
&gpio4 {
status = "okay";
};
diff --git a/dts/src/arm/am571x-idk.dts b/dts/src/arm/am571x-idk.dts
new file mode 100644
index 0000000..d6e43e5
--- /dev/null
+++ b/dts/src/arm/am571x-idk.dts
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ model = "TI AM5718 IDK";
+ compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1-led {
+ label = "status1:red:usr";
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ usr2-led {
+ label = "status1:green:usr";
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
diff --git a/dts/src/arm/am572x-idk.dts b/dts/src/arm/am572x-idk.dts
index 87bbc66..27d9149 100644
--- a/dts/src/arm/am572x-idk.dts
+++ b/dts/src/arm/am572x-idk.dts
@@ -83,3 +83,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
+
+&sn65hvs882 {
+ load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/am57xx-beagle-x15-common.dtsi b/dts/src/arm/am57xx-beagle-x15-common.dtsi
index 6df7829..78bee26 100644
--- a/dts/src/arm/am57xx-beagle-x15-common.dtsi
+++ b/dts/src/arm/am57xx-beagle-x15-common.dtsi
@@ -204,6 +204,7 @@
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
diff --git a/dts/src/arm/am57xx-idk-common.dtsi b/dts/src/arm/am57xx-idk-common.dtsi
index 03cec62..555ae21 100644
--- a/dts/src/arm/am57xx-idk-common.dtsi
+++ b/dts/src/arm/am57xx-idk-common.dtsi
@@ -43,6 +43,58 @@
regulator-always-on;
regulator-boot-on;
};
+
+ leds-iio {
+ status = "disabled";
+ compatible = "gpio-leds";
+ led-out0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
&i2c1 {
@@ -57,6 +109,7 @@
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
@@ -253,6 +306,28 @@
};
};
+&mcspi3 {
+ status = "okay";
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+
+ tpic2810: tpic2810@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
diff --git a/dts/src/arm/armada-370-db.dts b/dts/src/arm/armada-370-db.dts
index 033fa63..a9419f8 100644
--- a/dts/src/arm/armada-370-db.dts
+++ b/dts/src/arm/armada-370-db.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
@@ -86,18 +86,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -182,24 +170,6 @@
};
};
};
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * both standard PCIe slots and mini-PCIe
- * slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
sound {
@@ -261,6 +231,37 @@
};
};
+&pciec {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * both standard PCIe slots and mini-PCIe
+ * slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+
&spi0 {
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
diff --git a/dts/src/arm/armada-370-dlink-dns327l.dts b/dts/src/arm/armada-370-dlink-dns327l.dts
index e2a363b..aeedc46 100644
--- a/dts/src/arm/armada-370-dlink-dns327l.dts
+++ b/dts/src/arm/armada-370-dlink-dns327l.dts
@@ -62,7 +62,7 @@
stdout-path = &uart0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MiB */
};
@@ -72,20 +72,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
sata@a0000 {
nr-ports = <2>;
@@ -262,6 +248,20 @@
};
};
+&pciec {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&pinctrl {
sata_l_white_pin: sata-l-white-pin {
marvell,pins = "mpp57";
diff --git a/dts/src/arm/armada-370-mirabox.dts b/dts/src/arm/armada-370-mirabox.dts
index d5e19cd..a142540 100644
--- a/dts/src/arm/armada-370-mirabox.dts
+++ b/dts/src/arm/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -64,22 +64,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -113,17 +97,6 @@
};
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -197,6 +170,34 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
diff --git a/dts/src/arm/armada-370-netgear-rn102.dts b/dts/src/arm/armada-370-netgear-rn102.dts
index 39181b3..6bd9265 100644
--- a/dts/src/arm/armada-370-netgear-rn102.dts
+++ b/dts/src/arm/armada-370-netgear-rn102.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to Marvell 88SE9170 SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to FL1009 USB 3.0 controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -99,14 +83,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
- };
-
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
@@ -120,8 +96,11 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
+
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
isl12057: isl12057@68 {
@@ -257,6 +236,30 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to Marvell 88SE9170 SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to FL1009 USB 3.0 controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+};
+
&pinctrl {
power_led_pin: power-led-pin {
marvell,pins = "mpp57";
diff --git a/dts/src/arm/armada-370-netgear-rn104.dts b/dts/src/arm/armada-370-netgear-rn104.dts
index 1156575..c84ab5b 100644
--- a/dts/src/arm/armada-370-netgear-rn104.dts
+++ b/dts/src/arm/armada-370-netgear-rn104.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -66,22 +66,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to FL1009 USB 3.0 controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to Marvell 88SE9215 SATA controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -93,18 +77,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -126,8 +98,11 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
+
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
isl12057: isl12057@68 {
@@ -279,6 +254,34 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to FL1009 USB 3.0 controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to Marvell 88SE9215 SATA controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp60";
diff --git a/dts/src/arm/armada-370-rd.dts b/dts/src/arm/armada-370-rd.dts
index fbef730..c3fd6e4 100644
--- a/dts/src/arm/armada-370-rd.dts
+++ b/dts/src/arm/armada-370-rd.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -77,22 +77,6 @@
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Internal mini-PCIe connector */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -102,14 +86,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -146,7 +122,7 @@
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ button {
label = "Software Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
@@ -196,7 +172,7 @@
};
};
- dsa@0 {
+ dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -235,7 +211,32 @@
};
};
};
- };
+};
+
+&pciec {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Internal mini-PCIe connector */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
fan_pins: fan-pins {
diff --git a/dts/src/arm/armada-370-seagate-nas-4bay.dts b/dts/src/arm/armada-370-seagate-nas-4bay.dts
index ae2e1fe..eb6af53 100644
--- a/dts/src/arm/armada-370-seagate-nas-4bay.dts
+++ b/dts/src/arm/armada-370-seagate-nas-4bay.dts
@@ -28,20 +28,7 @@
compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
soc {
- pcie-controller {
- /* SATA AHCI controller 88SE9170 */
- pcie@1,0 {
- status = "okay";
- };
- };
-
internal-regs {
- mdio {
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@@ -131,3 +118,17 @@
1300 0>;
};
};
+
+&pciec {
+ /* SATA AHCI controller 88SE9170 */
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
diff --git a/dts/src/arm/armada-370-seagate-nas-xbay.dtsi b/dts/src/arm/armada-370-seagate-nas-xbay.dtsi
index 3036e25..e9a5b95 100644
--- a/dts/src/arm/armada-370-seagate-nas-xbay.dtsi
+++ b/dts/src/arm/armada-370-seagate-nas-xbay.dtsi
@@ -23,7 +23,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -32,15 +32,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
- pcie-controller {
- status = "okay";
-
- /* USB 3.0 bridge ASM1042A */
- pcie@2,0 {
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -51,15 +42,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -159,19 +141,19 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@2 {
+ backup {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@3 {
+ reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
@@ -208,6 +190,25 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* USB 3.0 bridge ASM1042A */
+ pcie@2,0 {
+ status = "okay";
+ };
+};
+
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
pinctrl-names = "default";
diff --git a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
index 01cded3..d079a89 100644
--- a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
+++ b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
@@ -24,7 +24,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -33,15 +33,6 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
- pcie-controller {
- status = "okay";
-
- /* USB 3.0 Bridge ASM1042A */
- pcie@1,0 {
- status = "okay";
- };
- };
-
internal-regs {
coherency-fabric@20200 {
broken-idle;
@@ -51,15 +42,6 @@
status = "okay";
};
- mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
@@ -107,19 +89,19 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
- button@2 {
+ reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button@3 {
+ button {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
@@ -143,6 +125,24 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* USB 3.0 Bridge ASM1042A */
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl {
pinctrl-0 = <&sata_led_pin>;
pinctrl-names = "default";
diff --git a/dts/src/arm/armada-370-synology-ds213j.dts b/dts/src/arm/armada-370-synology-ds213j.dts
index a9cc427..99f9de2 100644
--- a/dts/src/arm/armada-370-synology-ds213j.dts
+++ b/dts/src/arm/armada-370-synology-ds213j.dts
@@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
@@ -127,12 +127,6 @@
status = "okay";
};
- mdio {
- phy1: ethernet-phy@1 { /* Marvell 88E1512 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy1>;
@@ -192,7 +186,7 @@
pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
pinctrl-names = "default";
- sata1_regulator: sata1-regulator {
+ sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -205,7 +199,7 @@
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
- sata2_regulator: sata2-regulator {
+ sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@@ -220,6 +214,12 @@
};
};
+&mdio {
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
disk1_led_pin: disk1-led-pin {
marvell,pins = "mpp31";
diff --git a/dts/src/arm/armada-370-xp.dtsi b/dts/src/arm/armada-370-xp.dtsi
index 3ccedc9..b0520bd 100644
--- a/dts/src/arm/armada-370-xp.dtsi
+++ b/dts/src/arm/armada-370-xp.dtsi
@@ -50,8 +50,6 @@
* 370 and Armada XP SoC.
*/
-/include/ "skeleton64.dtsi"
-
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
@@ -86,7 +84,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -96,7 +94,7 @@
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -106,7 +104,7 @@
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -116,7 +114,7 @@
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -126,7 +124,7 @@
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -142,7 +140,7 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
- rtc@10300 {
+ rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
@@ -214,33 +212,38 @@
msi-controller;
};
- coherency-fabric@20200 {
+ coherencyfab: coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
- timer@20300 {
+ timer: timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
- watchdog@20300 {
+ watchdog: watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
- pmsu@22000 {
+ cpurst: cpurst@20800 {
+ compatible = "marvell,armada-370-cpu-reset";
+ reg = <0x20800 0x8>;
+ };
+
+ pmsu: pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
- usb@50000 {
+ usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
- usb@51000 {
+ usb1: usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@@ -254,7 +257,7 @@
status = "disabled";
};
- mdio: mdio {
+ mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@@ -269,7 +272,7 @@
status = "disabled";
};
- sata@a0000 {
+ sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@@ -278,7 +281,7 @@
status = "disabled";
};
- nand@d0000 {
+ nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@@ -288,7 +291,7 @@
status = "disabled";
};
- mvsdio@d4000 {
+ sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi
index b425810..b704bcc 100644
--- a/dts/src/arm/armada-370.dtsi
+++ b/dts/src/arm/armada-370.dtsi
@@ -50,9 +50,11 @@
*/
#include "armada-370-xp.dtsi"
-/include/ "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
@@ -70,7 +72,7 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
- pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -89,7 +91,7 @@
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
- pcie@1,0 {
+ pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -106,7 +108,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -125,7 +127,7 @@
};
internal-regs {
- L2: l2-cache {
+ L2: l2-cache@8000 {
compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@@ -134,14 +136,6 @@
wt-override;
};
- i2c0: i2c@11000 {
- reg = <0x11000 0x20>;
- };
-
- i2c1: i2c@11100 {
- reg = <0x11100 0x20>;
- };
-
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
@@ -175,22 +169,8 @@
interrupts = <91>;
};
- /*
- * Default UART pinctrl setting without RTS/CTS, can
- * be overwritten on board level if a different
- * configuration is used.
- */
- uart0: serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- };
-
- uart1: serial@12100 {
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
@@ -208,37 +188,18 @@
#clock-cells = <1>;
};
- thermal@18300 {
+ thermal: thermal@18300 {
compatible = "marvell,armada370-thermal";
reg = <0x18300 0x4
0x18304 0x4>;
status = "okay";
};
- sscg@18330 {
+ sscg: sscg@18330 {
reg = <0x18330 0x4>;
};
- interrupt-controller@20a00 {
- reg = <0x20a00 0x1d0>, <0x21870 0x58>;
- };
-
- timer@20300 {
- compatible = "marvell,armada-370-timer";
- clocks = <&coreclk 2>;
- };
-
- watchdog@20300 {
- compatible = "marvell,armada-370-wdt";
- clocks = <&coreclk 2>;
- };
-
- cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x8>;
- };
-
- cpu-config@21000 {
+ cpuconf: cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
@@ -253,15 +214,7 @@
status = "disabled";
};
- usb@50000 {
- clocks = <&coreclk 0>;
- };
-
- usb@51000 {
- clocks = <&coreclk 0>;
- };
-
- xor@60800 {
+ xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@@ -280,7 +233,7 @@
};
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -299,15 +252,7 @@
};
};
- ethernet@70000 {
- compatible = "marvell,armada-370-neta";
- };
-
- ethernet@74000 {
- compatible = "marvell,armada-370-neta";
- };
-
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@@ -342,6 +287,59 @@
};
};
+/*
+ * Default UART pinctrl setting without RTS/CTS, can be overwritten on
+ * board level if a different configuration is used.
+ */
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c0 {
+ reg = <0x11000 0x20>;
+};
+
+&i2c1 {
+ reg = <0x11100 0x20>;
+};
+
+&mpic {
+ reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+};
+
+&timer {
+ compatible = "marvell,armada-370-timer";
+ clocks = <&coreclk 2>;
+};
+
+&watchdog {
+ compatible = "marvell,armada-370-wdt";
+ clocks = <&coreclk 2>;
+};
+
+&usb0 {
+ clocks = <&coreclk 0>;
+};
+
+&usb1 {
+ clocks = <&coreclk 0>;
+};
+
+&eth0 {
+ compatible = "marvell,armada-370-neta";
+};
+
+&eth1 {
+ compatible = "marvell,armada-370-neta";
+};
+
&pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
diff --git a/dts/src/arm/armada-375-db.dts b/dts/src/arm/armada-375-db.dts
index cded5f0..ef45cbe 100644
--- a/dts/src/arm/armada-375-db.dts
+++ b/dts/src/arm/armada-375-db.dts
@@ -58,7 +58,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
@@ -69,138 +69,141 @@
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
- internal-regs {
- spi@10600 {
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- /*
- * SPI conflicts with NAND, so we disable it
- * here, and select NAND as the enabled device
- * by default.
- */
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
- };
-
- i2c@11000 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- };
-
- i2c@11100 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- };
-
- serial@12000 {
- status = "okay";
- };
-
- pinctrl {
- sdio_st_pins: sdio-st-pins {
- marvell,pins = "mpp44", "mpp45";
- marvell,function = "gpio";
- };
- };
-
- sata@a0000 {
- status = "okay";
- nr-ports = <2>;
- };
-
- nand: nand@d0000 {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x800000>;
- };
- partition@800000 {
- label = "Linux";
- reg = <0x800000 0x800000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
-
- usb@54000 {
- status = "okay";
- };
-
- usb3@58000 {
- status = "okay";
- };
-
- mvsdio@d4000 {
- pinctrl-0 = <&sdio_pins &sdio_st_pins>;
- pinctrl-names = "default";
- status = "okay";
- cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
-
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
-
- ethernet@f0000 {
- status = "okay";
-
- eth0@c4000 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
-
- eth1@c5000 {
- status = "okay";
- phy = <&phy3>;
- phy-mode = "gmii";
- };
- };
- };
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
};
+&pciec {
+ status = "okay";
+};
+
+/*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+&pcie0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&pcie1 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+
+ /*
+ * SPI conflicts with NAND, so we disable it here, and
+ * select NAND as the enabled device by default.
+ */
+
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&pinctrl {
+ sdio_st_pins: sdio-st-pins {
+ marvell,pins = "mpp44", "mpp45";
+ marvell,function = "gpio";
+ };
+};
+
+&sata {
+ status = "okay";
+ nr-ports = <2>;
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x800000>;
+ };
+ partition@800000 {
+ label = "Linux";
+ reg = <0x800000 0x800000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&sdio {
+ pinctrl-0 = <&sdio_pins &sdio_st_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+&ethernet {
+ status = "okay";
+};
+
+
+&eth0 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&eth1 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "gmii";
+};
diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi
index cc952cf..f515591 100644
--- a/dts/src/arm/armada-375.dtsi
+++ b/dts/src/arm/armada-375.dtsi
@@ -45,7 +45,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
@@ -53,6 +52,9 @@
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
model = "Marvell Armada 375 family SoC";
compatible = "marvell,armada375";
@@ -65,7 +67,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -84,12 +86,12 @@
#size-cells = <0>;
enable-method = "marvell,armada-375-smp";
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@@ -115,7 +117,7 @@
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -125,7 +127,7 @@
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -135,7 +137,7 @@
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -145,7 +147,7 @@
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -155,7 +157,7 @@
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -182,12 +184,12 @@
prefetch-data = <1>;
};
- scu@c000 {
+ scu: scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
- timer@c600 {
+ timer0: timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
@@ -203,7 +205,7 @@
<0xc100 0x100>;
};
- mdio {
+ mdio: mdio@c0054 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@@ -212,7 +214,7 @@
};
/* Network controller */
- ethernet@f0000 {
+ ethernet: ethernet@f0000 {
compatible = "marvell,armada-375-pp2";
reg = <0xf0000 0xa000>, /* Packet Processor regs */
<0xc0000 0x3060>, /* LMS regs */
@@ -222,20 +224,20 @@
clock-names = "pp_clk", "gop_clk";
status = "disabled";
- eth0: eth0@c4000 {
+ eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
status = "disabled";
};
- eth1: eth1@c5000 {
+ eth1: eth1 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
status = "disabled";
};
};
- rtc@10300 {
+ rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -307,7 +309,7 @@
status = "disabled";
};
- pinctrl {
+ pinctrl: pinctrl@18000 {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
@@ -382,7 +384,7 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
};
@@ -415,7 +417,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
- timer@20300 {
+ timer1: timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@@ -428,24 +430,24 @@
clock-names = "nbclk", "fixed";
};
- watchdog@20300 {
+ watchdog: watchdog@20300 {
compatible = "marvell,armada-375-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
- cpurst@20800 {
+ cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
- coherency-fabric@21010 {
+ coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-375-coherency-fabric";
reg = <0x21010 0x1c>;
};
- usb@50000 {
+ usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -455,7 +457,7 @@
status = "disabled";
};
- usb@54000 {
+ usb1: usb@54000 {
compatible = "marvell,orion-ehci";
reg = <0x54000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -463,7 +465,7 @@
status = "disabled";
};
- usb3@58000 {
+ usb2: usb3@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,7 +475,7 @@
status = "disabled";
};
- xor@60800 {
+ xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
@@ -493,7 +495,7 @@
};
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -513,7 +515,7 @@
};
};
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@@ -528,7 +530,7 @@
marvell,crypto-sram-size = <0x800>;
};
- sata@a0000 {
+ sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -537,7 +539,7 @@
status = "disabled";
};
- nand@d0000 {
+ nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@@ -547,7 +549,7 @@
status = "disabled";
};
- mvsdio@d4000 {
+ sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -559,7 +561,7 @@
status = "disabled";
};
- thermal@e8078 {
+ thermal: thermal@e8078 {
compatible = "marvell,armada375-thermal";
reg = <0xe8078 0x4>, <0xe807c 0x8>;
status = "okay";
@@ -580,7 +582,7 @@
};
};
- pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -599,7 +601,7 @@
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
- pcie@1,0 {
+ pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -616,7 +618,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie1: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
diff --git a/dts/src/arm/armada-385-turris-omnia.dts b/dts/src/arm/armada-385-turris-omnia.dts
new file mode 100644
index 0000000..ab49acb
--- /dev/null
+++ b/dts/src/arm/armada-385-turris-omnia.dts
@@ -0,0 +1,340 @@
+/*
+ * Device Tree file for the Turris Omnia
+ *
+ * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
+ * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "Turris Omnia";
+ compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1024 MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+
+ /* USB part of the PCIe2/USB 2.0 port */
+ usb@58000 {
+ status = "okay";
+ };
+
+ sata@a8000 {
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ status = "okay";
+
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@3,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ };
+ };
+};
+
+/* Connected to 88E6176 switch, port 6 */
+&eth0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* Connected to 88E6176 switch, port 5 */
+&eth1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* WAN port */
+&eth2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&phy1>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ status = "okay";
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ /* STM32F0 command interface at address 0x2a */
+ /* leds device (in STM32F0) at address 0x2b */
+
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+
+ /* The EEPROM contains data for bootloader.
+ * Contents:
+ * struct omnia_eeprom {
+ * u32 magic; (=0x0341a034 in LE)
+ * u32 ramsize; (in GiB)
+ * char regdomain[4];
+ * u32 crc32;
+ * };
+ */
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ /* routed to PCIe0/mSATA connector (CN7A) */
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ /* routed to PCIe1/USB2 connector (CN61A) */
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ /* routed to PCIe2 connector (CN62A) */
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ /* routed to SFP+ */
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+
+ /* ATSHA204A at address 0x64 */
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ /* exposed on pin header */
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pcawan: gpio@71 {
+ /*
+ * GPIO expander for SFP+ signals and
+ * and phy irq
+ */
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcawan_pins>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy1: phy@1 {
+ status = "okay";
+ compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ /* irq is connected to &pcawan pin 7 */
+ };
+
+ /* Switch MV88E7176 at address 0x10 */
+};
+
+&pinctrl {
+ pcawan_pins: pcawan-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ spi0cs0_pins: spi0cs0-pins {
+ marvell,pins = "mpp25";
+ marvell,function = "spi0";
+ };
+
+ spi0cs1_pins: spi0cs1-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "spi0";
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
+ status = "okay";
+
+ spi-nor@0 {
+ compatible = "spansion,s25fl164k", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x00100000>;
+ label = "U-Boot";
+ };
+
+ partition@100000 {
+ reg = <0x00100000 0x00700000>;
+ label = "Rescue system";
+ };
+ };
+ };
+
+ /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
+};
+
+&uart0 {
+ /* Pin header CN10 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ /* Pin header CN11 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi
index 2d76688..7450e9f 100644
--- a/dts/src/arm/armada-38x.dtsi
+++ b/dts/src/arm/armada-38x.dtsi
@@ -661,7 +661,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi
index 34cba87..de171ba 100644
--- a/dts/src/arm/armada-39x.dtsi
+++ b/dts/src/arm/armada-39x.dtsi
@@ -573,7 +573,7 @@
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/dts/src/arm/armada-xp-axpwifiap.dts b/dts/src/arm/armada-xp-axpwifiap.dts
index ce15271..1e1fc4f 100644
--- a/dts/src/arm/armada-xp-axpwifiap.dts
+++ b/dts/src/arm/armada-xp-axpwifiap.dts
@@ -62,7 +62,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
};
@@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* First mini-PCIe port */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Second mini-PCIe port */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Renesas uPD720202 USB 3.0 controller */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- };
-
internal-regs {
/* UART0 */
serial@12000 {
@@ -111,16 +89,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -145,7 +113,7 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- button@1 {
+ reset {
label = "Factory Reset Button";
linux,code = <KEY_SETUP>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -153,6 +121,38 @@
};
};
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&pciec {
+ status = "okay";
+
+ /* First mini-PCIe port */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Second mini-PCIe port */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Renesas uPD720202 USB 3.0 controller */
+ pcie@3,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+};
+
&pinctrl {
pinctrl-0 = <&phy_int_pin>;
pinctrl-names = "default";
diff --git a/dts/src/arm/armada-xp-db.dts b/dts/src/arm/armada-xp-db.dts
index 075120b..44a724d 100644
--- a/dts/src/arm/armada-xp-db.dts
+++ b/dts/src/arm/armada-xp-db.dts
@@ -67,7 +67,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
};
@@ -108,39 +108,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * All 6 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
- pcie@3,0 {
- /* Port 0, Lane 2 */
- status = "okay";
- };
- pcie@4,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -160,24 +127,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <25>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <27>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -266,6 +215,57 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * All 6 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 0, Lane 2 */
+ status = "okay";
+ };
+ pcie@4,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <25>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <27>;
+ };
+};
+
&spi0 {
status = "okay";
diff --git a/dts/src/arm/armada-xp-gp.dts b/dts/src/arm/armada-xp-gp.dts
index 190e4ec..72cb8fa 100644
--- a/dts/src/arm/armada-xp-gp.dts
+++ b/dts/src/arm/armada-xp-gp.dts
@@ -68,7 +68,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
@@ -127,27 +127,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -175,24 +154,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <16>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <17>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <18>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <19>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -251,6 +212,45 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <16>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <17>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <18>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <19>;
+ };
+};
+
&spi0 {
status = "okay";
diff --git a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts
index 8af463f..d848ae9 100644
--- a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts
+++ b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts
@@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512MB */
};
@@ -68,37 +68,11 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Quad port sata: Marvell 88SX7042 */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* USB 3.0 xHCI controller: NEC D720200F1 */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
@@ -295,6 +269,31 @@
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
};
+&pciec {
+ status = "okay";
+
+ /* Quad port sata: Marvell 88SX7042 */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* USB 3.0 xHCI controller: NEC D720200F1 */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
&pinctrl {
poweroff_pin: poweroff-pin {
diff --git a/dts/src/arm/armada-xp-linksys-mamba.dts b/dts/src/arm/armada-xp-linksys-mamba.dts
index 076f27f..83ac884 100644
--- a/dts/src/arm/armada-xp-linksys-mamba.dts
+++ b/dts/src/arm/armada-xp-linksys-mamba.dts
@@ -62,7 +62,7 @@
stdout-path = &uart0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
};
@@ -73,28 +73,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Etron EJ168 USB 3.0 controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* First mini-PCIe port */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Second mini-PCIe port */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- };
-
internal-regs {
rtc@10300 {
@@ -289,13 +267,13 @@
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- button@1 {
+ wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
- button@2 {
+ reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -323,7 +301,7 @@
4500 1>;
};
- dsa@0 {
+ dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
@@ -369,6 +347,28 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Etron EJ168 USB 3.0 controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* First mini-PCIe port */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Second mini-PCIe port */
+ pcie@3,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+};
+
&pinctrl {
keys_pin: keys-pin {
diff --git a/dts/src/arm/armada-xp-matrix.dts b/dts/src/arm/armada-xp-matrix.dts
index 6522b04..1627738 100644
--- a/dts/src/arm/armada-xp-matrix.dts
+++ b/dts/src/arm/armada-xp-matrix.dts
@@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
/*
* This board has 4 GB of RAM, but the last 256 MB of
@@ -99,18 +99,18 @@
};
};
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
-
usb@50000 {
status = "okay";
};
};
};
};
+
+&pciec {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+};
diff --git a/dts/src/arm/armada-xp-mv78230.dtsi b/dts/src/arm/armada-xp-mv78230.dtsi
index 6e6d0f0..05c164b 100644
--- a/dts/src/arm/armada-xp-mv78230.dtsi
+++ b/dts/src/arm/armada-xp-mv78230.dtsi
@@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
- pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -114,7 +114,7 @@
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -131,7 +131,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -148,7 +148,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -165,7 +165,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -182,7 +182,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
diff --git a/dts/src/arm/armada-xp-mv78260.dtsi b/dts/src/arm/armada-xp-mv78260.dtsi
index c5fdc99..07894b0 100644
--- a/dts/src/arm/armada-xp-mv78260.dtsi
+++ b/dts/src/arm/armada-xp-mv78260.dtsi
@@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
- pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -129,7 +129,7 @@
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -146,7 +146,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -163,7 +163,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -180,7 +180,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -197,7 +197,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -214,7 +214,7 @@
status = "disabled";
};
- pcie@6,0 {
+ pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -231,7 +231,7 @@
status = "disabled";
};
- pcie@7,0 {
+ pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -248,7 +248,7 @@
status = "disabled";
};
- pcie@8,0 {
+ pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -265,7 +265,7 @@
status = "disabled";
};
- pcie@9,0 {
+ pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
diff --git a/dts/src/arm/armada-xp-mv78460.dtsi b/dts/src/arm/armada-xp-mv78460.dtsi
index 0e24f1a..775bee5 100644
--- a/dts/src/arm/armada-xp-mv78460.dtsi
+++ b/dts/src/arm/armada-xp-mv78460.dtsi
@@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
- pcie-controller {
+ pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -150,7 +150,7 @@
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -167,7 +167,7 @@
status = "disabled";
};
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -184,7 +184,7 @@
status = "disabled";
};
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -201,7 +201,7 @@
status = "disabled";
};
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -218,7 +218,7 @@
status = "disabled";
};
- pcie@5,0 {
+ pcie5: pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
@@ -235,7 +235,7 @@
status = "disabled";
};
- pcie@6,0 {
+ pcie6: pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
@@ -252,7 +252,7 @@
status = "disabled";
};
- pcie@7,0 {
+ pcie7: pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
@@ -269,7 +269,7 @@
status = "disabled";
};
- pcie@8,0 {
+ pcie8: pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
@@ -286,7 +286,7 @@
status = "disabled";
};
- pcie@9,0 {
+ pcie9: pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
@@ -303,7 +303,7 @@
status = "disabled";
};
- pcie@10,0 {
+ pcie10: pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
diff --git a/dts/src/arm/armada-xp-netgear-rn2120.dts b/dts/src/arm/armada-xp-netgear-rn2120.dts
index d19f44c..a2f0e78 100644
--- a/dts/src/arm/armada-xp-netgear-rn2120.dts
+++ b/dts/src/arm/armada-xp-netgear-rn2120.dts
@@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2GB */
};
@@ -67,28 +67,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to first Marvell 88SE9170 SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to second Marvell 88SE9170 SATA controller */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Connected to Fresco Logic FL1009 USB 3.0 controller */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -97,7 +75,6 @@
};
i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
clock-frequency = <400000>;
status = "okay";
@@ -154,23 +131,19 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1318 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
+
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
@@ -295,6 +268,39 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to first Marvell 88SE9170 SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to second Marvell 88SE9170 SATA controller */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+};
+
+
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp42";
diff --git a/dts/src/arm/armada-xp-openblocks-ax3-4.dts b/dts/src/arm/armada-xp-openblocks-ax3-4.dts
index ed3b889..b577c9f 100644
--- a/dts/src/arm/armada-xp-openblocks-ax3-4.dts
+++ b/dts/src/arm/armada-xp-openblocks-ax3-4.dts
@@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
};
@@ -98,15 +98,6 @@
};
};
- pcie-controller {
- status = "okay";
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
rtc@10300 {
/* No crystal connected to the internal RTC */
@@ -148,31 +139,13 @@
#address-cells = <1>;
#size-cells = <0>;
- button@1 {
+ init {
label = "Init Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
};
};
- mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
-
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@@ -240,6 +213,33 @@
};
};
+&pciec {
+ status = "okay";
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
&pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
diff --git a/dts/src/arm/armada-xp-synology-ds414.dts b/dts/src/arm/armada-xp-synology-ds414.dts
index ae28673..e803da0 100644
--- a/dts/src/arm/armada-xp-synology-ds414.dts
+++ b/dts/src/arm/armada-xp-synology-ds414.dts
@@ -70,7 +70,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
@@ -81,28 +81,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /*
- * Connected to Marvell 88SX7042 SATA-II controller
- * handling the four disks.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /*
- * Connected to EtronTech EJ168A XHCI controller
- * providing the two rear USB 3.0 ports.
- */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Seiko S-35390A below */
@@ -150,16 +128,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy@0 { /* Marvell 88E1512 */
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 { /* Marvell 88E1512 */
- reg = <1>;
- };
- };
-
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -186,7 +154,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
- sata1_regulator: sata1-regulator {
+ sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -199,7 +167,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- sata2_regulator: sata2-regulator {
+ sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@@ -212,7 +180,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
- sata3_regulator: sata3-regulator {
+ sata3_regulator: sata3-regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@@ -225,7 +193,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- sata4_regulator: sata4-regulator {
+ sata4_regulator: sata4-regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
@@ -240,6 +208,39 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+
+&mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";
diff --git a/dts/src/arm/armada-xp.dtsi b/dts/src/arm/armada-xp.dtsi
index 4a5f99e..5274e4f 100644
--- a/dts/src/arm/armada-xp.dtsi
+++ b/dts/src/arm/armada-xp.dtsi
@@ -53,6 +53,9 @@
#include "armada-370-xp.dtsi"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
@@ -75,7 +78,7 @@
reg = <0x1400 0x500>;
};
- L2: l2-cache {
+ L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@@ -84,16 +87,6 @@
wt-override;
};
- i2c0: i2c@11000 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11000 0x100>;
- };
-
- i2c1: i2c@11100 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11100 0x100>;
- };
-
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@@ -118,7 +111,7 @@
status = "disabled";
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@@ -136,7 +129,7 @@
#clock-cells = <1>;
};
- thermal@182b0 {
+ thermal: thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@@ -150,27 +143,6 @@
clocks = <&coreclk 1>;
};
- interrupt-controller@20a00 {
- reg = <0x20a00 0x2d0>, <0x21070 0x58>;
- };
-
- timer@20300 {
- compatible = "marvell,armada-xp-timer";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- watchdog@20300 {
- compatible = "marvell,armada-xp-wdt";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x20>;
- };
-
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
@@ -184,15 +156,7 @@
status = "disabled";
};
- usb@50000 {
- clocks = <&gateclk 18>;
- };
-
- usb@51000 {
- clocks = <&gateclk 19>;
- };
-
- usb@52000 {
+ usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@@ -200,7 +164,7 @@
status = "disabled";
};
- xor@60900 {
+ xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -228,7 +192,7 @@
compatible = "marvell,armada-xp-neta";
};
- crypto@90000 {
+ cesa: crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
@@ -248,7 +212,7 @@
status = "disabled";
};
- xor@f0900 {
+ xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
@@ -309,6 +273,44 @@
};
};
+&i2c0 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x100>;
+};
+
+&mpic {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+ compatible = "marvell,armada-xp-timer";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+ compatible = "marvell,armada-xp-wdt";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+ reg = <0x20800 0x20>;
+};
+
+&usb0 {
+ clocks = <&gateclk 18>;
+};
+
+&usb1 {
+ clocks = <&gateclk 19>;
+};
+
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =
diff --git a/dts/src/arm/artpec6-devboard.dts b/dts/src/arm/artpec6-devboard.dts
index f823ed3..9dfe845 100644
--- a/dts/src/arm/artpec6-devboard.dts
+++ b/dts/src/arm/artpec6-devboard.dts
@@ -46,6 +46,10 @@
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
&ethernet {
status = "okay";
diff --git a/dts/src/arm/artpec6.dtsi b/dts/src/arm/artpec6.dtsi
index 3489019..767cbe8 100644
--- a/dts/src/arm/artpec6.dtsi
+++ b/dts/src/arm/artpec6.dtsi
@@ -67,7 +67,7 @@
};
};
- syscon {
+ syscon: syscon@f8000000 {
compatible = "axis,artpec6-syscon", "syscon";
reg = <0xf8000000 0x48>;
};
@@ -154,6 +154,33 @@
interrupt-parent = <&intc>;
};
+ pcie: pcie@f8050000 {
+ compatible = "axis,artpec6-pcie", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8040000 0x1000
+ 0xc0000000 0x2000>;
+ reg-names = "dbi", "phy", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ /* downstream I/O */
+ ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ axis,syscon-pcie = <&syscon>;
+ status = "disabled";
+ };
+
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
diff --git a/dts/src/arm/at91-sama5d4_ma5d4.dtsi b/dts/src/arm/at91-sama5d4_ma5d4.dtsi
index a92c6e0..b5a5a91 100644
--- a/dts/src/arm/at91-sama5d4_ma5d4.dtsi
+++ b/dts/src/arm/at91-sama5d4_ma5d4.dtsi
@@ -12,8 +12,8 @@
#include "sama5d4.dtsi"
/ {
- model = "DENX MA5D4";
- compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4";
+ compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;
diff --git a/dts/src/arm/at91-sama5d4_ma5d4evk.dts b/dts/src/arm/at91-sama5d4_ma5d4evk.dts
index eac4ea2..84be29f 100644
--- a/dts/src/arm/at91-sama5d4_ma5d4evk.dts
+++ b/dts/src/arm/at91-sama5d4_ma5d4evk.dts
@@ -13,8 +13,8 @@
#include "at91-sama5d4_ma5d4.dtsi"
/ {
- model = "DENX MA5D4EVK";
- compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4EVK";
+ compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
chosen {
stdout-path = "serial3:115200n8";
diff --git a/dts/src/arm/at91rm9200.dtsi b/dts/src/arm/at91rm9200.dtsi
index 4e913c2..f057e0b 100644
--- a/dts/src/arm/at91rm9200.dtsi
+++ b/dts/src/arm/at91rm9200.dtsi
@@ -481,8 +481,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
- AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi
index a3e363d..9e035b2 100644
--- a/dts/src/arm/at91sam9260.dtsi
+++ b/dts/src/arm/at91sam9260.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
+ <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9260ek.dts b/dts/src/arm/at91sam9260ek.dts
index 2c87f58..b2578fe 100644
--- a/dts/src/arm/at91sam9260ek.dts
+++ b/dts/src/arm/at91sam9260ek.dts
@@ -174,14 +174,14 @@
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
- gpio-key,wakeup;
+ wakeup-source;
};
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
- gpio-key,wakeup;
+ wakeup-source;
};
};
diff --git a/dts/src/arm/at91sam9261.dtsi b/dts/src/arm/at91sam9261.dtsi
index 32752d7..3fe77c3 100644
--- a/dts/src/arm/at91sam9261.dtsi
+++ b/dts/src/arm/at91sam9261.dtsi
@@ -302,8 +302,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi
index aeb1a36..a1888f6 100644
--- a/dts/src/arm/at91sam9263.dtsi
+++ b/dts/src/arm/at91sam9263.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
- AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
+ <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index b3501ae..e567d5f 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -478,8 +478,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi
index 3b3eb3e..f43d769 100644
--- a/dts/src/arm/at91sam9n12.dtsi
+++ b/dts/src/arm/at91sam9n12.dtsi
@@ -500,8 +500,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi
index 70adf94..f4c129a 100644
--- a/dts/src/arm/at91sam9rl.dtsi
+++ b/dts/src/arm/at91sam9rl.dtsi
@@ -438,8 +438,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi
index ed4e4bd..f66bae9 100644
--- a/dts/src/arm/at91sam9x5.dtsi
+++ b/dts/src/arm/at91sam9x5.dtsi
@@ -460,8 +460,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi
index fabc9f3..8833a4c 100644
--- a/dts/src/arm/bcm-cygnus.dtsi
+++ b/dts/src/arm/bcm-cygnus.dtsi
@@ -91,6 +91,13 @@
#address-cells = <1>;
#size-cells = <1>;
+ otp: otp@0301c800 {
+ compatible = "brcm,ocotp";
+ reg = <0x0301c800 0x2c>;
+ brcm,ocotp-size = <2048>;
+ status = "disabled";
+ };
+
pcie_phy: phy@0301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
@@ -108,12 +115,21 @@
};
};
- pinctrl: pinctrl@0x0301d0c8 {
+ pinctrl: pinctrl@0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
};
+ mailbox: mailbox@03024024 {
+ compatible = "brcm,iproc-mailbox";
+ reg = <0x03024024 0x40>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ #mbox-cells = <1>;
+ };
+
gpio_crmu: gpio@03024800 {
compatible = "brcm,cygnus-crmu-gpio";
reg = <0x03024800 0x50>,
@@ -121,6 +137,9 @@
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
+ interrupt-controller;
+ interrupt-parent = <&mailbox>;
+ interrupts = <0>;
};
i2c0: i2c@18008000 {
diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi
index 7c9e0fa..b6142bd 100644
--- a/dts/src/arm/bcm-nsp.dtsi
+++ b/dts/src/arm/bcm-nsp.dtsi
@@ -160,7 +160,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x0011ba08>;
+ ranges = <0x00000000 0x18000000 0x0011c40a>;
#address-cells = <1>;
#size-cells = <1>;
@@ -241,6 +241,16 @@
brcm,nand-has-wp;
};
+ gpiob: gpio@30000 {
+ compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
+ reg = <0x30000 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <4>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pwm: pwm@31000 {
compatible = "brcm,iproc-pwm";
reg = <0x31000 0x28>;
@@ -254,6 +264,35 @@
reg = <0x33000 0x14>;
};
+ qspi: qspi@27200 {
+ compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+ reg = <0x027200 0x184>,
+ <0x027000 0x124>,
+ <0x11c408 0x004>,
+ <0x0273a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs",
+ "intr_status_reg";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overhead",
+ "mspi_done",
+ "mspi_halted";
+ clocks = <&iprocmed>;
+ clock-names = "iprocmed";
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccbtimer0: timer@34000 {
compatible = "arm,sp804";
reg = <0x34000 0x1000>;
diff --git a/dts/src/arm/bcm2835-rpi-a-plus.dts b/dts/src/arm/bcm2835-rpi-a-plus.dts
index f7f9db3..d070454 100644
--- a/dts/src/arm/bcm2835-rpi-a-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-a-plus.dts
@@ -22,7 +22,72 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ /*
+ * This is based on the unreleased schematic for the Model A+.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "USB_LIMIT", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/dts/src/arm/bcm2835-rpi-a.dts b/dts/src/arm/bcm2835-rpi-a.dts
index 8be102f..46d078e 100644
--- a/dts/src/arm/bcm2835-rpi-a.dts
+++ b/dts/src/arm/bcm2835-rpi-a.dts
@@ -15,7 +15,74 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_GPIO1",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO0",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/dts/src/arm/bcm2835-rpi-b-plus.dts b/dts/src/arm/bcm2835-rpi-b-plus.dts
index 35cde65..432088e 100644
--- a/dts/src/arm/bcm2835-rpi-b-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-b-plus.dts
@@ -23,7 +23,73 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ /*
+ * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf
+ * RPI-BPLUS sheet 1
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "LAN_RUN", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "USB_LIMIT", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "ETHCLK", /* GPIO44 */
+ "PWM1_OUT", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/dts/src/arm/bcm2835-rpi-b-rev2.dts b/dts/src/arm/bcm2835-rpi-b-rev2.dts
index 84df85e..4133bc2 100644
--- a/dts/src/arm/bcm2835-rpi-b-rev2.dts
+++ b/dts/src/arm/bcm2835-rpi-b-rev2.dts
@@ -16,7 +16,73 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ /*
+ * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf
+ * RPI00022 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_CLK",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "CAM_GPIO",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts
index 8e626a8..4d56fe3 100644
--- a/dts/src/arm/bcm2835-rpi-b.dts
+++ b/dts/src/arm/bcm2835-rpi-b.dts
@@ -16,7 +16,74 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &alt3>;
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "CAM_GPIO1",
+ "LAN_RUN",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "STATUS_LED_N",
+ "GPIO17",
+ "GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO0",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "PWM0_OUT",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "PWM1_OUT",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
diff --git a/dts/src/arm/bcm2835-rpi-zero.dts b/dts/src/arm/bcm2835-rpi-zero.dts
index 60e359f..cc8b832 100644
--- a/dts/src/arm/bcm2835-rpi-zero.dts
+++ b/dts/src/arm/bcm2835-rpi-zero.dts
@@ -26,7 +26,72 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "SDA0",
+ "SCL0",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "NC", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "NC", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED_N",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi
index e9b47b2..6ddf7df 100644
--- a/dts/src/arm/bcm2835-rpi.dtsi
+++ b/dts/src/arm/bcm2835-rpi.dtsi
@@ -39,22 +39,21 @@
};
alt0: alt0 {
- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+ brcm,pins = <4 5 7 8 9 10 11 14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
-
- alt3: alt3 {
- brcm,pins = <48 49 50 51 52 53>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
};
&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_gpio0>;
status = "okay";
clock-frequency = <100000>;
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_gpio2>;
status = "okay";
clock-frequency = <100000>;
};
@@ -64,11 +63,15 @@
};
&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
};
diff --git a/dts/src/arm/bcm2835.dtsi b/dts/src/arm/bcm2835.dtsi
index a78759e..0890d97 100644
--- a/dts/src/arm/bcm2835.dtsi
+++ b/dts/src/arm/bcm2835.dtsi
@@ -23,3 +23,9 @@
};
};
};
+
+/* enable thermal sensor with the correct compatible property set */
+&thermal {
+ compatible = "brcm,bcm2835-thermal";
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2836-rpi-2-b.dts b/dts/src/arm/bcm2836-rpi-2-b.dts
index 39dccf6..bf19e8c 100644
--- a/dts/src/arm/bcm2836-rpi-2-b.dts
+++ b/dts/src/arm/bcm2836-rpi-2-b.dts
@@ -27,7 +27,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/dts/src/arm/bcm2836.dtsi b/dts/src/arm/bcm2836.dtsi
index 9d0651d..519a44f 100644
--- a/dts/src/arm/bcm2836.dtsi
+++ b/dts/src/arm/bcm2836.dtsi
@@ -76,3 +76,9 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
+
+/* enable thermal sensor with the correct compatible property set */
+&thermal {
+ compatible = "brcm,bcm2836-thermal";
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi
index 46d46d8..9a44da1 100644
--- a/dts/src/arm/bcm283x.dtsi
+++ b/dts/src/arm/bcm283x.dtsi
@@ -104,7 +104,7 @@
reg = <0x7e104000 0x10>;
};
- mailbox: mailbox@7e00b800 {
+ mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
@@ -132,6 +132,209 @@
interrupt-controller;
#interrupt-cells = <2>;
+
+ /* Defines pin muxing groups according to
+ * BCM2835-ARM-Peripherals.pdf page 102.
+ *
+ * While each pin can have its mux selected
+ * for various functions individually, some
+ * groups only make sense to switch to a
+ * particular function together.
+ */
+ dpi_gpio0: dpi_gpio0 {
+ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
+ 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ emmc_gpio22: emmc_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ emmc_gpio34: emmc_gpio34 {
+ brcm,pins = <34 35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_OFF
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP>;
+ };
+ emmc_gpio48: emmc_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ gpclk0_gpio4: gpclk0_gpio4 {
+ brcm,pins = <4>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio5: gpclk1_gpio5 {
+ brcm,pins = <5>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio42: gpclk1_gpio42 {
+ brcm,pins = <42>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio44: gpclk1_gpio44 {
+ brcm,pins = <44>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio6: gpclk2_gpio6 {
+ brcm,pins = <6>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio43: gpclk2_gpio43 {
+ brcm,pins = <43>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ i2c0_gpio0: i2c0_gpio0 {
+ brcm,pins = <0 1>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio32: i2c0_gpio32 {
+ brcm,pins = <32 34>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio44: i2c0_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT1>;
+ };
+ i2c1_gpio2: i2c1_gpio2 {
+ brcm,pins = <2 3>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c1_gpio44: i2c1_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ jtag_gpio22: jtag_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ pcm_gpio18: pcm_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pcm_gpio28: pcm_gpio28 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ sdhost_gpio48: sdhost_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ spi0_gpio7: spi0_gpio7 {
+ brcm,pins = <7 8 9 10 11>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi0_gpio35: spi0_gpio35 {
+ brcm,pins = <35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi1_gpio16: spi1_gpio16 {
+ brcm,pins = <16 17 18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ spi2_gpio40: spi2_gpio40 {
+ brcm,pins = <40 41 42 43 44 45>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ uart0_gpio14: uart0_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ /* Separate from the uart0_gpio14 group
+ * because it conflicts with spi1_gpio16, and
+ * people often run uart0 on the two pins
+ * without flow contrl.
+ */
+ uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_gpio30: uart0_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ uart1_gpio14: uart1_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio32: uart1_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio36: uart1_gpio36 {
+ brcm,pins = <36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ uart1_gpio40: uart1_gpio40 {
+ brcm,pins = <40 41>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
+ brcm,pins = <42 43>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
};
uart0: serial@7e201000 {
@@ -187,6 +390,13 @@
interrupts = <2 14>; /* pwa1 */
};
+ thermal: thermal@7e212000 {
+ compatible = "brcm,bcm2835-thermal";
+ reg = <0x7e212000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ status = "disabled";
+ };
+
aux: aux@0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
diff --git a/dts/src/arm/bcm4708-luxul-xap-1510.dts b/dts/src/arm/bcm4708-luxul-xap-1510.dts
new file mode 100644
index 0000000..35e6ed6
--- /dev/null
+++ b/dts/src/arm/bcm4708-luxul-xap-1510.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+ compatible = "luxul,xap-1510v1", "brcm,bcm4708";
+ model = "Luxul XAP-1510 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ };
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi_nor {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm4709-asus-rt-ac87u.dts b/dts/src/arm/bcm4709-asus-rt-ac87u.dts
index 8ade7de..eac0f52 100644
--- a/dts/src/arm/bcm4709-asus-rt-ac87u.dts
+++ b/dts/src/arm/bcm4709-asus-rt-ac87u.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
index 0653e7e..aab39c9 100644
--- a/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/dts/src/arm/bcm4709-netgear-r7000.dts b/dts/src/arm/bcm4709-netgear-r7000.dts
index a22ed14..fd38d2a 100644
--- a/dts/src/arm/bcm4709-netgear-r7000.dts
+++ b/dts/src/arm/bcm4709-netgear-r7000.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
diff --git a/dts/src/arm/bcm4709-netgear-r8000.dts b/dts/src/arm/bcm4709-netgear-r8000.dts
index ca18151..92f8a72 100644
--- a/dts/src/arm/bcm4709-netgear-r8000.dts
+++ b/dts/src/arm/bcm4709-netgear-r8000.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm4709.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
@@ -107,6 +107,10 @@
};
};
+&uart0 {
+ status = "okay";
+};
+
&usb2 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
new file mode 100644
index 0000000..9a92c24
--- /dev/null
+++ b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4709.dtsi"
+
+/ {
+ compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708";
+ model = "TP-LINK Archer C9 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ label = "bcm53xx:blue:lan";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:blue:usb3";
+ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb2 {
+ label = "bcm53xx:blue:usb2";
+ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-blue {
+ label = "bcm53xx:blue:wan";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-amber {
+ label = "bcm53xx:amber:wan";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ power {
+ label = "bcm53xx:blue:power";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+};
+
+&spi_nor {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm4709.dtsi b/dts/src/arm/bcm4709.dtsi
new file mode 100644
index 0000000..f039765
--- /dev/null
+++ b/dts/src/arm/bcm4709.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm4708.dtsi"
+
+&uart0 {
+ clock-frequency = <125000000>;
+};
diff --git a/dts/src/arm/bcm47094-dlink-dir-885l.dts b/dts/src/arm/bcm47094-dlink-dir-885l.dts
index c8c0b36..661348d 100644
--- a/dts/src/arm/bcm47094-dlink-dir-885l.dts
+++ b/dts/src/arm/bcm47094-dlink-dir-885l.dts
@@ -9,7 +9,7 @@
/dts-v1/;
-#include "bcm4708.dtsi"
+#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch1.dtsi"
/ {
@@ -107,7 +107,6 @@
&uart0 {
status = "okay";
- clock-frequency = <125000000>;
};
&usb3 {
diff --git a/dts/src/arm/bcm47094-luxul-xwr-3100.dts b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
new file mode 100644
index 0000000..169b35f
--- /dev/null
+++ b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch4.dtsi"
+
+/ {
+ compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Luxul XWR-3100 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "bcm53xx:green:power";
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ lan3 {
+ label = "bcm53xx:green:lan1";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan4 {
+ label = "bcm53xx:green:lan0";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan {
+ label = "bcm53xx:green:wan";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan1 {
+ label = "bcm53xx:green:lan3";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan2 {
+ label = "bcm53xx:green:lan2";
+ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:green:usb3";
+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+
+ 2ghz {
+ label = "bcm53xx:green:2ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:green:5ghz";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+};
+
+&spi_nor {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm47094-netgear-r8500.dts b/dts/src/arm/bcm47094-netgear-r8500.dts
new file mode 100644
index 0000000..521b415
--- /dev/null
+++ b/dts/src/arm/bcm47094-netgear-r8500.dts
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Netgear R8500";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power0 {
+ label = "bcm53xx:white:power";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ power1 {
+ label = "bcm53xx:amber:power";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz-1 {
+ label = "bcm53xx:white:5ghz-1";
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz-2 {
+ label = "bcm53xx:white:5ghz-2";
+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ 2ghz {
+ label = "bcm53xx:white:2ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb2 {
+ label = "bcm53xx:white:usb2";
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:white:usb3";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brightness {
+ label = "Backlight";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ };
+
+ rfkill {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm47094.dtsi b/dts/src/arm/bcm47094.dtsi
new file mode 100644
index 0000000..4f09aa0
--- /dev/null
+++ b/dts/src/arm/bcm47094.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm4708.dtsi"
+
+/ {
+ usb3_phy: usb3-phy {
+ compatible = "brcm,ns-bx-usb3-phy";
+ };
+};
+
+&uart0 {
+ clock-frequency = <125000000>;
+};
diff --git a/dts/src/arm/bcm47189-tenda-ac9.dts b/dts/src/arm/bcm47189-tenda-ac9.dts
new file mode 100644
index 0000000..4403ae8
--- /dev/null
+++ b/dts/src/arm/bcm47189-tenda-ac9.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm53573.dtsi"
+
+/ {
+ compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573";
+ model = "Tenda AC9";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usb {
+ label = "bcm53xx:blue:usb";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ system {
+ label = "bcm53xx:blue:system";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rfkill {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm5301x-nand-cs0-bch4.dtsi b/dts/src/arm/bcm5301x-nand-cs0-bch4.dtsi
new file mode 100644
index 0000000..b4e875d
--- /dev/null
+++ b/dts/src/arm/bcm5301x-nand-cs0-bch4.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2016 Luxul Inc.
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm5301x-nand-cs0.dtsi"
+
+&nandcs {
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index ae4b388..f09a2bb 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -149,6 +149,13 @@
clock-names = "phy-ref-clk";
};
+ usb3_phy: usb3-phy {
+ compatible = "brcm,ns-ax-usb3-phy";
+ reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
+ reg-names = "dmp", "ccb-mii";
+ #phy-cells = <0>;
+ };
+
axi@18000000 {
compatible = "brcm,bus-axi";
reg = <0x18000000 0x1000>;
diff --git a/dts/src/arm/bcm53573.dtsi b/dts/src/arm/bcm53573.dtsi
new file mode 100644
index 0000000..e2c496a
--- /dev/null
+++ b/dts/src/arm/bcm53573.dtsi
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ };
+ };
+
+ mpcore {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18310000 0x00008000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x0100>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ alp: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ };
+ };
+
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x000fffff 0xffff>;
+ interrupt-map =
+ /* ChipCommon */
+ <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* IEEE 802.11 0 */
+ <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 0 */
+ <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 2.0 Controller */
+ <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 0 */
+ <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* IEEE 802.11 1 */
+ <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 1 */
+ <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ chipcommon: chipcommon@0 {
+ compatible = "simple-bus";
+ reg = <0x00000000 0x1000>;
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ uart0: serial@0300 {
+ compatible = "ns16550a";
+ reg = <0x0300 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&alp>;
+ status = "okay";
+ };
+ };
+
+ usb2: usb2@4000 {
+ reg = <0x4000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ehci: ehci@4000 {
+ compatible = "generic-ehci";
+ reg = <0x4000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ohci: ohci@d000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ohci";
+ reg = <0xd000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gmac0: ethernet@5000 {
+ reg = <0x5000 0x1000>;
+ };
+
+ gmac1: ethernet@b000 {
+ reg = <0xb000 0x1000>;
+ };
+
+ pmu@12000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x00012000 0x00001000>;
+
+ ilp: ilp {
+ compatible = "brcm,bcm53573-ilp";
+ clocks = <&alp>;
+ #clock-cells = <0>;
+ clock-output-names = "ilp";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts
index 05c5f98..59d96fb 100644
--- a/dts/src/arm/bcm958625k.dts
+++ b/dts/src/arm/bcm958625k.dts
@@ -139,3 +139,37 @@
groups = "nand_grp";
};
};
+
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
diff --git a/dts/src/arm/berlin2q-marvell-dmp.dts b/dts/src/arm/berlin2q-marvell-dmp.dts
index f485308..57aa5f8 100644
--- a/dts/src/arm/berlin2q-marvell-dmp.dts
+++ b/dts/src/arm/berlin2q-marvell-dmp.dts
@@ -48,7 +48,7 @@
reg = <0x00000000 0x80000000>;
};
- choosen {
+ chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
@@ -58,7 +58,7 @@
#address-cells = <1>;
#size-cells = <0>;
- reg_usb0_vbus: regulator@0 {
+ reg_usb0_vbus: regulator_usb0 {
compatible = "regulator-fixed";
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
@@ -67,7 +67,7 @@
enable-active-high;
};
- reg_usb1_vbus: regulator@1 {
+ reg_usb1_vbus: regulator_usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -76,7 +76,7 @@
enable-active-high;
};
- reg_usb2_vbus: regulator@2 {
+ reg_usb2_vbus: regulator_usb2 {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
@@ -85,7 +85,7 @@
enable-active-high;
};
- reg_sdio1_vmmc: regulator@3 {
+ reg_sdio1_vmmc: regulator_sdio1_vmmc {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -95,7 +95,7 @@
gpio = <&portb 21 GPIO_ACTIVE_HIGH>;
};
- reg_sdio1_vqmmc: regulator@4 {
+ reg_sdio1_vqmmc: regulator_sido1_vqmmc {
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
diff --git a/dts/src/arm/cloudengines-pogoplug-series-3.dts b/dts/src/arm/cloudengines-pogoplug-series-3.dts
new file mode 100644
index 0000000..bfde32e
--- /dev/null
+++ b/dts/src/arm/cloudengines-pogoplug-series-3.dts
@@ -0,0 +1,94 @@
+/*
+ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+ model = "Cloud Engines PogoPlug Series 3";
+
+ compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ /* 128Mbytes DDR */
+ reg = <0x60000000 0x8000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "pogoplug:blue";
+ gpios = <&gpio0 2 0>;
+ default-state = "keep";
+ };
+
+ orange {
+ label = "pogoplug:orange";
+ gpios = <&gpio1 16 1>;
+ default-state = "keep";
+ };
+
+ green {
+ label = "pogoplug:green";
+ gpios = <&gpio1 17 1>;
+ default-state = "keep";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "hamming";
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00e00000>;
+ read-only;
+ };
+
+ partition@e00000 {
+ label = "ubi";
+ reg = <0x00e00000 0x07200000>;
+ };
+ };
+};
+
+&etha {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_etha_mdio>;
+};
diff --git a/dts/src/arm/da850-lcdk.dts b/dts/src/arm/da850-lcdk.dts
index 7b8ab21..afcb482 100644
--- a/dts/src/arm/da850-lcdk.dts
+++ b/dts/src/arm/da850-lcdk.dts
@@ -13,6 +13,7 @@
aliases {
serial2 = &serial2;
+ ethernet0 = &eth0;
};
chosen {
@@ -122,7 +123,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -158,6 +159,14 @@
rx-num-evt = <32>;
};
+&usb_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
@@ -219,3 +228,11 @@
};
};
};
+
+&prictrl {
+ status = "okay";
+};
+
+&memctrl {
+ status = "okay";
+};
diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi
index f79e1b9..104155d 100644
--- a/dts/src/arm/da850.dtsi
+++ b/dts/src/arm/da850.dtsi
@@ -36,6 +36,7 @@
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
@@ -186,8 +187,44 @@
0xc 0x88888888 0xffffffff
>;
};
+ lcd_pins: pinmux_lcd_pins {
+ pinctrl-single,bits = <
+ /*
+ * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
+ * LCD_D[6], LCD_D[7]
+ */
+ 0x40 0x22222200 0xffffff00
+ /*
+ * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
+ * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
+ */
+ 0x44 0x22222222 0xffffffff
+ /* LCD_D[8], LCD_D[9] */
+ 0x48 0x00000022 0x000000ff
+
+ /* LCD_PCLK */
+ 0x48 0x02000000 0x0f000000
+ /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
+ 0x4c 0x02000022 0x0f0000ff
+ >;
+ };
};
+ prictrl: priority-controller@14110 {
+ compatible = "ti,da850-mstpri";
+ reg = <0x14110 0x0c>;
+ status = "disabled";
+ };
+ cfgchip: chip-controller@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy: usb-phy {
+ compatible = "ti,da830-usb-phy";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
@@ -280,6 +317,8 @@
mmc0: mmc@40000 {
compatible = "ti,da830-mmc";
reg = <0x40000 0x1000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
interrupts = <16>;
dmas = <&edma0 16 0>, <&edma0 17 0>;
dma-names = "rx", "tx";
@@ -288,6 +327,8 @@
mmc1: mmc@21b000 {
compatible = "ti,da830-mmc";
reg = <0x21b000 0x1000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
interrupts = <72>;
dmas = <&edma1 28 0>, <&edma1 29 0>;
dma-names = "rx", "tx";
@@ -336,6 +377,8 @@
num-cs = <6>;
ti,davinci-spi-intr-line = <1>;
interrupts = <20>;
+ dmas = <&edma0 14 0>, <&edma0 15 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi1: spi@30e000 {
@@ -350,6 +393,16 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ usb0: usb@200000 {
+ compatible = "ti,da830-musb";
+ reg = <0x200000 0x10000>;
+ interrupts = <58>;
+ interrupt-names = "mc";
+ dr_mode = "otg";
+ phys = <&usb_phy 0>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ };
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
@@ -386,6 +439,11 @@
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
};
+ pinconf: pin-controller@22c00c {
+ compatible = "ti,da850-pupd";
+ reg = <0x22c00c 0x8>;
+ status = "disabled";
+ };
mcasp0: mcasp@100000 {
compatible = "ti,da830-mcasp-audio";
@@ -399,6 +457,13 @@
<&edma0 0 1>;
dma-names = "tx", "rx";
};
+
+ display: display@213000 {
+ compatible = "ti,da850-tilcdc";
+ reg = <0x213000 0x1000>;
+ interrupts = <52>;
+ status = "disabled";
+ };
};
aemif: aemif@68000000 {
compatible = "ti,da850-aemif";
@@ -410,4 +475,9 @@
1 0 0x68000000 0x00008000>;
status = "disabled";
};
+ memctrl: memory-controller@b0000000 {
+ compatible = "ti,da850-ddr-controller";
+ reg = <0xb0000000 0xe8>;
+ status = "disabled";
+ };
};
diff --git a/dts/src/arm/dm814x.dtsi b/dts/src/arm/dm814x.dtsi
index ff90a6c..1facc5f 100644
--- a/dts/src/arm/dm814x.dtsi
+++ b/dts/src/arm/dm814x.dtsi
@@ -373,6 +373,7 @@
reg = <0x800 0x438>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x307ff>;
};
diff --git a/dts/src/arm/dm816x.dtsi b/dts/src/arm/dm816x.dtsi
index f1e0f77..61dd2f6 100644
--- a/dts/src/arm/dm816x.dtsi
+++ b/dts/src/arm/dm816x.dtsi
@@ -83,6 +83,7 @@
reg = <0x48140000 0x21000>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges = <0 0x48140000 0x21000>;
dm816x_pinmux: pinmux@800 {
@@ -90,6 +91,7 @@
reg = <0x800 0x50a>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xf>;
};
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index d4fcd68..addb753 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -171,6 +171,7 @@
reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
diff --git a/dts/src/arm/dra71-evm.dts b/dts/src/arm/dra71-evm.dts
new file mode 100644
index 0000000..2b9a5a8
--- /dev/null
+++ b/dts/src/arm/dra71-evm.dts
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
+ model = "TI DRA718 EVM";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+ };
+
+ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "vddshv8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ vin-supply = <&evm_5v0>;
+
+ gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3000000 0x1>;
+ };
+
+ poweroff: gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lp8733: lp8733@60 {
+ compatible = "ti,lp8733";
+ reg = <0x60>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&evm_5v0>;
+ ldo1-in-supply =<&evm_5v0>;
+
+ lp8733_regulators: regulators {
+ lp8733_buck0_reg: buck0 {
+ /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
+ regulator-name = "lp8733-buck0";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_buck1_reg: buck1 {
+ /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
+ regulator-name = "lp8733-buck1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8733_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
+ regulator-name = "lp8733-ldo0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lp8733_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
+ regulator-name = "lp8733-ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ lp8732: lp8732@61 {
+ compatible = "ti,lp8732";
+ reg = <0x61>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&vsys_3v3>;
+ ldo1-in-supply =<&vsys_3v3>;
+
+ lp8732_regulators: regulators {
+ lp8732_buck0_reg: buck0 {
+ /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
+ regulator-name = "lp8732-buck0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8732_buck1_reg: buck1 {
+ /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
+ regulator-name = "lp8732-buck1";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
+ regulator-name = "lp8732-ldo0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
+ regulator-name = "lp8732-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio7>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&pcf_hdmi {
+ p0 {
+ /*
+ * PM_OEn to High: Disable routing I2C3 to PM_I2C
+ * With this PM_SEL(p3) should not matter
+ */
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "pm_oe_n";
+ };
+};
+
+&mmc1 {
+ vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mac {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+ <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
+ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+};
+
+/* No Sata on this device */
+&sata_phy {
+ status = "disabled";
+};
+
+&sata {
+ status = "disabled";
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&dss {
+ /* Supplied by VDA_1V8_PLL */
+ vdda_video-supply = <&lp8732_ldo0_reg>;
+};
+
+&hdmi {
+ /* Supplied by VDA_1V8_PHY */
+ vdda_video-supply = <&lp8732_ldo1_reg>;
+};
diff --git a/dts/src/arm/dra72-evm-common.dtsi b/dts/src/arm/dra72-evm-common.dtsi
index c94d8d6..e50fbee 100644
--- a/dts/src/arm/dra72-evm-common.dtsi
+++ b/dts/src/arm/dra72-evm-common.dtsi
@@ -18,11 +18,49 @@
display0 = &hdmi0;
};
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_5v0: fixedregulator-evm5v0 {
+ /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
evm_3v3_sw: fixedregulator-evm_3v3 {
+ /* TPS22965DSG */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
};
aic_dvdd: fixedregulator-aic_dvdd {
@@ -39,6 +77,7 @@
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_3v3_sw>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
@@ -69,9 +108,6 @@
tpd12s015: encoder {
compatible = "ti,tpd12s015";
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
@@ -134,72 +170,6 @@
};
&dra7_pmx_core {
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- nand_default: nand_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
- DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
- DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- usb2_pins: pinmux_usb2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
- >;
- };
-
- tps65917_pins_default: tps65917_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
- >;
- };
-
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
@@ -240,161 +210,12 @@
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
- >;
- };
-
- atl_pins: pinmux_atl_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
- DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
- >;
- };
-
- mcasp3_pins: pinmux_mcasp3_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
- DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
- DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
- >;
- };
-
- mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
- >;
- };
};
&i2c1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
- tps65917: tps65917@58 {
- compatible = "ti,tps65917";
- reg = <0x58>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tps65917_pins_default>;
-
- interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
- interrupt-controller;
- #interrupt-cells = <2>;
-
- ti,system-power-controller;
-
- tps65917_pmic {
- compatible = "ti,tps65917-pmic";
-
- tps65917_regulators: regulators {
- smps1_reg: smps1 {
- /* VDD_MPU */
- regulator-name = "smps1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps2_reg: smps2 {
- /* VDD_CORE */
- regulator-name = "smps2";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_GPU IVA DSPEVE */
- regulator-name = "smps3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps4_reg: smps4 {
- /* VDDS1V8 */
- regulator-name = "smps4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps5_reg: smps5 {
- /* VDD_DDR */
- regulator-name = "smps5";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /* LDO1_OUT --> SDIO */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-allow-bypass;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PLL */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
- };
- };
-
- tps65917_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps65917>;
- interrupts = <1 IRQ_TYPE_NONE>;
- wakeup-source;
- ti,palmas-long-press-seconds = <6>;
- };
- };
-
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
@@ -423,8 +244,6 @@
&i2c5 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
@@ -462,8 +281,6 @@
&gpmc {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&nand_default>;
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
@@ -548,14 +365,6 @@
};
};
-&usb2_phy1 {
- phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldo4_reg>;
-};
-
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
@@ -566,14 +375,10 @@
&usb1 {
dr_mode = "peripheral";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_pins>;
};
&mmc1 {
@@ -581,7 +386,6 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&evm_3v3_sd>;
- vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
@@ -603,71 +407,8 @@
max-frequency = <192000000>;
};
-&dra7_pmx_core {
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
- >;
-
- };
-
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
-
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
- >;
- };
-};
-
&mac {
status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_default>;
- pinctrl-1 = <&cpsw_sleep>;
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- pinctrl-1 = <&davinci_mdio_sleep>;
};
&dcan1 {
@@ -741,16 +482,11 @@
&dss {
status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
status = "ok";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
@@ -759,9 +495,6 @@
};
&atl {
- pinctrl-names = "default";
- pinctrl-0 = <&atl_pins>;
-
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
@@ -780,9 +513,6 @@
&mcasp3 {
#sound-dai-cells = <0>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mcasp3_pins>;
- pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
diff --git a/dts/src/arm/dra72-evm-revc.dts b/dts/src/arm/dra72-evm-revc.dts
index 064b322..c3d939c 100644
--- a/dts/src/arm/dra72-evm-revc.dts
+++ b/dts/src/arm/dra72-evm-revc.dts
@@ -17,17 +17,22 @@
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> VDDA_1V8_PHY2 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+ /* LDO2_OUT --> VDDA_1V8_PHY2 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
&hdmi {
vdda-supply = <&ldo2_reg>;
};
@@ -59,15 +64,17 @@
&davinci_mdio {
dp83867_0: ethernet-phy@2 {
reg = <2>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-impedance;
};
dp83867_1: ethernet-phy@3 {
reg = <3>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-imepdance;
};
};
diff --git a/dts/src/arm/dra72-evm-tps65917.dtsi b/dts/src/arm/dra72-evm-tps65917.dtsi
new file mode 100644
index 0000000..ee6dac4
--- /dev/null
+++ b/dts/src/arm/dra72-evm-tps65917.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ */
+
+&tps65917 {
+ compatible = "ti,tps65917";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+};
diff --git a/dts/src/arm/dra72-evm.dts b/dts/src/arm/dra72-evm.dts
index e3a9b69..cd9c4ff 100644
--- a/dts/src/arm/dra72-evm.dts
+++ b/dts/src/arm/dra72-evm.dts
@@ -15,16 +15,16 @@
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> TP1017 (UNUSED) */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-allow-bypass;
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
&hdmi {
vdda-supply = <&ldo3_reg>;
};
diff --git a/dts/src/arm/emev2.dtsi b/dts/src/arm/emev2.dtsi
index cd11940..0124faf 100644
--- a/dts/src/arm/emev2.dtsi
+++ b/dts/src/arm/emev2.dtsi
@@ -8,13 +8,14 @@
* kind, whether express or implied.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "renesas,emev2";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
aliases {
gpio0 = &gpio0;
diff --git a/dts/src/arm/exynos3250-artik5-eval.dts b/dts/src/arm/exynos3250-artik5-eval.dts
index be4d6aa..4bd2ee8 100644
--- a/dts/src/arm/exynos3250-artik5-eval.dts
+++ b/dts/src/arm/exynos3250-artik5-eval.dts
@@ -28,7 +28,7 @@
vqmmc-supply = <&ldo3_reg>;
card-detect-delay = <200>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/dts/src/arm/exynos3250-artik5.dtsi b/dts/src/arm/exynos3250-artik5.dtsi
index a70819b..59c89d7 100644
--- a/dts/src/arm/exynos3250-artik5.dtsi
+++ b/dts/src/arm/exynos3250-artik5.dtsi
@@ -310,7 +310,7 @@
card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts
index 66f04f6..cccfe4b 100644
--- a/dts/src/arm/exynos3250-monk.dts
+++ b/dts/src/arm/exynos3250-monk.dts
@@ -435,7 +435,7 @@
card-detect-delay = <200>;
vmmc-supply = <&vemmc_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/dts/src/arm/exynos3250-pinctrl.dtsi b/dts/src/arm/exynos3250-pinctrl.dtsi
index ec33116..a149f14 100644
--- a/dts/src/arm/exynos3250-pinctrl.dtsi
+++ b/dts/src/arm/exynos3250-pinctrl.dtsi
@@ -362,8 +362,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -373,8 +379,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts
index 3967ee5..548413e 100644
--- a/dts/src/arm/exynos3250-rinato.dts
+++ b/dts/src/arm/exynos3250-rinato.dts
@@ -649,7 +649,7 @@
card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
- clock-freq-min-max = <400000 100000000>;
+ max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi
index e9d2556..ba17ee1 100644
--- a/dts/src/arm/exynos3250.dtsi
+++ b/dts/src/arm/exynos3250.dtsi
@@ -20,6 +20,8 @@
#include "exynos4-cpu-thermal.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos3250.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos3250";
@@ -211,7 +213,8 @@
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
@@ -219,7 +222,7 @@
tmu: tmu@100C0000 {
compatible = "samsung,exynos3250-tmu";
reg = <0x100C0000 0x100>;
- interrupts = <0 216 0>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -234,14 +237,21 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
@@ -249,24 +259,24 @@
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
- interrupts = <0 48 0>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
};
jpeg: codec@11830000 {
compatible = "samsung,exynos3250-jpeg";
reg = <0x11830000 0x1000>;
- interrupts = <0 171 0>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
clock-names = "jpeg", "sclk";
power-domains = <&pd_cam>;
@@ -280,7 +290,8 @@
sysmmu_jpeg: sysmmu@11A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <0 156 0>, <0 161 0>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -291,7 +302,9 @@
compatible = "samsung,exynos3250-fimd";
reg = <0x11c00000 0x30000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
@@ -303,7 +316,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos3250-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -318,7 +331,8 @@
sysmmu_fimd0: sysmmu@11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -328,7 +342,7 @@
hsotg: hsotg@12480000 {
compatible = "snps,dwc2";
reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -339,7 +353,7 @@
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -351,7 +365,7 @@
mshc_1: mshc@12520000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -363,7 +377,7 @@
mshc_2: mshc@12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -391,7 +405,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -402,7 +416,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -415,7 +429,7 @@
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>;
- interrupts = <0 137 0>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
@@ -427,7 +441,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
- interrupts = <0 102 0>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc", "sclk_mfc";
clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
power-domains = <&pd_mfc>;
@@ -437,7 +451,8 @@
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <0 96 0>, <0 98 0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
@@ -447,7 +462,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -458,7 +473,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -469,7 +484,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -482,7 +497,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -495,7 +510,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -508,7 +523,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -521,7 +536,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -534,7 +549,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -547,7 +562,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -560,7 +575,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -573,7 +588,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +599,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -600,7 +615,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -616,7 +631,7 @@
i2s2: i2s@13970000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13970000 0x100>;
- interrupts = <0 126 0>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0";
dmas = <&pdma0 14>, <&pdma0 13>;
@@ -629,15 +644,19 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a7-pmu";
- interrupts = <0 18 0>, <0 19 0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
ppmu_dmc0: ppmu_dmc0@106a0000 {
diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi
index 5f034eb..c64737b 100644
--- a/dts/src/arm/exynos4.dtsi
+++ b/dts/src/arm/exynos4.dtsi
@@ -21,6 +21,8 @@
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -78,6 +80,11 @@
reg = <0x10000000 0x100>;
};
+ scu: snoop-control-unit@10500000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x10500000 0x2000>;
+ };
+
memory-controller@12570000 {
compatible = "samsung,exynos4210-srom";
reg = <0x12570000 0x14>;
@@ -168,7 +175,7 @@
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 79 0>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
@@ -191,7 +198,7 @@
fimc_0: fimc@11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
- interrupts = <0 84 0>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -203,7 +210,7 @@
fimc_1: fimc@11810000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11810000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -215,7 +222,7 @@
fimc_2: fimc@11820000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11820000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -227,7 +234,7 @@
fimc_3: fimc@11830000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11830000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -239,7 +246,7 @@
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x4000>;
- interrupts = <0 78 0>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
clock-names = "csis", "sclk_csis";
bus-width = <4>;
@@ -254,7 +261,7 @@
csis_1: csis@11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
- interrupts = <0 80 0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
bus-width = <2>;
@@ -270,7 +277,7 @@
watchdog: watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
- interrupts = <0 43 0>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
status = "disabled";
@@ -280,7 +287,8 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupt-parent = <&pmu_system_controller>;
- interrupts = <0 44 0>, <0 45 0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
status = "disabled";
@@ -289,7 +297,7 @@
keypad: keypad@100A0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
@@ -298,7 +306,7 @@
sdhci_0: sdhci@12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
- interrupts = <0 73 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -307,7 +315,7 @@
sdhci_1: sdhci@12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
- interrupts = <0 74 0>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -316,7 +324,7 @@
sdhci_2: sdhci@12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
- interrupts = <0 75 0>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -325,7 +333,7 @@
sdhci_3: sdhci@12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
- interrupts = <0 76 0>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -344,7 +352,7 @@
hsotg: hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
- interrupts = <0 71 0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -355,7 +363,7 @@
ehci: ehci@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -381,7 +389,7 @@
ohci: ohci@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -423,7 +431,7 @@
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
@@ -434,7 +442,7 @@
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
@@ -445,7 +453,7 @@
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
@@ -456,7 +464,7 @@
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
@@ -467,7 +475,7 @@
serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
- interrupts = <0 55 0>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>, <&pdma1 18>;
@@ -480,7 +488,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -493,7 +501,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -506,7 +514,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -519,7 +527,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -532,7 +540,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -545,7 +553,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -558,7 +566,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 64 0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -571,7 +579,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +592,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x138E0000 0x100>;
- interrupts = <0 93 0>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
@@ -598,7 +606,7 @@
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -613,7 +621,7 @@
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -628,7 +636,7 @@
spi_2: spi@13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -643,7 +651,11 @@
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
@@ -660,7 +672,7 @@
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -671,7 +683,7 @@
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 36 0>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -682,7 +694,7 @@
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -712,7 +724,7 @@
jpeg_codec: jpeg-codec@11840000 {
compatible = "samsung,exynos4210-jpeg";
reg = <0x11840000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_JPEG>;
clock-names = "jpeg";
power-domains = <&pd_cam>;
@@ -722,7 +734,7 @@
rotator: rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x64>;
- interrupts = <0 83 0>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -731,7 +743,7 @@
hdmi: hdmi@12D00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
- interrupts = <0 92 0>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
"mout_hdmi";
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -746,7 +758,7 @@
hdmicec: cec@100B0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
- interrupts = <0 114 0>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -757,7 +769,7 @@
mixer: mixer@12C10000 {
compatible = "samsung,exynos4210-mixer";
- interrupts = <0 91 0>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
@@ -984,7 +996,7 @@
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
diff --git a/dts/src/arm/exynos4210-pinctrl.dtsi b/dts/src/arm/exynos4210-pinctrl.dtsi
index d9b6d25..f280954 100644
--- a/dts/src/arm/exynos4210-pinctrl.dtsi
+++ b/dts/src/arm/exynos4210-pinctrl.dtsi
@@ -537,8 +537,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -548,8 +554,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/dts/src/arm/exynos4210.dtsi b/dts/src/arm/exynos4210.dtsi
index 2d9b029..7f3a18c 100644
--- a/dts/src/arm/exynos4210.dtsi
+++ b/dts/src/arm/exynos4210.dtsi
@@ -109,12 +109,12 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
- <1 &gic 0 69 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 0 42 0>,
- <5 &gic 0 48 0>;
+ <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -127,18 +127,18 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -182,7 +182,7 @@
g2d: g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
power-domains = <&pd_lcd0>;
@@ -424,10 +424,22 @@
&combiner {
samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
&mdma1 {
diff --git a/dts/src/arm/exynos4412-itop-elite.dts b/dts/src/arm/exynos4412-itop-elite.dts
new file mode 100644
index 0000000..76d87f3
--- /dev/null
+++ b/dts/src/arm/exynos4412-itop-elite.dts
@@ -0,0 +1,240 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 core board
+ * which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/samsung-i2s.h>
+#include "exynos4412-itop-scp-core.dtsi"
+
+/ {
+ model = "TOPEET iTop 4412 Elite board based on Exynos4412";
+ compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "red:system";
+ gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led3 {
+ label = "red:user";
+ gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ home {
+ label = "GPIO Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
+ };
+
+ back {
+ label = "GPIO Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ sleep {
+ label = "GPIO Key Sleep";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-up {
+ label = "GPIO Key Vol+";
+ linux,code = <KEY_UP>;
+ gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-down {
+ label = "GPIO Key Vol-";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm-sound";
+
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-rates = <0>,
+ <0>,
+ <112896000>,
+ <11289600>;
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "RINPUT2", "Mic Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+
+ beep {
+ compatible = "pwm-beeper";
+ pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
+ };
+
+ camera: camera {
+ pinctrl-0 = <&cam_port_a_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&ehci {
+ status = "okay";
+ /* In order to reset USB ethernet */
+ samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+
+ port@0 {
+ status = "okay";
+ };
+
+ port@2 {
+ status = "okay";
+ };
+};
+
+&exynos_usbphy {
+ status = "okay";
+};
+
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&hsotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&i2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ codec: wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "MCLK1";
+ wlf,shared-lrclk;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+};
+
+&pinctrl_1 {
+ ether-reset {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pwm {
+ status = "okay";
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <0>;
+};
+
+&sdhci_2 {
+ bus-width = <4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+ pinctrl-names = "default";
+ cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>;
+ cap-sd-highspeed;
+ vmmc-supply = <&ldo23_reg>;
+ vqmmc-supply = <&ldo17_reg>;
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/exynos4412-itop-scp-core.dtsi b/dts/src/arm/exynos4412-itop-scp-core.dtsi
new file mode 100644
index 0000000..a36cd36
--- /dev/null
+++ b/dts/src/arm/exynos4412-itop-scp-core.dtsi
@@ -0,0 +1,501 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 SCP package core
+ * board which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include "exynos-mfc-reserved-memory.dtsi"
+
+/ {
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ firmware@0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>;
+ };
+ };
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503a";
+ reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
+ intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsic_reset>;
+ };
+};
+
+&bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&bus_acp {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_c2c {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+};
+
+&bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&hsotg {
+ vusb_d-supply = <&ldo15_reg>;
+ vusb_a-supply = <&ldo12_reg>;
+};
+
+&i2c_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c1_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ s5m8767: s5m8767-pmic@66 {
+ compatible = "samsung,s5m8767-pmic";
+ reg = <0x66>;
+
+ s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+ s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
+ <&gpb 6 GPIO_ACTIVE_HIGH>,
+ <&gpb 7 GPIO_ACTIVE_HIGH>;
+
+ s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
+ <&gpm3 6 GPIO_ACTIVE_HIGH>,
+ <&gpm3 7 GPIO_ACTIVE_HIGH>;
+
+ /* VDD_ARM */
+ s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
+ <1243750>, <1118750>,
+ <1068750>, <1012500>,
+ <956250>, <900000>;
+ /* VDD_INT */
+ s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
+ <925000>, <925000>,
+ <887500>, <887500>,
+ <850000>, <850000>;
+ /* VDD_G3D */
+ s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
+ <1025000>, <950000>,
+ <918750>, <900000>,
+ <875000>, <831250>;
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* SCP uses 1.5v, POP uses 1.2v */
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_M12";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDDIOAP_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_PRE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD_LDO5";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD10_MPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD10_XPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD10_MIPI";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD33_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD18_MIPI";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD18_ABB1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD33_UOTG";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDDIOPERI_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD18_ABB02";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD10_USH";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD18_HSIC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDIOAP_MMC012_28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* Used by HSIC */
+ ldo18_reg: LDO18 {
+ regulator-name = "VDDIOPERI_28";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDD_LDO19";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDD28_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VDD28_AF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDA28_2M";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "VDD28_TF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VDD33_A31";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VDD18_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "VDD18_A31";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "GPS_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "DVDD12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1456250>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_m12";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd12_5m";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "pvdd_buck7";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "pvdd_buck8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vddf28_emmc";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+ };
+
+ s5m8767_osc: clocks {
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap",
+ "s5m8767_cp", "s5m8767_bt";
+ };
+
+ };
+};
+
+&mfc {
+ status = "okay";
+};
+
+&mshc_0 {
+ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc-supply = <&buck9_reg>;
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&pinctrl_1 {
+ hsic_reset: hsic-reset {
+ samsung,pins = "gpm2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&tmu {
+ vtmu-supply = <&ldo16_reg>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/dts/src/arm/exynos4412-odroidx.dts b/dts/src/arm/exynos4412-odroidx.dts
index 61906b3..153a75f 100644
--- a/dts/src/arm/exynos4412-odroidx.dts
+++ b/dts/src/arm/exynos4412-odroidx.dts
@@ -64,6 +64,11 @@
};
};
+&adc {
+ vdd-supply = <&ldo10_reg>;
+ status = "okay";
+};
+
/* VDDQ for MSHC (eMMC card) */
&buck8_reg {
regulator-name = "BUCK8_VDDQ_MMC4_2.8V";
diff --git a/dts/src/arm/exynos4415-pinctrl.dtsi b/dts/src/arm/exynos4415-pinctrl.dtsi
deleted file mode 100644
index 76cfd87..0000000
--- a/dts/src/arm/exynos4415-pinctrl.dtsi
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
- * tree nodes are listed in this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <dt-bindings/pinctrl/samsung.h>
-
-&pinctrl_0 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc0: gpc0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd0: gpd0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd1: gpd1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart0_data: uart0-data {
- samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart0_fctl: uart0-fctl {
- samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_data: uart1-data {
- samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_fctl: uart1-fctl {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_data: uart2-data {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_fctl: uart2-fctl {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c2_bus: i2c2-bus {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c3_bus: i2c3-bus {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi0_bus: spi0-bus {
- samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c4_bus: i2c4-bus {
- samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi1_bus: spi1-bus {
- samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c5_bus: i2c5-bus {
- samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s1_bus: i2s1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s2_bus: i2s2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm2_bus: pcm2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c6_bus: i2c6-bus {
- samsung,pins = "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi2_bus: spi2-bus {
- samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm0_out: pwm0-out {
- samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm1_out: pwm1-out {
- samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm2_out: pwm2-out {
- samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm3_out: pwm3-out {
- samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c7_bus: i2c7-bus {
- samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c0_bus: i2c0-bus {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c1_bus: i2c1-bus {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_1 {
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm0: gpm0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm1: gpm1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm2: gpm2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm3: gpm3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm4: gpm4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx0: gpx0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
- #interrupt-cells = <2>;
- };
-
- gpx1: gpx1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
- #interrupt-cells = <2>;
- };
-
- gpx2: gpx2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx3: gpx3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk: sd0-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cmd: sd0-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cd: sd0-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_rdqs: sd0-rdqs {
- samsung,pins = "gpk0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus1: sd0-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus4: sd0-bus-width4 {
- samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus8: sd0-bus-width8 {
- samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_clk: sd1-clk {
- samsung,pins = "gpk1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cmd: sd1-cmd {
- samsung,pins = "gpk1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cd: sd1-cd {
- samsung,pins = "gpk1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus1: sd1-bus-width1 {
- samsung,pins = "gpk1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus4: sd1-bus-width4 {
- samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_clk: sd2-clk {
- samsung,pins = "gpk2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cmd: sd2-cmd {
- samsung,pins = "gpk2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cd: sd2-cd {
- samsung,pins = "gpk2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus1: sd2-bus-width1 {
- samsung,pins = "gpk2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus4: sd2-bus-width4 {
- samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_io: cam-port-b-io {
- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_b_clk_active: cam-port-b-clk-active {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_clk_idle: cam-port-b-clk-idle {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c0: fimc-is-i2c0 {
- samsung,pins = "gpm4-0", "gpm4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c1: fimc-is-i2c1 {
- samsung,pins = "gpm4-2", "gpm4-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_uart: fimc-is-uart {
- samsung,pins = "gpm3-5", "gpm3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_2 {
- gpz: gpz {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- i2s0_bus: i2s0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4", "gpz-5", "gpz-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-};
diff --git a/dts/src/arm/exynos4415.dtsi b/dts/src/arm/exynos4415.dtsi
deleted file mode 100644
index 3c40f8a..0000000
--- a/dts/src/arm/exynos4415.dtsi
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * Samsung's Exynos4415 SoC device tree source
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- *
- * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
- * based board files can include this file and provide values for board
- * specific bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
- * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
- * nodes can be added to this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/clock/exynos4415.h>
-#include <dt-bindings/clock/exynos-audss-clk.h>
-
-/ {
- compatible = "samsung,exynos4415";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- pinctrl0 = &pinctrl_0;
- pinctrl1 = &pinctrl_1;
- pinctrl2 = &pinctrl_2;
- mshc0 = &mshc_0;
- mshc1 = &mshc_1;
- mshc2 = &mshc_2;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- i2c0 = &i2c_0;
- i2c1 = &i2c_1;
- i2c2 = &i2c_2;
- i2c3 = &i2c_3;
- i2c4 = &i2c_4;
- i2c5 = &i2c_5;
- i2c6 = &i2c_6;
- i2c7 = &i2c_7;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@a00 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa00>;
- clock-frequency = <1600000000>;
- };
-
- cpu1: cpu@a01 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa01>;
- clock-frequency = <1600000000>;
- };
-
- cpu2: cpu@a02 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa02>;
- clock-frequency = <1600000000>;
- };
-
- cpu3: cpu@a03 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xa03>;
- clock-frequency = <1600000000>;
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sysram@02020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x50000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x50000>;
-
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
-
- smp-sysram@4f000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x4f000 0x1000>;
- };
- };
-
- pinctrl_2: pinctrl@03860000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x03860000 0x1000>;
- interrupts = <0 242 0>;
- };
-
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
-
- sysreg_system_controller: syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
-
- pmu_system_controller: system-controller@10020000 {
- compatible = "samsung,exynos4415-pmu", "syscon";
- reg = <0x10020000 0x4000>;
- };
-
- mipi_phy: video-phy@10020710 {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
-
- pd_cam: cam-power-domain@10024000 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024000 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_tv: tv-power-domain@10024020 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024020 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_mfc: mfc-power-domain@10024040 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024040 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_g3d: g3d-power-domain@10024060 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024060 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_lcd0: lcd0-power-domain@10024080 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10024080 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp0: isp0-power-domain@100240A0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240A0 0x20>;
- #power-domain-cells = <0>;
- };
-
- pd_isp1: isp1-power-domain@100240E0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100240E0 0x20>;
- #power-domain-cells = <0>;
- };
-
- cmu: clock-controller@10030000 {
- compatible = "samsung,exynos4415-cmu";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- rtc: rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
- status = "disabled";
- };
-
- mct@10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
- clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
- clock-names = "fin_pll", "mct";
- };
-
- gic: interrupt-controller@10481000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- l2c: l2-cache-controller@10502000 {
- compatible = "arm,pl310-cache";
- reg = <0x10502000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <2 2 1>;
- arm,data-latency = <3 2 1>;
- arm,double-linefill = <1>;
- arm,double-linefill-incr = <0>;
- arm,double-linefill-wrap = <1>;
- arm,prefetch-drop = <1>;
- arm,prefetch-offset = <7>;
- };
-
- cmu_dmc: clock-controller@105C0000 {
- compatible = "samsung,exynos4415-cmu-dmc";
- reg = <0x105C0000 0x3000>;
- #clock-cells = <1>;
- };
-
- pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos4210-wakeup-eint";
- interrupt-parent = <&gic>;
- interrupts = <0 48 0>;
- };
- };
-
- pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,exynos4415-pinctrl";
- reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
- };
-
- fimd: fimd@11C00000 {
- compatible = "samsung,exynos4415-fimd";
- reg = <0x11C00000 0x30000>;
- interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
- clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
- clock-names = "sclk_fimd", "fimd";
- samsung,power-domain = <&pd_lcd0>;
- iommus = <&sysmmu_fimd0>;
- samsung,sysreg = <&sysreg_system_controller>;
- status = "disabled";
- };
-
- dsi_0: dsi@11C80000 {
- compatible = "samsung,exynos4415-mipi-dsi";
- reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
- samsung,phy-type = <0>;
- samsung,power-domain = <&pd_lcd0>;
- phys = <&mipi_phy 1>;
- phy-names = "dsim";
- clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "pll_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sysmmu_fimd0: sysmmu@11E20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
- clock-names = "sysmmu", "master";
- clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
- power-domains = <&pd_lcd0>;
- #iommu-cells = <0>;
- };
-
- hsotg: hsotg@12480000 {
- compatible = "samsung,s3c6400-hsotg";
- reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
- clocks = <&cmu CLK_USBDEVICE>;
- clock-names = "otg";
- phys = <&exynos_usbphy 0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- mshc_0: mshc@12510000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
- clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_1: mshc@12520000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
- clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mshc_2: mshc@12530000 {
- compatible = "samsung,exynos5250-dw-mshc";
- reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
- clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ehci: ehci@12580000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12580000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- port@1 {
- reg = <1>;
- phys = <&exynos_usbphy 2>;
- status = "disabled";
- };
- port@2 {
- reg = <2>;
- phys = <&exynos_usbphy 3>;
- status = "disabled";
- };
- };
-
- ohci: ohci@12590000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12590000 0x100>;
- interrupts = <0 140 0>;
- clocks = <&cmu CLK_USBHOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
- status = "disabled";
- };
- };
-
- exynos_usbphy: exynos-usbphy@125B0000 {
- compatible = "samsung,exynos4x12-usb2-phy";
- reg = <0x125B0000 0x100>;
- samsung,pmureg-phandle = <&pmu_system_controller>;
- samsung,sysreg-phandle = <&sysreg_system_controller>;
- clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- status = "disabled";
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
- ranges;
-
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
- clocks = <&cmu CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
- clocks = <&cmu CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
- };
-
- adc: adc@126C0000 {
- compatible = "samsung,exynos3250-adc",
- "samsung,exynos-adc-v2";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
- interrupts = <0 137 0>;
- clock-names = "adc", "sclk";
- clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- status = "disabled";
- };
-
- serial_0: serial@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
- clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_1: serial@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
- clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_2: serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
- clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- serial_3: serial@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <0 112 0>;
- clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- i2c_0: i2c@13860000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
- clocks = <&cmu CLK_I2C0>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_bus>;
- status = "disabled";
- };
-
- i2c_1: i2c@13870000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
- clocks = <&cmu CLK_I2C1>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_bus>;
- status = "disabled";
- };
-
- i2c_2: i2c@13880000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
- clocks = <&cmu CLK_I2C2>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_bus>;
- status = "disabled";
- };
-
- i2c_3: i2c@13890000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
- clocks = <&cmu CLK_I2C3>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_bus>;
- status = "disabled";
- };
-
- i2c_4: i2c@138A0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
- clocks = <&cmu CLK_I2C4>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_bus>;
- status = "disabled";
- };
-
- i2c_5: i2c@138B0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
- clocks = <&cmu CLK_I2C5>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_bus>;
- status = "disabled";
- };
-
- i2c_6: i2c@138C0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
- clocks = <&cmu CLK_I2C6>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_bus>;
- status = "disabled";
- };
-
- i2c_7: i2c@138D0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
- clocks = <&cmu CLK_I2C7>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7_bus>;
- status = "disabled";
- };
-
- spi_0: spi@13920000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
- dmas = <&pdma0 7>, <&pdma0 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- status = "disabled";
- };
-
- spi_1: spi@13930000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
- dmas = <&pdma1 7>, <&pdma1 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- status = "disabled";
- };
-
- spi_2: spi@13940000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13940000 0x100>;
- interrupts = <0 123 0>;
- dmas = <&pdma0 9>, <&pdma0 8>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
- clock-names = "spi", "spi_busclk0";
- samsung,spi-src-clk = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_bus>;
- status = "disabled";
- };
-
- clock_audss: clock-controller@03810000 {
- compatible = "samsung,exynos4210-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
- };
-
- i2s0: i2s@3830000 {
- compatible = "samsung,s5pv210-i2s";
- reg = <0x03830000 0x100>;
- interrupts = <0 124 0>;
- clocks = <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_SCLK_I2S>;
- clock-names = "iis", "i2s_opclk0";
- dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
- dma-names = "tx", "rx", "tx-sec";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_bus>;
- samsung,idma-addr = <0x03000000>;
- status = "disabled";
- };
-
- pwm: pwm@139D0000 {
- compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
- };
- };
-};
-
-#include "exynos4415-pinctrl.dtsi"
diff --git a/dts/src/arm/exynos4x12-pinctrl.dtsi b/dts/src/arm/exynos4x12-pinctrl.dtsi
index a56bf9b..2f866f6 100644
--- a/dts/src/arm/exynos4x12-pinctrl.dtsi
+++ b/dts/src/arm/exynos4x12-pinctrl.dtsi
@@ -572,8 +572,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -583,8 +589,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/dts/src/arm/exynos4x12.dtsi b/dts/src/arm/exynos4x12.dtsi
index 3394bdc..85a7122 100644
--- a/dts/src/arm/exynos4x12.dtsi
+++ b/dts/src/arm/exynos4x12.dtsi
@@ -88,11 +88,11 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &combiner 12 5>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 1 12 0>;
+ <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -112,7 +112,7 @@
g2d: g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -127,7 +127,7 @@
fimc_lite_0: fimc-lite@12390000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x12390000 0x1000>;
- interrupts = <0 105 0>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
@@ -138,7 +138,7 @@
fimc_lite_1: fimc-lite@123A0000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x123A0000 0x1000>;
- interrupts = <0 106 0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
@@ -147,9 +147,10 @@
};
fimc_is: fimc-is@12000000 {
- compatible = "samsung,exynos4212-fimc-is", "simple-bus";
+ compatible = "samsung,exynos4212-fimc-is";
reg = <0x12000000 0x260000>;
- interrupts = <0 90 0>, <0 95 0>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>,
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
@@ -200,7 +201,7 @@
mshc_0: mmc@12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <0x80>;
@@ -461,11 +462,26 @@
};
&combiner {
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
&exynos_usbphy {
@@ -529,18 +545,18 @@
&pinctrl_0 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
&pinctrl_1 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -554,7 +570,7 @@
&pinctrl_3 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
- interrupts = <0 72 0>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
&pmu_system_controller {
diff --git a/dts/src/arm/exynos5.dtsi b/dts/src/arm/exynos5.dtsi
index 8f06609..7fd870e 100644
--- a/dts/src/arm/exynos5.dtsi
+++ b/dts/src/arm/exynos5.dtsi
@@ -13,6 +13,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -53,14 +55,38 @@
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10481000 {
@@ -71,7 +97,8 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
sysreg_system_controller: syscon@10050000 {
@@ -82,31 +109,31 @@
serial_0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
};
serial_1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
};
serial_2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
};
serial_3: serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
};
i2c_0: i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
- interrupts = <0 56 0>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -116,7 +143,7 @@
i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
- interrupts = <0 57 0>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -126,7 +153,7 @@
i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -136,7 +163,7 @@
i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -153,7 +180,8 @@
rtc: rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
diff --git a/dts/src/arm/exynos5250-snow-common.dtsi b/dts/src/arm/exynos5250-snow-common.dtsi
index d5d5191..8f3a804 100644
--- a/dts/src/arm/exynos5250-snow-common.dtsi
+++ b/dts/src/arm/exynos5250-snow-common.dtsi
@@ -523,6 +523,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -536,6 +537,7 @@
cap-mmc-highspeed;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
@@ -553,6 +555,8 @@
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
+ *
+ * WiFi SDIO module
*/
&mmc_3 {
status = "okay";
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index f7357d9..b6d7444 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -181,8 +181,8 @@
<0x1 0 &combiner 23 4>,
<0x2 0 &combiner 25 2>,
<0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
+ <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -195,31 +195,31 @@
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10040000 {
@@ -236,7 +236,7 @@
watchdog@101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -245,7 +245,7 @@
g2d@10850000 {
compatible = "samsung,exynos5250-g2d";
reg = <0x10850000 0x1000>;
- interrupts = <0 91 0>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_G2D>;
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -254,7 +254,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
@@ -265,7 +265,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -274,7 +274,7 @@
tmu: tmu@10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -284,7 +284,7 @@
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
- interrupts = <0 115 0>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
@@ -306,7 +306,7 @@
i2c_4: i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C4>;
@@ -319,7 +319,7 @@
i2c_5: i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C5>;
@@ -332,7 +332,7 @@
i2c_6: i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C6>;
@@ -345,7 +345,7 @@
i2c_7: i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C7>;
@@ -358,7 +358,7 @@
i2c_8: i2c@12CE0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
- interrupts = <0 64 0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C_HDMI>;
@@ -380,7 +380,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d20000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -396,7 +396,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d30000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -412,7 +412,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d40000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -426,7 +426,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 75 0>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x1000>;
@@ -438,7 +438,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 76 0>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x1000>;
@@ -450,7 +450,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -463,7 +463,7 @@
mmc_3: mmc@12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
@@ -526,7 +526,7 @@
usbdrd_dwc3: dwc3@12000000 {
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -544,7 +544,7 @@
ehci: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -559,7 +559,7 @@
ohci: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -591,7 +591,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -602,7 +602,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -613,7 +613,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -624,7 +624,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -636,7 +636,7 @@
gsc_0: gsc@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
@@ -646,7 +646,7 @@
gsc_1: gsc@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
@@ -656,7 +656,7 @@
gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL2>;
clock-names = "gscl";
@@ -666,7 +666,7 @@
gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL3>;
clock-names = "gscl";
@@ -677,7 +677,7 @@
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
power-domains = <&pd_disp1>;
- interrupts = <0 95 0>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -690,7 +690,7 @@
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
power-domains = <&pd_disp1>;
- interrupts = <0 94 0>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -706,7 +706,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -718,7 +718,7 @@
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
diff --git a/dts/src/arm/exynos5260.dtsi b/dts/src/arm/exynos5260.dtsi
index a86a489..5818718 100644
--- a/dts/src/arm/exynos5260.dtsi
+++ b/dts/src/arm/exynos5260.dtsi
@@ -10,6 +10,8 @@
*/
#include <dt-bindings/clock/exynos5260-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5260", "samsung,exynos5";
@@ -168,7 +170,8 @@
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
chipid: chipid@10000000 {
@@ -181,10 +184,18 @@
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 122 0>, <0 123 0>,
- <0 124 0>, <0 125 0>, <0 126 0>,
- <0 127 0>, <0 128 0>, <0 129 0>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
};
cci: cci@10F00000 {
@@ -210,25 +221,25 @@
pinctrl_0: pinctrl@11600000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x11600000 0x1000>;
- interrupts = <0 79 0>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@12290000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x12290000 0x1000>;
- interrupts = <0 157 0>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@128B0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
- interrupts = <0 243 0>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10D50000 {
@@ -239,7 +250,7 @@
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 146 0>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -248,7 +259,7 @@
uart1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 147 0>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -257,7 +268,7 @@
uart2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 148 0>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -266,7 +277,7 @@
uart3: serial@12860000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12860000 0x100>;
- interrupts = <0 145 0>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -275,7 +286,7 @@
mmc_0: mmc@12140000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12140000 0x2000>;
- interrupts = <0 156 0>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
@@ -287,7 +298,7 @@
mmc_1: mmc@12150000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12150000 0x2000>;
- interrupts = <0 158 0>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
@@ -299,7 +310,7 @@
mmc_2: mmc@12160000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12160000 0x2000>;
- interrupts = <0 159 0>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
diff --git a/dts/src/arm/exynos5410-odroidxu.dts b/dts/src/arm/exynos5410-odroidxu.dts
index 3c271cb..c4de135 100644
--- a/dts/src/arm/exynos5410-odroidxu.dts
+++ b/dts/src/arm/exynos5410-odroidxu.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos54xx-odroidxu-leds.dtsi"
/ {
@@ -57,6 +58,61 @@
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
+
+ sound: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,name = "Odroid-XU";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Speakers", "Speakers";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Headphone Jack", "MICBIAS",
+ "IN1", "Headphone Jack",
+ "Speakers", "SPKL",
+ "Speakers", "SPKR";
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&audi2s0 0>;
+ system-clock-frequency = <19200000>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&max98090>;
+ clocks = <&audi2s0 CLK_I2S_CDCLK>;
+ };
+ };
+};
+
+&audi2s0 {
+ status = "okay";
+};
+
+&clock {
+ clocks = <&fin_pll>;
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <192000000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+
+ assigned-clock-rates = <0>,
+ <0>,
+ <96000000>,
+ <19200000>;
};
&cpu0_thermal {
@@ -440,6 +496,19 @@
};
};
+&i2c_1 {
+ status = "okay";
+ max98090: max98090@10 {
+ compatible = "maxim,max98090";
+ reg = <0x10>;
+ interrupt-parent = <&gpj3>;
+ interrupts = <0 IRQ_TYPE_NONE>;
+ clocks = <&audi2s0 CLK_I2S_CDCLK>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ };
+};
+
&mmc_0 {
status = "okay";
mmc-pwrseq = <&emmc_pwrseq>;
diff --git a/dts/src/arm/exynos5410-pinctrl.dtsi b/dts/src/arm/exynos5410-pinctrl.dtsi
index a083d23..ff46a1c 100644
--- a/dts/src/arm/exynos5410-pinctrl.dtsi
+++ b/dts/src/arm/exynos5410-pinctrl.dtsi
@@ -615,4 +615,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ audi2s0_bus: audi2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
};
diff --git a/dts/src/arm/exynos5410.dtsi b/dts/src/arm/exynos5410.dtsi
index 137f484..2b6adaf 100644
--- a/dts/src/arm/exynos5410.dtsi
+++ b/dts/src/arm/exynos5410.dtsi
@@ -16,6 +16,7 @@
#include "exynos54xx.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -82,10 +83,18 @@
#clock-cells = <1>;
};
+ clock_audss: audss-clock-controller@3810000 {
+ compatible = "samsung,exynos5410-audss-clock";
+ reg = <0x03810000 0x0C>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
+ clock-names = "pll_ref", "pll_in";
+ };
+
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 65 0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -94,7 +103,7 @@
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <GIC_SPI 183 0>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -103,7 +112,7 @@
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10068000 0x100>;
- interrupts = <GIC_SPI 184 0>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -112,7 +121,7 @@
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x1006c000 0x100>;
- interrupts = <GIC_SPI 185 0>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -121,7 +130,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
@@ -133,7 +142,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
@@ -145,7 +154,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
@@ -157,31 +166,81 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@14000000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121A0000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121B0000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
+ audi2s0: i2s@03830000 {
+ compatible = "samsung,exynos5420-i2s";
+ reg = <0x03830000 0x100>;
+ dmas = <&pdma0 10
+ &pdma0 9
+ &pdma0 8>;
+ dma-names = "tx", "rx", "tx-sec";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
+ clock-output-names = "i2s_cdclk0";
+ #sound-dai-cells = <1>;
+ samsung,idma-addr = <0x03000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&audi2s0_bus>;
+ status = "disabled";
};
};
@@ -329,7 +388,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 200 0>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index ec4a00f..1f964ec 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -697,6 +697,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -714,6 +715,7 @@
bus-width = <8>;
};
+/* WiFi SDIO module */
&mmc_1 {
status = "okay";
num-slots = <1>;
@@ -733,6 +735,7 @@
vqmmc-supply = <&buck10_reg>;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 00c4cfa..906a1a4 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -193,7 +193,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
@@ -203,7 +203,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
@@ -215,7 +215,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
@@ -227,7 +227,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5420-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -320,37 +320,37 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@14000000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@14010000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_4: pinctrl@03860000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
amba {
@@ -363,7 +363,7 @@
adma: adma@03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -374,7 +374,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -385,7 +385,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -396,7 +396,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -407,7 +407,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -479,7 +479,7 @@
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -495,7 +495,7 @@
spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
- interrupts = <0 69 0>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -511,7 +511,7 @@
spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -539,7 +539,7 @@
dsi@14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
- interrupts = <0 82 0>;
+ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
@@ -552,7 +552,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -564,7 +564,7 @@
hsi2c_8: i2c@12E00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -577,7 +577,7 @@
hsi2c_9: i2c@12E10000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -590,7 +590,7 @@
hsi2c_10: i2c@12E20000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
- interrupts = <0 203 0>;
+ interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -603,7 +603,7 @@
hdmi: hdmi@14530000 {
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -622,7 +622,7 @@
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -633,7 +633,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -642,7 +642,7 @@
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -652,7 +652,7 @@
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -662,7 +662,7 @@
jpeg_0: jpeg@11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
@@ -671,7 +671,7 @@
jpeg_1: jpeg@11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
- interrupts = <0 168 0>;
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
@@ -691,7 +691,7 @@
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -700,7 +700,7 @@
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <0 183 0>;
+ interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -709,7 +709,7 @@
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
- interrupts = <0 184 0>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -718,7 +718,7 @@
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
- interrupts = <0 185 0>;
+ interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -727,7 +727,7 @@
tmu_gpu: tmu@100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
- interrupts = <0 215 0>;
+ interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -799,7 +799,7 @@
sysmmu_scaler1r: sysmmu@0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
- interrupts = <0 186 0>;
+ interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
@@ -808,7 +808,7 @@
sysmmu_scaler2r: sysmmu@0x128A0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
- interrupts = <0 188 0>;
+ interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
@@ -867,7 +867,7 @@
sysmmu_jpeg1: sysmmu@0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
- interrupts = <0 169 0>;
+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
@@ -1445,7 +1445,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 73 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
index 246d298..05b9afd 100644
--- a/dts/src/arm/exynos5422-odroidxu3-common.dtsi
+++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
@@ -147,6 +147,11 @@
};
};
+&adc {
+ vdd-supply = <&ldo4_reg>;
+ status = "okay";
+};
+
&bus_wcore {
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
@@ -293,6 +298,12 @@
regulator-max-microvolt = <1800000>;
};
+ ldo4_reg: LDO4 {
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
ldo5_reg: LDO5 {
regulator-name = "vdd_ldo5";
regulator-min-microvolt = <1800000>;
@@ -499,7 +510,6 @@
&mmc_0 {
status = "okay";
mmc-pwrseq = <&emmc_pwrseq>;
- cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
diff --git a/dts/src/arm/exynos5440.dtsi b/dts/src/arm/exynos5440.dtsi
index e6bffd1..2a2e570 100644
--- a/dts/src/arm/exynos5440.dtsi
+++ b/dts/src/arm/exynos5440.dtsi
@@ -10,6 +10,8 @@
*/
#include <dt-bindings/clock/exynos5440.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5440", "samsung,exynos5";
@@ -41,7 +43,8 @@
<0x2E2000 0x1000>,
<0x2E4000 0x2000>,
<0x2E6000 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
cpus {
@@ -72,26 +75,26 @@
arm-pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
- interrupts = <0 52 4>,
- <0 53 4>,
- <0 54 4>,
- <0 55 4>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <50000000>;
};
cpufreq@160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
- interrupts = <0 57 0>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
operating-points = <
/* KHz uV */
1500000 1100000
@@ -108,7 +111,7 @@
serial_0: serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
- interrupts = <0 2 0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -116,7 +119,7 @@
serial_1: serial@C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
- interrupts = <0 3 0>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -124,7 +127,7 @@
spi_0: spi@D0000 {
compatible = "samsung,exynos5440-spi";
reg = <0xD0000 0x100>;
- interrupts = <0 4 0>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,spi-src-clk = <0>;
@@ -136,8 +139,14 @@
pin_ctrl: pinctrl@E0000 {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
- <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
@@ -162,7 +171,7 @@
i2c@F0000 {
compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>;
- interrupts = <0 5 0>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -172,7 +181,7 @@
i2c@100000 {
compatible = "samsung,exynos5440-i2c";
reg = <0x100000 0x1000>;
- interrupts = <0 6 0>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -182,16 +191,16 @@
watchdog@110000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
- interrupts = <0 1 0>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "watchdog";
};
gmac: ethernet@00230000 {
- compatible = "snps,dwmac-3.70a";
+ compatible = "snps,dwmac-3.70a", "snps,dwmac";
reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>;
- interrupts = <0 31 4>;
+ interrupts = <GIC_SPI 31 4>;
interrupt-names = "macirq";
phy-mode = "sgmii";
clocks = <&clock CLK_GMAC0>;
@@ -209,7 +218,8 @@
rtc@130000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
- interrupts = <0 17 0>, <0 16 0>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "rtc";
};
@@ -217,7 +227,7 @@
tmuctrl_0: tmuctrl@160118 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -226,7 +236,7 @@
tmuctrl_1: tmuctrl@16011C {
compatible = "samsung,exynos5440-tmu";
reg = <0x16011C 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -235,7 +245,7 @@
tmuctrl_2: tmuctrl@160120 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160120 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -259,7 +269,7 @@
sata@210000 {
compatible = "snps,exynos5440-ahci";
reg = <0x210000 0x10000>;
- interrupts = <0 30 0>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>;
clock-names = "sata";
};
@@ -267,7 +277,7 @@
ohci@220000 {
compatible = "samsung,exynos5440-ohci";
reg = <0x220000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -275,7 +285,7 @@
ehci@221000 {
compatible = "samsung,exynos5440-ehci";
reg = <0x221000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -285,7 +295,9 @@
reg = <0x290000 0x1000
0x270000 0x1000
0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
@@ -306,7 +318,9 @@
reg = <0x2a0000 0x1000
0x272000 0x1000
0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
diff --git a/dts/src/arm/exynos54xx.dtsi b/dts/src/arm/exynos54xx.dtsi
index 9d31cdc..0389e8a 100644
--- a/dts/src/arm/exynos54xx.dtsi
+++ b/dts/src/arm/exynos54xx.dtsi
@@ -62,34 +62,34 @@
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
- <4 &gic 0 120 0>,
- <5 &gic 0 121 0>,
- <6 &gic 0 122 0>,
- <7 &gic 0 123 0>,
- <8 &gic 0 128 0>,
- <9 &gic 0 129 0>,
- <10 &gic 0 130 0>,
- <11 &gic 0 131 0>;
+ <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
+ <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
+ <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
+ <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
+ <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
};
};
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos5420-wdt";
reg = <0x101d0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x1000>;
- interrupts = <0 60 0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -98,7 +98,7 @@
hsi2c_5: i2c@12cb0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cb0000 0x1000>;
- interrupts = <0 61 0>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -107,7 +107,7 @@
hsi2c_6: i2c@12cc0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cc0000 0x1000>;
- interrupts = <0 62 0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -116,7 +116,7 @@
hsi2c_7: i2c@12cd0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cd0000 0x1000>;
- interrupts = <0 63 0>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -131,7 +131,7 @@
usbdrd_dwc3_0: dwc3@12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -166,7 +166,7 @@
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -179,7 +179,7 @@
usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index 01f4668..f9ff7f0 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -665,6 +665,7 @@
status = "okay";
};
+/* eMMC flash */
&mmc_0 {
status = "okay";
num-slots = <1>;
@@ -683,6 +684,7 @@
bus-width = <8>;
};
+/* WiFi SDIO module */
&mmc_1 {
status = "okay";
num-slots = <1>;
@@ -702,6 +704,7 @@
vqmmc-supply = <&buck10_reg>;
};
+/* uSD card */
&mmc_2 {
status = "okay";
num-slots = <1>;
diff --git a/dts/src/arm/hi3620.dtsi b/dts/src/arm/hi3620.dtsi
index c85d07e..541d700 100644
--- a/dts/src/arm/hi3620.dtsi
+++ b/dts/src/arm/hi3620.dtsi
@@ -11,10 +11,12 @@
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/hi3620-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
@@ -537,6 +539,7 @@
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
#gpio-range-cells = <3>;
ranges;
@@ -558,6 +561,7 @@
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <1>;
+ #pinctrl-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
diff --git a/dts/src/arm/hip01.dtsi b/dts/src/arm/hip01.dtsi
index 4e9562f..9d5fd5c 100644
--- a/dts/src/arm/hip01.dtsi
+++ b/dts/src/arm/hip01.dtsi
@@ -11,8 +11,6 @@
* published by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
-
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
diff --git a/dts/src/arm/hisi-x5hd2.dtsi b/dts/src/arm/hisi-x5hd2.dtsi
index fdcc23d..6c712a9 100644
--- a/dts/src/arm/hisi-x5hd2.dtsi
+++ b/dts/src/arm/hisi-x5hd2.dtsi
@@ -7,10 +7,12 @@
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/hix5hd2-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart0;
};
@@ -436,18 +438,20 @@
};
gmac0: ethernet@1840000 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
reg = <0x1840000 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
clocks = <&clock HIX5HD2_MAC0_CLK>;
+ clock-names = "mac_core";
status = "disabled";
};
gmac1: ethernet@1841000 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
clocks = <&clock HIX5HD2_MAC1_CLK>;
+ clock-names = "mac_core";
status = "disabled";
};
diff --git a/dts/src/arm/imx1.dtsi b/dts/src/arm/imx1.dtsi
index 22f5d1d..b792eee 100644
--- a/dts/src/arm/imx1.dtsi
+++ b/dts/src/arm/imx1.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
@@ -17,6 +16,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
diff --git a/dts/src/arm/imx23.dtsi b/dts/src/arm/imx23.dtsi
index 440ee9a..ac2a9da 100644
--- a/dts/src/arm/imx23.dtsi
+++ b/dts/src/arm/imx23.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx23-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
@@ -464,7 +466,7 @@
reg = <0x80038000 0x2000>;
status = "disabled";
};
- };
+ };
apbx@80040000 {
compatible = "simple-bus";
diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi
index af6af87..831d09a 100644
--- a/dts/src/arm/imx25.dtsi
+++ b/dts/src/arm/imx25.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/dts/src/arm/imx27.dtsi b/dts/src/arm/imx27.dtsi
index f818ea4..9d8b596 100644
--- a/dts/src/arm/imx27.dtsi
+++ b/dts/src/arm/imx27.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/clock/imx27-clock.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/dts/src/arm/imx28-m28.dtsi b/dts/src/arm/imx28-m28.dtsi
index 214bb15..a69856e 100644
--- a/dts/src/arm/imx28-m28.dtsi
+++ b/dts/src/arm/imx28-m28.dtsi
@@ -12,8 +12,8 @@
#include "imx28.dtsi"
/ {
- model = "DENX M28";
- compatible = "denx,m28", "fsl,imx28";
+ model = "Aries/DENX M28";
+ compatible = "aries,m28", "denx,m28", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
diff --git a/dts/src/arm/imx28-m28evk.dts b/dts/src/arm/imx28-m28evk.dts
index 8d04e57..dbfb8aa 100644
--- a/dts/src/arm/imx28-m28evk.dts
+++ b/dts/src/arm/imx28-m28evk.dts
@@ -13,8 +13,8 @@
#include "imx28-m28.dtsi"
/ {
- model = "DENX M28EVK";
- compatible = "denx,m28evk", "fsl,imx28";
+ model = "Aries/DENX M28EVK";
+ compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28";
apb@80000000 {
apbh@80000000 {
diff --git a/dts/src/arm/imx28.dtsi b/dts/src/arm/imx28.dtsi
index 0ad893b..3aabf65 100644
--- a/dts/src/arm/imx28.dtsi
+++ b/dts/src/arm/imx28.dtsi
@@ -10,10 +10,12 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
#include "imx28-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
diff --git a/dts/src/arm/imx31.dtsi b/dts/src/arm/imx31.dtsi
index 1ce7ae9..685916e 100644
--- a/dts/src/arm/imx31.dtsi
+++ b/dts/src/arm/imx31.dtsi
@@ -9,9 +9,10 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
@@ -118,13 +119,6 @@
interrupts = <19>;
clocks = <&clks 25>;
};
-
- clks: ccm@53f80000{
- compatible = "fsl,imx31-ccm";
- reg = <0x53f80000 0x4000>;
- interrupts = <0 31 0x04 0 53 0x04>;
- #clock-cells = <1>;
- };
};
aips@53f00000 { /* AIPS2 */
@@ -134,6 +128,13 @@
reg = <0x53f00000 0x100000>;
ranges;
+ clks: ccm@53f80000{
+ compatible = "fsl,imx31-ccm";
+ reg = <0x53f80000 0x4000>;
+ interrupts = <31>, <53>;
+ #clock-cells = <1>;
+ };
+
gpt: timer@53f90000 {
compatible = "fsl,imx31-gpt";
reg = <0x53f90000 0x4000>;
diff --git a/dts/src/arm/imx35.dtsi b/dts/src/arm/imx35.dtsi
index f812d58..9f40e62 100644
--- a/dts/src/arm/imx35.dtsi
+++ b/dts/src/arm/imx35.dtsi
@@ -8,10 +8,12 @@
* Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/dts/src/arm/imx50.dtsi b/dts/src/arm/imx50.dtsi
index 8fe8bee..fe0221e 100644
--- a/dts/src/arm/imx50.dtsi
+++ b/dts/src/arm/imx50.dtsi
@@ -11,11 +11,13 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@@ -103,8 +105,8 @@
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -115,8 +117,8 @@
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -127,7 +129,7 @@
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -139,7 +141,7 @@
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -164,8 +166,8 @@
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -176,8 +178,8 @@
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -279,7 +281,7 @@
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -298,7 +300,7 @@
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -308,7 +310,7 @@
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -318,7 +320,7 @@
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -328,7 +330,7 @@
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -383,7 +385,7 @@
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
- <&clks IMX5_CLK_UART4_PER_GATE>;
+ <&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -401,7 +403,7 @@
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
- <&clks IMX5_CLK_UART5_PER_GATE>;
+ <&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -420,7 +422,7 @@
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -430,7 +432,7 @@
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
};
@@ -442,7 +444,7 @@
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -492,8 +494,8 @@
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
diff --git a/dts/src/arm/imx51.dtsi b/dts/src/arm/imx51.dtsi
index f46fe9b..33526ca 100644
--- a/dts/src/arm/imx51.dtsi
+++ b/dts/src/arm/imx51.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@@ -130,8 +132,8 @@
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
- <&clks IMX5_CLK_IPU_DI0_GATE>,
- <&clks IMX5_CLK_IPU_DI1_GATE>;
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@@ -169,8 +171,8 @@
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@@ -180,8 +182,8 @@
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -192,7 +194,7 @@
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -204,7 +206,7 @@
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -229,8 +231,8 @@
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -241,8 +243,8 @@
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -364,7 +366,7 @@
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -378,7 +380,7 @@
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -388,7 +390,7 @@
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -398,7 +400,7 @@
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -408,7 +410,7 @@
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -456,7 +458,7 @@
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -466,7 +468,7 @@
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@@ -479,7 +481,7 @@
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -582,8 +584,8 @@
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
diff --git a/dts/src/arm/imx53-m53.dtsi b/dts/src/arm/imx53-m53.dtsi
index d259f57..ec390aa 100644
--- a/dts/src/arm/imx53-m53.dtsi
+++ b/dts/src/arm/imx53-m53.dtsi
@@ -12,8 +12,8 @@
#include "imx53.dtsi"
/ {
- model = "DENX M53";
- compatible = "denx,imx53-m53", "fsl,imx53";
+ model = "Aries/DENX M53";
+ compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,
diff --git a/dts/src/arm/imx53-m53evk.dts b/dts/src/arm/imx53-m53evk.dts
index dcee1e0..4347a32 100644
--- a/dts/src/arm/imx53-m53evk.dts
+++ b/dts/src/arm/imx53-m53evk.dts
@@ -13,8 +13,8 @@
#include "imx53-m53.dtsi"
/ {
- model = "DENX M53EVK";
- compatible = "denx,imx53-m53evk", "fsl,imx53";
+ model = "Aries/DENX M53EVK";
+ compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi
index 0777b41..ca51dc0 100644
--- a/dts/src/arm/imx53.dtsi
+++ b/dts/src/arm/imx53.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@@ -131,8 +133,8 @@
reg = <0x18000000 0x08000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
- <&clks IMX5_CLK_IPU_DI0_GATE>,
- <&clks IMX5_CLK_IPU_DI1_GATE>;
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@@ -199,8 +201,8 @@
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -211,8 +213,8 @@
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -223,7 +225,7 @@
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
- <&clks IMX5_CLK_UART3_PER_GATE>;
+ <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
dma-names = "rx", "tx";
@@ -237,7 +239,7 @@
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -264,8 +266,8 @@
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -276,8 +278,8 @@
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
- <&clks IMX5_CLK_DUMMY>,
- <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -419,7 +421,7 @@
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
- <&clks IMX5_CLK_GPT_HF_GATE>;
+ <&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@@ -440,11 +442,11 @@
reg = <0x53fa8008 0x4>;
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
- <&clks IMX5_CLK_LDB_DI1_SEL>,
- <&clks IMX5_CLK_IPU_DI0_SEL>,
- <&clks IMX5_CLK_IPU_DI1_SEL>,
- <&clks IMX5_CLK_LDB_DI0_GATE>,
- <&clks IMX5_CLK_LDB_DI1_GATE>;
+ <&clks IMX5_CLK_LDB_DI1_SEL>,
+ <&clks IMX5_CLK_IPU_DI0_SEL>,
+ <&clks IMX5_CLK_IPU_DI1_SEL>,
+ <&clks IMX5_CLK_LDB_DI0_GATE>,
+ <&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
@@ -486,7 +488,7 @@
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@@ -496,7 +498,7 @@
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
- <&clks IMX5_CLK_PWM2_HF_GATE>;
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@@ -506,7 +508,7 @@
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
- <&clks IMX5_CLK_UART1_PER_GATE>;
+ <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
dma-names = "rx", "tx";
@@ -518,7 +520,7 @@
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
- <&clks IMX5_CLK_UART2_PER_GATE>;
+ <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
dma-names = "rx", "tx";
@@ -530,7 +532,7 @@
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
- <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
+ <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -540,7 +542,7 @@
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
- <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
+ <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -603,7 +605,7 @@
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
- <&clks IMX5_CLK_UART4_PER_GATE>;
+ <&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
dma-names = "rx", "tx";
@@ -635,7 +637,7 @@
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
- <&clks IMX5_CLK_UART5_PER_GATE>;
+ <&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
dma-names = "rx", "tx";
@@ -656,7 +658,7 @@
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
- <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -666,7 +668,7 @@
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
- <&clks IMX5_CLK_SDMA_GATE>;
+ <&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@@ -679,7 +681,7 @@
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
- <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -755,8 +757,8 @@
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>,
- <&clks IMX5_CLK_FEC_GATE>;
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
@@ -766,7 +768,7 @@
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks IMX5_CLK_TVE_GATE>,
- <&clks IMX5_CLK_IPU_DI1_SEL>;
+ <&clks IMX5_CLK_IPU_DI1_SEL>;
clock-names = "tve", "di_sel";
status = "disabled";
@@ -782,7 +784,7 @@
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
- <&clks IMX5_CLK_VPU_GATE>;
+ <&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&ocram>;
@@ -793,7 +795,7 @@
reg = <0x63ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
- <&clks IMX5_CLK_SAHARA_IPG_GATE>;
+ <&clks IMX5_CLK_SAHARA_IPG_GATE>;
clock-names = "ipg", "ahb";
};
};
diff --git a/dts/src/arm/imx6dl-colibri-eval-v3.dts b/dts/src/arm/imx6dl-colibri-eval-v3.dts
new file mode 100644
index 0000000..e0c2172
--- /dev/null
+++ b/dts/src/arm/imx6dl-colibri-eval-v3.dts
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ clocks {
+ /* Fixed crystal dedicated to mcp251x */
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+};
+
+&backlight {
+ brightness-levels = <0 127 191 223 239 247 251 255>;
+ default-brightness-level = <1>;
+ status = "okay";
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ status = "okay";
+
+ mcp251x0: mcp251x@1 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 0x2>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+/*
+ * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t00";
+ reg = <0x68>;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc_cd>;
+ cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
+ status = "okay";
+};
+
+&weim {
+ status = "okay";
+
+ /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
+ ranges = <0 0 0x08000000 0x02000000
+ 1 0 0x0a000000 0x02000000
+ 2 0 0x0c000000 0x02000000>;
+
+ /* SRAM on Colibri nEXT_CS0 */
+ sram@0,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <0 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+
+ /* SRAM on Colibri nEXT_CS1 */
+ sram@1,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <1 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+};
diff --git a/dts/src/arm/imx6dl-icore.dts b/dts/src/arm/imx6dl-icore.dts
new file mode 100644
index 0000000..aec332c
--- /dev/null
+++ b/dts/src/arm/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6dl-riotboard.dts b/dts/src/arm/imx6dl-riotboard.dts
index 75d7343..2cb7282 100644
--- a/dts/src/arm/imx6dl-riotboard.dts
+++ b/dts/src/arm/imx6dl-riotboard.dts
@@ -390,7 +390,7 @@
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
diff --git a/dts/src/arm/imx6dl-tx6dl-comtft.dts b/dts/src/arm/imx6dl-tx6dl-comtft.dts
index 063fe75..aac42ac 100644
--- a/dts/src/arm/imx6dl-tx6dl-comtft.dts
+++ b/dts/src/arm/imx6dl-tx6dl-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/dts/src/arm/imx6dl-tx6u-801x.dts b/dts/src/arm/imx6dl-tx6u-801x.dts
index b7a7284..d1f1298 100644
--- a/dts/src/arm/imx6dl-tx6u-801x.dts
+++ b/dts/src/arm/imx6dl-tx6u-801x.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ipu1_di0_disp0 {
diff --git a/dts/src/arm/imx6q-apalis-ixora.dts b/dts/src/arm/imx6q-apalis-ixora.dts
index 207b85b..0ea75f7 100644
--- a/dts/src/arm/imx6q-apalis-ixora.dts
+++ b/dts/src/arm/imx6q-apalis-ixora.dts
@@ -147,28 +147,6 @@
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
};
-
- pwmleds {
- compatible = "pwm-leds";
-
- ledpwm1 {
- label = "PWM1";
- pwms = <&pwm1 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm2 {
- label = "PWM2";
- pwms = <&pwm2 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm3 {
- label = "PWM3";
- pwms = <&pwm3 0 50000>;
- max-brightness = <255>;
- };
- };
};
&backlight {
diff --git a/dts/src/arm/imx6q-b650v3.dts b/dts/src/arm/imx6q-b650v3.dts
index d853887..1dcaee2 100644
--- a/dts/src/arm/imx6q-b650v3.dts
+++ b/dts/src/arm/imx6q-b650v3.dts
@@ -98,3 +98,9 @@
line-name = "PCA9539-P05";
};
};
+
+&usbphy1 {
+ fsl,tx-cal-45-dn-ohms = <55>;
+ fsl,tx-cal-45-dp-ohms = <55>;
+ fsl,tx-d-cal = <100>;
+};
diff --git a/dts/src/arm/imx6q-cm-fx6.dts b/dts/src/arm/imx6q-cm-fx6.dts
index 59bc5a4..a150bca 100644
--- a/dts/src/arm/imx6q-cm-fx6.dts
+++ b/dts/src/arm/imx6q-cm-fx6.dts
@@ -183,7 +183,6 @@
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
diff --git a/dts/src/arm/imx6q-evi.dts b/dts/src/arm/imx6q-evi.dts
index 6de21ff..7c7c1a8 100644
--- a/dts/src/arm/imx6q-evi.dts
+++ b/dts/src/arm/imx6q-evi.dts
@@ -232,10 +232,7 @@
};
&weim {
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
- fsl,weim-cs-gpr = <&gpr>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
status = "okay";
diff --git a/dts/src/arm/imx6q-icore.dts b/dts/src/arm/imx6q-icore.dts
new file mode 100644
index 0000000..025f543
--- /dev/null
+++ b/dts/src/arm/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6q-nitrogen6_som2.dts b/dts/src/arm/imx6q-nitrogen6_som2.dts
new file mode 100644
index 0000000..cf4feef
--- /dev/null
+++ b/dts/src/arm/imx6q-nitrogen6_som2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-nitrogen6_som2.dtsi"
+
+/ {
+ model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board";
+ compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6q-novena.dts b/dts/src/arm/imx6q-novena.dts
index 1723e89..758bca9 100644
--- a/dts/src/arm/imx6q-novena.dts
+++ b/dts/src/arm/imx6q-novena.dts
@@ -451,6 +451,10 @@
status = "okay";
};
+&pwm1 {
+ status = "okay";
+};
+
&sata {
target-supply = <&reg_sata>;
fsl,transmit-level-mV = <1025>;
diff --git a/dts/src/arm/imx6q-phytec-pbab01.dts b/dts/src/arm/imx6q-phytec-pbab01.dts
index c139ac0..1f47713 100644
--- a/dts/src/arm/imx6q-phytec-pbab01.dts
+++ b/dts/src/arm/imx6q-phytec-pbab01.dts
@@ -23,5 +23,5 @@
};
&sata {
- status = "okay";
+ status = "okay";
};
diff --git a/dts/src/arm/imx6q-tx6q-1010-comtft.dts b/dts/src/arm/imx6q-tx6q-1010-comtft.dts
index 65e95ae..71746ed 100644
--- a/dts/src/arm/imx6q-tx6q-1010-comtft.dts
+++ b/dts/src/arm/imx6q-tx6q-1010-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/dts/src/arm/imx6q-tx6q-1010.dts b/dts/src/arm/imx6q-tx6q-1010.dts
index 20cd0e7..f9cd21a 100644
--- a/dts/src/arm/imx6q-tx6q-1010.dts
+++ b/dts/src/arm/imx6q-tx6q-1010.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ipu1_di0_disp0 {
diff --git a/dts/src/arm/imx6q-tx6q-1020-comtft.dts b/dts/src/arm/imx6q-tx6q-1020-comtft.dts
index 9ed243b..959ff3f 100644
--- a/dts/src/arm/imx6q-tx6q-1020-comtft.dts
+++ b/dts/src/arm/imx6q-tx6q-1020-comtft.dts
@@ -105,7 +105,7 @@
pixelclk-active = <1>;
};
};
- };
+ };
};
&can1 {
diff --git a/dts/src/arm/imx6q-tx6q-1020.dts b/dts/src/arm/imx6q-tx6q-1020.dts
index 347b531..b49133d 100644
--- a/dts/src/arm/imx6q-tx6q-1020.dts
+++ b/dts/src/arm/imx6q-tx6q-1020.dts
@@ -199,7 +199,7 @@
pixelclk-active = <0>;
};
};
- };
+ };
};
&ds1339 {
diff --git a/dts/src/arm/imx6q-utilite-pro.dts b/dts/src/arm/imx6q-utilite-pro.dts
index 6199063..2200994 100644
--- a/dts/src/arm/imx6q-utilite-pro.dts
+++ b/dts/src/arm/imx6q-utilite-pro.dts
@@ -68,7 +68,41 @@
label = "Power Button";
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
- gpio-key,wakeup;
+ wakeup-source;
+ };
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c1>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "at24,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ em3027: rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+ };
+
+ i2c_dvi_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
@@ -82,17 +116,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
-
- eeprom@50 {
- compatible = "at24,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- em3027: rtc@56 {
- compatible = "emmicro,em3027";
- reg = <0x56>;
- };
};
&i2c2 {
@@ -115,6 +138,12 @@
>;
};
+ pinctrl_i2c1mux: i2c1muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi
index 99e323b..8c8a049 100644
--- a/dts/src/arm/imx6qdl-apalis.dtsi
+++ b/dts/src/arm/imx6qdl-apalis.dtsi
@@ -49,7 +49,10 @@
backlight: backlight {
compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
pwms = <&pwm4 0 5000000>;
+ enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -620,6 +623,12 @@
>;
};
+ pinctrl_gpio_bl_on: gpioblon {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
+ >;
+ };
+
pinctrl_gpio_keys: gpio1io04grp {
fsl,pins = <
/* Power button */
diff --git a/dts/src/arm/imx6qdl-apf6dev.dtsi b/dts/src/arm/imx6qdl-apf6dev.dtsi
index edbce222..5e7792d 100644
--- a/dts/src/arm/imx6qdl-apf6dev.dtsi
+++ b/dts/src/arm/imx6qdl-apf6dev.dtsi
@@ -347,13 +347,13 @@
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};
diff --git a/dts/src/arm/imx6qdl-colibri.dtsi b/dts/src/arm/imx6qdl-colibri.dtsi
new file mode 100644
index 0000000..e6faa65
--- /dev/null
+++ b/dts/src/arm/imx6qdl-colibri.dtsi
@@ -0,0 +1,890 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Toradex Colibri iMX6DL/S Module";
+ compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ pwms = <&pwm3 0 5000000>;
+ enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
+ status = "disabled";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_host_vbus: regulator-usb-host-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
+ status = "disabled";
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx6dl-colibri-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias";
+ mux-int-port = <1>;
+ mux-ext-port = <5>;
+ };
+
+ /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
+ sound_spdif: sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ spdif-out;
+ status = "disabled";
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
+ status = "okay";
+};
+
+/* Optional on SODIMM 55/63 */
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+/* Optional on SODIMM 178/188 */
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ status = "disabled";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_ddc>;
+ status = "disabled";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vgen1: unused */
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vgen3: unused */
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <&reg_2p5v>;
+ VDDIO-supply = <&reg_3p3v>;
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio6>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ reg = <0>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+ };
+};
+
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "recovery";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+/* Colibri PWM<B> */
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "disabled";
+};
+
+/* Colibri PWM<D> */
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "disabled";
+};
+
+/* Colibri PWM<A> */
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "disabled";
+};
+
+/* Colibri PWM<C> */
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "disabled";
+};
+
+/* Optional S/PDIF out on SODIMM 137 */
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ status = "disabled";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+ fsl,dte-mode;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Colibri UART_B */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ fsl,dte-mode;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Colibri UART_C */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dte>;
+ fsl,dte-mode;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ disable-over-current;
+ dr_mode = "peripheral";
+ status = "disabled";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ vqmmc-supply = <&reg_3p3v>;
+ bus-width = <4>;
+ voltage-ranges = <3300 3300>;
+ status = "disabled";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vqmmc-supply = <&reg_3p3v>;
+ bus-width = <8>;
+ voltage-ranges = <3300 3300>;
+ non-removable;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
+ &pinctrl_weim_cs1 &pinctrl_weim_cs2
+ &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
+ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
+ /* SGTL5000 sys_mclk */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
+ >;
+ };
+
+ pinctrl_cam_mclk: cammclkgrp {
+ fsl,pins = <
+ /* Parallel Camera CAM sys_mclk */
+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ /* SPI CS */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpioblon {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeys {
+ fsl,pins = <
+ /* Power button */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmi_ddc: hdmiddcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_recovery: i2c3recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
+ MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
+ MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
+ MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
+ MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
+ MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
+ MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
+ MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
+ MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
+ /* Disable PWM pins on camera interface */
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
+ >;
+ };
+
+ pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
+ >;
+ };
+
+ pinctrl_mic_gnd: gpiomicgnd {
+ fsl,pins = <
+ /* Controls Mic GND, PU or '1' pull Mic GND to GND */
+ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
+ >;
+ };
+
+ pinctrl_mmc_cd: gpiommccd {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+ fsl,pins = <
+ /* USBH_EN */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_touch_int: gpiotouchintgrp {
+ fsl,pins = <
+ /* STMPE811 interrupt */
+ MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1_dce: uart1dcegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ /* DTE mode */
+ pinctrl_uart1_dte: uart1dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+ >;
+ };
+
+ /* Additional DTR, DSR, DCD */
+ pinctrl_uart1_ctrl: uart1ctrlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart2_dte: uart2dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3_dte: uart3dtegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbc_det: usbcdetgrp {
+ fsl,pins = <
+ /* USBC_DET */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ /* USBC_DET_EN */
+ MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
+ /* USBC_DET_OVERWRITE */
+ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
+ /* eMMC reset */
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
+ >;
+ };
+
+ pinctrl_weim_cs0: weimcs0grp {
+ fsl,pins = <
+ /* nEXT_CS0 */
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs1: weimcs1grp {
+ fsl,pins = <
+ /* nEXT_CS1 */
+ MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs2: weimcs2grp {
+ fsl,pins = <
+ /* nEXT_CS2 */
+ MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_sram: weimsramgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ /* Data */
+ MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+ /* Address */
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_rdnwr: weimrdnwr {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
+ >;
+ };
+
+ pinctrl_weim_npwe: weimnpwe {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
+ MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
+ >;
+ };
+
+ /* ADDRESS[16:18] [25] used as GPIO */
+ pinctrl_weim_gpio_1: weimgpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ /* ADDRESS[19:24] used as GPIO */
+ pinctrl_weim_gpio_2: weimgpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ /* DATA[16:31] used as GPIO */
+ pinctrl_weim_gpio_3: weimgpio-3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ /* DQM[0:3] used as GPIO */
+ pinctrl_weim_gpio_4: weimgpio-4 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ >;
+ };
+
+ /* RDY used as GPIO */
+ pinctrl_weim_gpio_5: weimgpio-5 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
+ >;
+ };
+
+ /* ADDRESS[16] DATA[30] used as GPIO */
+ pinctrl_weim_gpio_6: weimgpio-6 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-gw52xx.dtsi b/dts/src/arm/imx6qdl-gw52xx.dtsi
index a7100f9..54aca3a 100644
--- a/dts/src/arm/imx6qdl-gw52xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw52xx.dtsi
@@ -153,9 +153,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi3 {
diff --git a/dts/src/arm/imx6qdl-gw53xx.dtsi b/dts/src/arm/imx6qdl-gw53xx.dtsi
index 8953eba..88e5cb3 100644
--- a/dts/src/arm/imx6qdl-gw53xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw53xx.dtsi
@@ -154,9 +154,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/dts/src/arm/imx6qdl-gw54xx.dtsi b/dts/src/arm/imx6qdl-gw54xx.dtsi
index 6ac41c7..1753ab7 100644
--- a/dts/src/arm/imx6qdl-gw54xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw54xx.dtsi
@@ -144,9 +144,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/dts/src/arm/imx6qdl-gw552x.dtsi b/dts/src/arm/imx6qdl-gw552x.dtsi
index 805e236..ee83161 100644
--- a/dts/src/arm/imx6qdl-gw552x.dtsi
+++ b/dts/src/arm/imx6qdl-gw552x.dtsi
@@ -291,7 +291,7 @@
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
- };
+ };
pinctrl_wdog: wdoggrp {
fsl,pins = <
diff --git a/dts/src/arm/imx6qdl-icore.dtsi b/dts/src/arm/imx6qdl-icore.dtsi
new file mode 100644
index 0000000..023839a
--- /dev/null
+++ b/dts/src/arm/imx6qdl-icore.dtsi
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ rmii_clk: clock-rmii-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>; /* 25MHz for example */
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_3p3v>;
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_3p3v>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-nit6xlite.dtsi b/dts/src/arm/imx6qdl-nit6xlite.dtsi
index 880bd78..63acd54 100644
--- a/dts/src/arm/imx6qdl-nit6xlite.dtsi
+++ b/dts/src/arm/imx6qdl-nit6xlite.dtsi
@@ -97,15 +97,6 @@
};
};
- bt_rfkill {
- compatible = "rfkill-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt_rfkill>;
- gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
- name = "bt_rfkill";
- type = <2>;
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -160,7 +151,7 @@
};
};
- backlight_lcd {
+ backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -169,7 +160,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -178,7 +169,7 @@
status = "okay";
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -328,19 +319,6 @@
>;
};
- pinctrl_bt_rfkill: bt_rfkillgrp {
- fsl,pins = <
- /* BT wake */
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- /* BT reset */
- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0
- /* BT reg en */
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
- /* BT host wake irq */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0
- >;
- };
-
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
@@ -374,7 +352,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Home Button: J14 pin 5 */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
@@ -457,7 +435,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
index b0b3220..34887a1 100644
--- a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
@@ -229,7 +229,7 @@
};
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -238,7 +238,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -247,7 +247,7 @@
status = "okay";
};
- backlight_lvds1: backlight_lvds1 {
+ backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -282,7 +282,7 @@
};
};
- panel_lcd {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -293,7 +293,7 @@
};
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -304,7 +304,7 @@
};
};
- panel_lvds1 {
+ panel-lvds1 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds1>;
@@ -447,7 +447,7 @@
};
&iomuxc {
- imx6q-nitrogen6_max {
+ imx6q-nitrogen6-max {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
@@ -504,7 +504,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -720,7 +720,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
diff --git a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
new file mode 100644
index 0000000..d80f21a
--- /dev/null
+++ b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
@@ -0,0 +1,770 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lcd: backlight-lcd {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <&reg_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <&reg_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds1: backlight-lvds1 {
+ compatible = "gpio-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_lvds1>;
+ gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ default-on;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ menu {
+ label = "Menu";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ };
+
+ home {
+ label = "Home";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ back {
+ label = "Back";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_j15>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel-lcd {
+ compatible = "okaya,rs800480t-7x0gp";
+ backlight = <&backlight_lcd>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ panel-lvds0 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds0>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel-lvds1 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds1>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_can_xcvr: regulator-can-xcvr {
+ compatible = "regulator-fixed";
+ regulator-name = "CAN XCVR";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_xcvr>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_wlan_vmmc: regulator-wlan-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan_vmmc>;
+ regulator-name = "reg_wlan_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-nitrogen6_som2-sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <&reg_can_xcvr>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ compatible = "microchip,sst25vf016b";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <&reg_2p5v>;
+ VDDIO-supply = <&reg_3p3v>;
+ };
+
+ rtc@68 {
+ compatible = "st,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ touchscreen@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_backlight_lvds1: backlight-lvds1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0
+ >;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_can_xcvr: can-xcvrgrp {
+ fsl,pins = <
+ /* Flexcan XCVR enable */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ /* Power Button */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ /* Menu Button */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ /* Home Button */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ /* Back Button */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ /* Volume Up Button */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
+ /* Volume Down Button */
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ /* PCIe I2C enable */
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
+ >;
+ };
+
+ pinctrl_j15: j15grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ /* PCIe reset */
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_rv4162: rv4162grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+ /* power enable, high active */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0
+ MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
+ >;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <&reg_wlan_vmmc>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <&reg_1p8v>;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
index db868bc..e476d01 100644
--- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
@@ -167,7 +167,7 @@
mux-ext-port = <3>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -176,7 +176,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -211,7 +211,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -222,7 +222,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -413,7 +413,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -561,7 +561,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
diff --git a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
index e0280ca..e9801a2 100644
--- a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
@@ -427,10 +427,10 @@
};
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ status = "disabled";
};
diff --git a/dts/src/arm/imx6qdl-sabreauto.dtsi b/dts/src/arm/imx6qdl-sabreauto.dtsi
index e000e6f..52390ba 100644
--- a/dts/src/arm/imx6qdl-sabreauto.dtsi
+++ b/dts/src/arm/imx6qdl-sabreauto.dtsi
@@ -283,7 +283,7 @@
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
- };
+ };
};
@@ -613,8 +613,6 @@
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi
index 81dd6cd..1f9076e 100644
--- a/dts/src/arm/imx6qdl-sabrelite.dtsi
+++ b/dts/src/arm/imx6qdl-sabrelite.dtsi
@@ -153,7 +153,7 @@
mux-ext-port = <4>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -162,7 +162,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -197,7 +197,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -208,7 +208,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -378,7 +378,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
diff --git a/dts/src/arm/imx6qdl-sabresd.dtsi b/dts/src/arm/imx6qdl-sabresd.dtsi
index 8e9e0d9..55ef535 100644
--- a/dts/src/arm/imx6qdl-sabresd.dtsi
+++ b/dts/src/arm/imx6qdl-sabresd.dtsi
@@ -129,8 +129,8 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
- gpios = <&gpio1 2 0>;
- default-state = "on";
+ gpios = <&gpio1 2 0>;
+ default-state = "on";
};
};
diff --git a/dts/src/arm/imx6qdl-tx6.dtsi b/dts/src/arm/imx6qdl-tx6.dtsi
index ac9529f..2bf2e62 100644
--- a/dts/src/arm/imx6qdl-tx6.dtsi
+++ b/dts/src/arm/imx6qdl-tx6.dtsi
@@ -429,8 +429,8 @@
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
@@ -481,21 +481,21 @@
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
diff --git a/dts/src/arm/imx6qdl-wandboard-revb1.dtsi b/dts/src/arm/imx6qdl-wandboard-revb1.dtsi
index ef7fa62..a320891 100644
--- a/dts/src/arm/imx6qdl-wandboard-revb1.dtsi
+++ b/dts/src/arm/imx6qdl-wandboard-revb1.dtsi
@@ -28,7 +28,7 @@
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
>;
};
};
diff --git a/dts/src/arm/imx6qdl-wandboard.dtsi b/dts/src/arm/imx6qdl-wandboard.dtsi
index 2b9c2be..82dc574 100644
--- a/dts/src/arm/imx6qdl-wandboard.dtsi
+++ b/dts/src/arm/imx6qdl-wandboard.dtsi
@@ -129,8 +129,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index b13b0b2..53e6e63 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -13,9 +13,10 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
can0 = &can1;
@@ -204,9 +205,9 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
@@ -1092,10 +1093,13 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/dts/src/arm/imx6qp.dtsi b/dts/src/arm/imx6qp.dtsi
index 886dbf2..0d4977a 100644
--- a/dts/src/arm/imx6qp.dtsi
+++ b/dts/src/arm/imx6qp.dtsi
@@ -85,5 +85,22 @@
pcie: pcie@0x01000000 {
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
};
+
+ aips-bus@02100000 {
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+ };
};
};
+
+&ldb {
+ clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+ "di0", "di1";
+};
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index 02378db..4fd6de2 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -8,11 +8,13 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
-#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@@ -893,8 +895,11 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/dts/src/arm/imx6sx-sdb.dtsi b/dts/src/arm/imx6sx-sdb.dtsi
index 9d70cfd..da81552 100644
--- a/dts/src/arm/imx6sx-sdb.dtsi
+++ b/dts/src/arm/imx6sx-sdb.dtsi
@@ -192,10 +192,10 @@
};
&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
@@ -290,6 +290,14 @@
status = "okay";
};
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
diff --git a/dts/src/arm/imx6sx-udoo-neo-basic.dts b/dts/src/arm/imx6sx-udoo-neo-basic.dts
new file mode 100644
index 0000000..0c1fc1a
--- /dev/null
+++ b/dts/src/arm/imx6sx-udoo-neo-basic.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Basic";
+ compatible = "udoo,neobasic", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&fec1 {
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo-extended.dts b/dts/src/arm/imx6sx-udoo-neo-extended.dts
new file mode 100644
index 0000000..5d6c227
--- /dev/null
+++ b/dts/src/arm/imx6sx-udoo-neo-extended.dts
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Extended";
+ compatible = "udoo,neoextended", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo-full.dts b/dts/src/arm/imx6sx-udoo-neo-full.dts
new file mode 100644
index 0000000..653ceb2
--- /dev/null
+++ b/dts/src/arm/imx6sx-udoo-neo-full.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx-udoo-neo.dtsi"
+
+/ {
+ model = "UDOO Neo Full";
+ compatible = "udoo,neofull", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&fec1 {
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo.dtsi b/dts/src/arm/imx6sx-udoo-neo.dtsi
new file mode 100644
index 0000000..2b65d26
--- /dev/null
+++ b/dts/src/arm/imx6sx-udoo-neo.dtsi
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWIS