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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-14 11:48:37 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-14 11:48:37 +0100 |
commit | b73c4f6c38bb94fe5a00b9cd47fe8a6578ac7c49 (patch) | |
tree | 3a7777fca34ce5724ddd959bd7ecca362d4109d6 /dts/src/arm | |
parent | 55f509cd644e9f5c476bf89a7c40bbe50c0ba217 (diff) | |
download | barebox-b73c4f6c38bb94fe5a00b9cd47fe8a6578ac7c49.tar.gz barebox-b73c4f6c38bb94fe5a00b9cd47fe8a6578ac7c49.tar.xz |
dts: update to v5.16
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm')
-rw-r--r-- | dts/src/arm/bcm2711.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm/bcm283x.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_arria10.dtsi | 2 |
4 files changed, 6 insertions, 2 deletions
diff --git a/dts/src/arm/bcm2711.dtsi b/dts/src/arm/bcm2711.dtsi index 9e01dbca4a..dff18fc9a9 100644 --- a/dts/src/arm/bcm2711.dtsi +++ b/dts/src/arm/bcm2711.dtsi @@ -582,6 +582,8 @@ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&gpio 0 0 58>; + gpclk0_gpio49: gpclk0_gpio49 { pin-gpclk { pins = "gpio49"; diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi index a3e06b6809..c113661a66 100644 --- a/dts/src/arm/bcm283x.dtsi +++ b/dts/src/arm/bcm283x.dtsi @@ -126,6 +126,8 @@ interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&gpio 0 0 54>; + /* Defines common pin muxing groups * * While each pin can have its mux selected diff --git a/dts/src/arm/socfpga.dtsi b/dts/src/arm/socfpga.dtsi index 0b021eef0b..7c1d6423d7 100644 --- a/dts/src/arm/socfpga.dtsi +++ b/dts/src/arm/socfpga.dtsi @@ -782,7 +782,7 @@ }; qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, diff --git a/dts/src/arm/socfpga_arria10.dtsi b/dts/src/arm/socfpga_arria10.dtsi index a574ea91d9..3ba431dfa8 100644 --- a/dts/src/arm/socfpga_arria10.dtsi +++ b/dts/src/arm/socfpga_arria10.dtsi @@ -756,7 +756,7 @@ }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, |