diff options
Diffstat (limited to 'arch/arm/boards/phytec-som-imx8mq/lowlevel.c')
-rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 46 |
1 files changed, 13 insertions, 33 deletions
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 05226866f8..362b3ed823 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -6,24 +6,25 @@ #include <common.h> #include <firmware.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8m-ccm-regs.h> -#include <mach/iomux-mx8mq.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> #include <soc/imx8m/ddr.h> -#include <mach/xload.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" -extern char __dtb_imx8mq_phytec_phycore_som_start[]; +extern char __dtb_z_imx8mq_phytec_phycore_som_start[]; #define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) @@ -42,22 +43,6 @@ static void setup_uart(void) putc_ll('>'); } -static void phytec_imx8mq_som_sram_setup(void) -{ - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - - ddr_init(); - - imx8mq_get_boot_source(&src, &instance); - - if (src == BOOTSOURCE_MMC) - ret = imx8m_esdhc_load_image(instance, true); - - BUG_ON(ret); -} - static __noreturn noinline void phytec_phycore_imx8mq_start(void) { setup_uart(); @@ -69,7 +54,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * that means DDR needs to be initialized for the * first time. */ - phytec_imx8mq_som_sram_setup(); + ddr_init(); } /* * Straight from the power-on we are at EL3, so the following @@ -79,18 +64,13 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * initialization routine, it is EL2 which means we'll skip * loadting ATF blob again */ - if (current_el() == 3) { - const u8 *bl31; - size_t bl31_size; - - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - imx8mq_atf_load_bl31(bl31, bl31_size); - } + if (current_el() == 3) + imx8mq_load_and_start_image_via_tfa(); /* * Standard entry we hit once we initialized both DDR and ATF */ - imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); + imx8mq_barebox_entry(__dtb_z_imx8mq_phytec_phycore_som_start); } /* @@ -108,7 +88,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR, * executing start_phytec_phycore_imx8mq() the third time * * 6. Standard barebox boot flow continues |