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-rw-r--r--arch/arm/boards/Makefile1
-rw-r--r--arch/arm/boards/altera-socdk/board.c2
-rw-r--r--arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c2
-rw-r--r--arch/arm/boards/altera-socdk/lowlevel.c4
-rw-r--r--arch/arm/boards/ebv-socrates/board.c2
-rw-r--r--arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c2
-rw-r--r--arch/arm/boards/ebv-socrates/lowlevel.c4
-rw-r--r--arch/arm/boards/reflex-achilles/Makefile2
-rw-r--r--arch/arm/boards/reflex-achilles/lowlevel.c48
-rw-r--r--arch/arm/boards/reflex-achilles/pinmux-config-arria10.c102
-rw-r--r--arch/arm/boards/reflex-achilles/pll-config-arria10.c54
-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/board.c2
-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c2
-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/lowlevel.c4
-rw-r--r--arch/arm/boards/terasic-sockit/board.c1
-rw-r--r--arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c2
-rw-r--r--arch/arm/boards/terasic-sockit/lowlevel.c4
17 files changed, 222 insertions, 16 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 0f08ebb9e4..0ecfb3e4b3 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/
diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c
index d7fb923a04..f4b1dcd324 100644
--- a/arch/arm/boards/altera-socdk/board.c
+++ b/arch/arm/boards/altera-socdk/board.c
@@ -8,7 +8,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int ksz9021rn_phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
index 07a4485f1f..9777d15dfe 100644
--- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
= {
diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c
index 02c995fe45..8cfe839159 100644
--- a/arch/arm/boards/altera-socdk/lowlevel.c
+++ b/arch/arm/boards/altera-socdk/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c
index f3207b88ef..965150f9a3 100644
--- a/arch/arm/boards/ebv-socrates/board.c
+++ b/arch/arm/boards/ebv-socrates/board.c
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
index ab6733f92b..9a814cba79 100644
--- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index ea4e1d746a..9643269f8e 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -7,13 +7,13 @@
#include <mach/generic.h>
#include <debug_ll.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile
new file mode 100644
index 0000000000..6b42141153
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
new file mode 100644
index 0000000000..12994177cc
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -0,0 +1,48 @@
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <debug_ll.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include "pll-config-arria10.c"
+#include "pinmux-config-arria10.c"
+#include <mach/generic.h>
+
+extern char __dtb_socfpga_arria10_achilles_start[];
+
+static noinline void achilles_entry(void)
+{
+ void *fdt;
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ puts_ll("lowlevel init done\n");
+
+ arria10_ddr_calibration_sequence();
+
+ puts_ll("SDRAM setup done\n");
+
+ fdt = __dtb_socfpga_arria10_achilles_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
+{
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(0xffe00000 + SZ_256K - SZ_32K - SZ_4K - 16);
+
+ achilles_entry();
+}
diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
new file mode 100644
index 0000000000..246838a228
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
@@ -0,0 +1,102 @@
+#include <mach/arria10-pinmux.h>
+
+static uint32_t pinmux[] = {
+[arria10_pinmux_shared_io_q4_12] = 8,
+[arria10_pinmux_shared_io_q4_11] = 8,
+[arria10_pinmux_shared_io_q4_10] = 8,
+[arria10_pinmux_shared_io_q4_9] = 8,
+[arria10_pinmux_shared_io_q4_8] = 8,
+[arria10_pinmux_shared_io_q4_6] = 8,
+[arria10_pinmux_shared_io_q4_7] = 8,
+[arria10_pinmux_shared_io_q4_5] = 8,
+[arria10_pinmux_shared_io_q4_4] = 8,
+[arria10_pinmux_shared_io_q4_3] = 8,
+[arria10_pinmux_shared_io_q4_2] = 8,
+[arria10_pinmux_shared_io_q4_1] = 8,
+[arria10_pinmux_shared_io_q3_12] = 8,
+[arria10_pinmux_shared_io_q3_11] = 8,
+[arria10_pinmux_shared_io_q3_10] = 8,
+[arria10_pinmux_shared_io_q3_8] = 8,
+[arria10_pinmux_shared_io_q3_9] = 8,
+[arria10_pinmux_shared_io_q3_7] = 8,
+[arria10_pinmux_shared_io_q3_6] = 8,
+[arria10_pinmux_shared_io_q3_5] = 8,
+[arria10_pinmux_shared_io_q3_4] = 8,
+[arria10_pinmux_shared_io_q3_3] = 8,
+[arria10_pinmux_shared_io_q3_2] = 8,
+[arria10_pinmux_shared_io_q3_1] = 8,
+[arria10_pinmux_shared_io_q2_12] = 8,
+[arria10_pinmux_shared_io_q2_10] = 8,
+[arria10_pinmux_shared_io_q2_11] = 8,
+[arria10_pinmux_shared_io_q2_9] = 8,
+[arria10_pinmux_shared_io_q2_8] = 8,
+[arria10_pinmux_shared_io_q2_7] = 8,
+[arria10_pinmux_shared_io_q2_6] = 8,
+[arria10_pinmux_shared_io_q2_5] = 8,
+[arria10_pinmux_shared_io_q2_4] = 8,
+[arria10_pinmux_shared_io_q2_3] = 8,
+[arria10_pinmux_shared_io_q2_2] = 8,
+[arria10_pinmux_shared_io_q2_1] = 8,
+[arria10_pinmux_shared_io_q1_12] = 10,
+[arria10_pinmux_shared_io_q1_11] = 10,
+[arria10_pinmux_shared_io_q1_10] = 1,
+[arria10_pinmux_shared_io_q1_9] = 1,
+[arria10_pinmux_shared_io_q1_8] = 1,
+[arria10_pinmux_shared_io_q1_7] = 1,
+[arria10_pinmux_shared_io_q1_6] = 0,
+[arria10_pinmux_shared_io_q1_5] = 0,
+[arria10_pinmux_shared_io_q1_4] = 13,
+[arria10_pinmux_shared_io_q1_3] = 13,
+[arria10_pinmux_shared_io_q1_2] = 13,
+[arria10_pinmux_shared_io_q1_1] = 13,
+[arria10_pinmux_dedicated_io_4] = 8,
+[arria10_pinmux_dedicated_io_5] = 8,
+[arria10_pinmux_dedicated_io_6] = 8,
+[arria10_pinmux_dedicated_io_7] = 8,
+[arria10_pinmux_dedicated_io_8] = 8,
+[arria10_pinmux_dedicated_io_9] = 8,
+[arria10_pinmux_dedicated_io_10] = 10,
+[arria10_pinmux_dedicated_io_11] = 10,
+[arria10_pinmux_dedicated_io_12] = 8,
+[arria10_pinmux_dedicated_io_13] = 8,
+[arria10_pinmux_dedicated_io_14] = 8,
+[arria10_pinmux_dedicated_io_15] = 8,
+[arria10_pinmux_dedicated_io_16] = 15,
+[arria10_pinmux_dedicated_io_17] = 15,
+[arria10_pincfg_dedicated_io_bank] = 0x101,
+[arria10_pincfg_dedicated_io_1] = 0xb080a,
+[arria10_pincfg_dedicated_io_2] = 0xb080a,
+[arria10_pincfg_dedicated_io_3] = 0xb080a,
+[arria10_pincfg_dedicated_io_4] = 0xa282a,
+[arria10_pincfg_dedicated_io_5] = 0xa282a,
+[arria10_pincfg_dedicated_io_6] = 0xa282a,
+[arria10_pincfg_dedicated_io_7] = 0xa282a,
+[arria10_pincfg_dedicated_io_8] = 0xa282a,
+[arria10_pincfg_dedicated_io_9] = 0xa282a,
+[arria10_pincfg_dedicated_io_10] = 0x90000,
+[arria10_pincfg_dedicated_io_11] = 0x90000,
+[arria10_pincfg_dedicated_io_12] = 0xa282a,
+[arria10_pincfg_dedicated_io_13] = 0xa282a,
+[arria10_pincfg_dedicated_io_14] = 0xa282a,
+[arria10_pincfg_dedicated_io_15] = 0xa282a,
+[arria10_pincfg_dedicated_io_16] = 0xa282a,
+[arria10_pincfg_dedicated_io_17] = 0xa282a,
+[arria10_pinmux_rgmii0_usefpga] = 0,
+[arria10_pinmux_rgmii1_usefpga] = 0,
+[arria10_pinmux_rgmii2_usefpga] = 0,
+[arria10_pinmux_nand_usefpga] = 0,
+[arria10_pinmux_qspi_usefpga] = 0,
+[arria10_pinmux_sdmmc_usefpga] = 0,
+[arria10_pinmux_spim0_usefpga] = 1,
+[arria10_pinmux_spim1_usefpga] = 0,
+[arria10_pinmux_spis0_usefpga] = 0,
+[arria10_pinmux_spis1_usefpga] = 0,
+[arria10_pinmux_uart0_usefpga] = 0,
+[arria10_pinmux_uart1_usefpga] = 0,
+[arria10_pinmux_i2c0_usefpga] = 0,
+[arria10_pinmux_i2c1_usefpga] = 0,
+[arria10_pinmux_i2cemac0_usefpga] = 0,
+[arria10_pinmux_i2cemac1_usefpga] = 0,
+[arria10_pinmux_i2cemac2_usefpga] = 0,
+};
+
diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
new file mode 100644
index 0000000000..94d596606e
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
@@ -0,0 +1,54 @@
+#include <mach/arria10-clock-manager.h>
+
+static struct arria10_mainpll_cfg mainpll_cfg = {
+ .cntr15clk_cnt = 900,
+ .cntr2clk_cnt = 900,
+ .cntr3clk_cnt = 900,
+ .cntr4clk_cnt = 900,
+ .cntr5clk_cnt = 900,
+ .cntr6clk_cnt = 7,
+ .cntr7clk_cnt = 900,
+ .cntr7clk_src = 0,
+ .cntr8clk_cnt = 900,
+ .cntr9clk_cnt = 900,
+ .cntr9clk_src = 0,
+ .mpuclk_cnt = 0,
+ .mpuclk_src = 0,
+ .nocclk_cnt = 0,
+ .nocclk_src = 0,
+ .nocdiv_csatclk = 2,
+ .nocdiv_cspdbgclk = 0,
+ .nocdiv_cstraceclk = 0,
+ .nocdiv_l4mainclk = 2,
+ .nocdiv_l4mpclk = 2,
+ .nocdiv_l4spclk = 2,
+ .vco0_psrc = 0,
+ .vco1_denom = 1,
+ .vco1_numer = 127,
+ .mpuclk = 0x3840001,
+ .nocclk = 0x3840003,
+};
+
+static struct arria10_perpll_cfg perpll_cfg = {
+ .cntr2clk_cnt = 5,
+ .cntr2clk_src = 1,
+ .cntr3clk_cnt = 900,
+ .cntr3clk_src = 1,
+ .cntr4clk_cnt = 14,
+ .cntr4clk_src = 1,
+ .cntr5clk_cnt = 374,
+ .cntr5clk_src = 1,
+ .cntr6clk_cnt = 900,
+ .cntr6clk_src = 0,
+ .cntr7clk_cnt = 900,
+ .cntr8clk_cnt = 900,
+ .cntr8clk_src = 0,
+ .cntr9clk_cnt = 900,
+ .emacctl_emac0sel = 0,
+ .emacctl_emac1sel = 0,
+ .emacctl_emac2sel = 0,
+ .gpiodiv_gpiodbclk = 32000,
+ .vco0_psrc = 0,
+ .vco1_denom = 1,
+ .vco1_numer = 119,
+};
diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c
index 919bfc8c54..8e69319d17 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/board.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/board.c
@@ -8,7 +8,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
index 4e9ac7fb77..d5098055ff 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index 6d937abda5..1d5ea6b12a 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c
index 53cd36834f..ec68315998 100644
--- a/arch/arm/boards/terasic-sockit/board.c
+++ b/arch/arm/boards/terasic-sockit/board.c
@@ -8,7 +8,6 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
index 117d7f4ebc..9367b0d110 100644
--- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
index 8012783df3..0a6eb21365 100644
--- a/arch/arm/boards/terasic-sockit/lowlevel.c
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 08:31:40 +0000