diff options
Diffstat (limited to 'arch/arm/dts/imx8mm.dtsi')
| -rw-r--r-- | arch/arm/dts/imx8mm.dtsi | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi new file mode 100644 index 0000000000..01f74c1074 --- /dev/null +++ b/arch/arm/dts/imx8mm.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/features/imx8m.h> + +/ { + aliases { + gpr.reboot_mode = &reboot_mode_gpr; + pwm0 = &pwm1; + pwm1 = &pwm2; + pwm2 = &pwm3; + pwm3 = &pwm4; + }; + + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; + }; +}; + +feat: &ocotp { + #feature-cells = <1>; + barebox,feature-controller; +}; + +&src { + compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon", "simple-mfd"; + + reboot_mode_gpr: reboot-mode { + compatible = "barebox,syscon-reboot-mode"; + offset = <0x94>, <0x98>; /* SRC_GPR{9,10} */ + mask = <0xffffffff>, <0x40000000>; + mode-normal = <0>, <0>; + mode-serial = <0x00000010>, <0x40000000>; + }; +}; + +&A53_1 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>; +}; + +&A53_2 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&A53_3 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&gpc { + barebox,feature-gates = <&feat 0>; +}; + +&vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_blk_ctrl { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpumix { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_h1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; |