diff options
Diffstat (limited to 'arch/arm/dts')
323 files changed, 11953 insertions, 8623 deletions
diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore deleted file mode 100644 index 077903c50a..0000000000 --- a/arch/arm/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*dtb* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8bba8749fa..056d4d565b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -7,6 +7,7 @@ obj- += dummy.o lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o +lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o @@ -26,6 +27,7 @@ lwl-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o lwl-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o lwl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o lwl-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o +lwl-$(CONFIG_MACH_MEERKAT96) += imx7d-meerkat96.dtb.o lwl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o lwl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o lwl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o @@ -34,6 +36,8 @@ lwl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o lwl-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o lwl-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o lwl-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += imx7d-flex-concentrator-mfg.dtb.o +lwl-$(CONFIG_MACH_KARO_QSXP_ML81) += imx8mp-karo-qsxp-ml81-qsbase4.dtb.o +lwl-$(CONFIG_MACH_KOENIGBAUER_ALPHAJET) += imx8mp-koenigbauer-alphajet.dtb.o lwl-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \ imx6dl-samx6i.dtb.o lwl-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o @@ -45,6 +49,7 @@ lwl-$(CONFIG_MACH_MYIRTECH_X335X) += am335x-myirtech-myd.dtb.o lwl-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o lwl-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o lwl-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o +lwl-$(CONFIG_MACH_NOVENA) += imx6q-novena.dtb.o lwl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o lwl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o lwl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o @@ -78,10 +83,14 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \ imx6ull-phytec-phycore-som-emmc.dtb.o lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += stm32mp157c-phycore-stm32mp1-3.dtb.o +lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += imx8mm-phyboard-polis-rdk.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o lwl-$(CONFIG_MACH_PINE64_QUARTZ64) += rk3566-quartz64-a.dtb.o lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o +lwl-$(CONFIG_MACH_POLYHEX_DEBIX) += \ + imx8mp-debix-model-a.dtb.o \ + imx8mp-debix-som-a-bmb-08.dtb.o lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \ imx6q-prti6q.dtb.o \ imx6q-prtwd2.dtb.o \ @@ -106,6 +115,8 @@ lwl-$(CONFIG_MACH_PROTONIC_STM32MP1) += \ stm32mp151-prtt1s.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK3) += rk3568-rock-3a.dtb.o +lwl-$(CONFIG_MACH_RADXA_ROCK5) += rk3588-rock-5b.dtb.o +lwl-$(CONFIG_MACH_RADXA_CM3) += rk3566-cm3-io.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o @@ -114,9 +125,9 @@ lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o -lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o +lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o bcm2711-rpi-400.dtb.o bcm2711-rpi-cm4-io.dtb.o bcm2711-rpi-cm4s-io.dtb.o lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o -lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o +lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o imx6dl-sabresd.dtb.o lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o @@ -130,24 +141,31 @@ lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingb imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o lwl-$(CONFIG_MACH_SKOV_IMX6) += imx6s-skov-imx6.dtb.o imx6dl-skov-imx6.dtb.o imx6q-skov-imx6.dtb.o +lwl-$(CONFIG_MACH_SKOV_IMX8MP) += imx8mp-skov.dtb.o lwl-$(CONFIG_MACH_SKOV_ARM9CPU) += at91-skov-arm9cpu.dtb.o lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o -lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o +lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o \ + stm32mp157c-dk2-scmi.dtb.o stm32mp157a-dk1-scmi.dtb.o lwl-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp135f-dk.dtb.o -lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o -lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o +lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o stm32mp157c-lxa-mc1-scmi.dtb.o +lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o stm32mp157c-ev1-scmi.dtb.o lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o -lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o -lwl-$(CONFIG_MACH_NXP_IMX8MN_EVK) += imx8mn-evk.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o imx8mm-evkb.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MN_EVK) += imx8mn-evk.dtb.o imx8mn-ddr4-evk.dtb.o lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o +lwl-$(CONFIG_MACH_INNOCOMM_WB15) += imx8mm-innocomm-wb15-evk.dtb.o +lwl-$(CONFIG_MACH_TQ_MBA8MPXL) += imx8mp-tqma8mpql-mba8mpxl.dtb.o lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o lwl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o -lwl-$(CONFIG_MACH_TQMA6UL) += imx6ul-mba6ulx.dtb.o +lwl-$(CONFIG_MACH_TQMA6UL) += imx6ul-tqma6ul2-mba6ulx.dtb.o \ + imx6ul-tqma6ul2l-mba6ulx.dtb.o \ + imx6ull-tqma6ull2-mba6ulx.dtb.o \ + imx6ull-tqma6ull2l-mba6ulx.dtb.o lwl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o lwl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o lwl-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o @@ -157,6 +175,7 @@ lwl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o lwl-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o lwl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o lwl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o +lwl-$(CONFIG_MACH_VARISCITE_SOM_MX7) += imx7d-gome-e143_01.dtb.o lwl-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o @@ -183,20 +202,31 @@ lwl-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-spb4.dtb.o \ vf610-zii-ssmb-dtu.dtb.o lwl-$(CONFIG_MACH_AC_SXB) += ac-sxb.dtb.o +lwl-$(CONFIG_MACH_CALAO) += \ + tny_a9260.dtb.o tny_a9g20.dtb.o \ + usb_a9260.dtb.o usb_a9g20.dtb.o lwl-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o lwl-$(CONFIG_MACH_SAMA5D3_XPLAINED) += at91-sama5d3_xplained.dtb.o lwl-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o +lwl-$(CONFIG_MACH_MICROCHIP_SAMA5D3_EDS) += at91-microchip-sama5d3-eds.dtb.o lwl-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o lwl-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o +lwl-$(CONFIG_MACH_SAMA5D4_WIFX) += at91-sama5d4_wifx_l1.dtb.o lwl-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o +lwl-$(CONFIG_MACH_XILINX_ZCU102) += zynqmp-zcu102-revA.dtb.o zynqmp-zcu102-revB.dtb.o lwl-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o lwl-$(CONFIG_MACH_XILINX_ZCU106) += zynqmp-zcu106-revA.dtb.o lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o +lwl-$(CONFIG_MACH_LS1028ARDB) += fsl-ls1028a-rdb.dtb.o lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o -lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o +lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb.o +lwl-$(CONFIG_MACH_LS1021AIOT) += fsl-ls1021a-iot.dtb.o lwl-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o lwl-$(CONFIG_MACH_MNT_REFORM) += imx8mq-mnt-reform2.dtb.o +lwl-$(CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP) += imx8mp-var-dart-dt8mcustomboard.dtb.o +lwl-$(CONFIG_MACH_TQMA93XX) += imx93-tqma9352-mba93xxca.dtb.o \ + imx93-tqma9352-mba93xxla.dtb.o -clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts index dff901f050..28a550aa84 100644 --- a/arch/arm/dts/am335x-baltos-minimal.dts +++ b/arch/arm/dts/am335x-baltos-minimal.dts @@ -45,6 +45,18 @@ }; &am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&dip_switch_pins>; + + dip_switch_pins: pinmux_dip_switch_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < 0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */ @@ -285,6 +297,10 @@ interrupts = <20 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; }; }; @@ -399,33 +415,40 @@ }; }; -&mac { +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { + status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; + phy1: ethernet-phy@1 { + reg = <7>; + eee-broken-100tx; + eee-broken-1000t; + }; }; -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; +&cpsw_port1 { phy-mode = "rmii"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; + fixed-link { + speed = <100>; + full-duplex; + }; }; -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; +&cpsw_port2 { + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; + phy-handle = <&phy1>; }; &mmc1 { @@ -438,3 +461,111 @@ &gpio0 { ti,no-reset-on-init; }; + +&gpio1 { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0_alt", + "SW2_1_alt", + "SW2_2_alt", + "SW2_3_alt", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; + +&gpio2 { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; + +&gpio3 { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "3G_PWR_EN", + "NC", + "NC", + "NC", + "NC", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 8711802f57..f6e24d73ae 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -6,4 +6,4 @@ * published by the Free Software Foundation. */ -#include <arm/am335x-bone-common.dtsi> +#include <arm/ti/omap/am335x-bone-common.dtsi> diff --git a/arch/arm/dts/am335x-myirtech-myd.dts b/arch/arm/dts/am335x-myirtech-myd.dts index 1ea0f2a440..647b71cca7 100644 --- a/arch/arm/dts/am335x-myirtech-myd.dts +++ b/arch/arm/dts/am335x-myirtech-myd.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include <arm/am335x-myirtech-myd.dts> +#include <arm/ti/omap/am335x-myirtech-myd.dts> / { aliases { @@ -19,36 +19,16 @@ device-path = &nand_environment; }; }; - }; -&nand0 { - /delete-node/ partition@0; - /delete-node/ partition@20000; - - nand_parts: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; - - partition@80000 { - label = "boot"; - reg = <0x80000 0x100000>; - }; - - nand_environment: partition@180000 { - label = "env"; - reg = <0x180000 0x40000>; - }; +&nand_parts { + nand_environment: partition@180000 { + label = "env"; + reg = <0x180000 0x40000>; + }; - partition@1c0000 { - label = "system"; - reg = <0x1c0000 0>; - }; + partition@1c0000 { + label = "system"; + reg = <0x1c0000 0>; }; }; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index e459824a77..a80f92f22c 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -4,7 +4,7 @@ environment-nand { compatible = "barebox,environment"; - device-path = &nand, "partname:bareboxenv"; + device-path = &env_nand; status = "disabled"; }; }; @@ -211,7 +211,7 @@ reg = <0x100000 0x80000>; }; - partition@180000 { + env_nand: partition@180000 { label = "bareboxenv"; reg = <0x180000 0x40000>; }; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index 4b2ff9b2ea..275e146fce 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -4,13 +4,13 @@ environment-spi { compatible = "barebox,environment"; - device-path = &flash, "partname:bareboxenv"; + device-path = &env_nor; status = "disabled"; }; environment-nand { compatible = "barebox,environment"; - device-path = &nand, "partname:bareboxenv"; + device-path = &env_nand; status = "disabled"; }; }; @@ -217,7 +217,7 @@ reg = <0x20000 0x80000>; }; - partition@a0000 { + env_nor: partition@a0000 { label = "bareboxenv"; reg = <0xa0000 0x20000>; }; @@ -333,7 +333,7 @@ reg = <0x100000 0x80000>; }; - partition@180000 { + env_nand: partition@180000 { label = "bareboxenv"; reg = <0x180000 0x40000>; }; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index 29776f4556..2de89f6058 100644 --- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -4,13 +4,13 @@ environment-spi { compatible = "barebox,environment"; - device-path = &flash, "partname:bareboxenv"; + device-path = &env_nor; status = "disabled"; }; environment-nand { compatible = "barebox,environment"; - device-path = &nand, "partname:bareboxenv"; + device-path = &env_nand; status = "disabled"; }; }; @@ -170,7 +170,7 @@ reg = <0x20000 0x80000>; }; - partition@a0000 { + env_nor: partition@a0000 { label = "bareboxenv"; reg = <0xa0000 0x20000>; }; @@ -312,7 +312,7 @@ reg = <0x100000 0x80000>; }; - partition@180000 { + env_nand: partition@180000 { label = "bareboxenv"; reg = <0x180000 0x40000>; }; diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index f1ee7b3c57..34764bb68e 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -7,7 +7,7 @@ * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ -#include <arm/am33xx.dtsi> +#include <arm/ti/omap/am33xx.dtsi> / { aliases { diff --git a/arch/arm/dts/am35xx-pfc-750_820x.dts b/arch/arm/dts/am35xx-pfc-750_820x.dts index 55c883944b..ad54be4dd6 100644 --- a/arch/arm/dts/am35xx-pfc-750_820x.dts +++ b/arch/arm/dts/am35xx-pfc-750_820x.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include <arm/am3517.dtsi> +#include <arm/ti/omap/am3517.dtsi> / { model = "Wago PFC200 (AM3505)"; diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts b/arch/arm/dts/armada-370-mirabox-bb.dts index 99263d4854..fcd72bda0e 100644 --- a/arch/arm/dts/armada-370-mirabox-bb.dts +++ b/arch/arm/dts/armada-370-mirabox-bb.dts @@ -3,11 +3,11 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/armada-370-mirabox.dts" +#include "arm/marvell/armada-370-mirabox.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-370-rn104-bb.dts b/arch/arm/dts/armada-370-rn104-bb.dts index 32f961e529..d59f00b9be 100644 --- a/arch/arm/dts/armada-370-rn104-bb.dts +++ b/arch/arm/dts/armada-370-rn104-bb.dts @@ -2,10 +2,10 @@ * Barebox specific DT overlay for Netgear ReadyNAS 104 */ -#include "arm/armada-370-netgear-rn104.dts" +#include "arm/marvell/armada-370-netgear-rn104.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-385-turris-omnia-bb.dts b/arch/arm/dts/armada-385-turris-omnia-bb.dts index 53bef01af7..ffea724ac4 100644 --- a/arch/arm/dts/armada-385-turris-omnia-bb.dts +++ b/arch/arm/dts/armada-385-turris-omnia-bb.dts @@ -1,7 +1,7 @@ -#include "arm/armada-385-turris-omnia.dts" +#include "arm/marvell/armada-385-turris-omnia.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-xp-db-bb.dts b/arch/arm/dts/armada-xp-db-bb.dts index 7201f4aaa1..68974de783 100644 --- a/arch/arm/dts/armada-xp-db-bb.dts +++ b/arch/arm/dts/armada-xp-db-bb.dts @@ -3,10 +3,10 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/armada-xp-db.dts" +#include "arm/marvell/armada-xp-db.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-xp-gp-bb.dts b/arch/arm/dts/armada-xp-gp-bb.dts index 3836016425..a863bd5bb1 100644 --- a/arch/arm/dts/armada-xp-gp-bb.dts +++ b/arch/arm/dts/armada-xp-gp-bb.dts @@ -3,10 +3,10 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/armada-xp-gp.dts" +#include "arm/marvell/armada-xp-gp.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts index b43bac37dd..5a883ecdc2 100644 --- a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts +++ b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts @@ -3,7 +3,7 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/armada-xp-lenovo-ix4-300d.dts" +#include "arm/marvell/armada-xp-lenovo-ix4-300d.dts" &{/gpio-leds/power-led} { linux,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts index e57cd8f0ce..b4a80388bc 100644 --- a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts +++ b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts @@ -3,10 +3,10 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/armada-xp-openblocks-ax3-4.dts" +#include "arm/marvell/armada-xp-openblocks-ax3-4.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/armada-xp-rn2120-bb.dts b/arch/arm/dts/armada-xp-rn2120-bb.dts index 969136b336..30bf4f6229 100644 --- a/arch/arm/dts/armada-xp-rn2120-bb.dts +++ b/arch/arm/dts/armada-xp-rn2120-bb.dts @@ -2,10 +2,10 @@ * Barebox specific DT overlay for Netgear ReadyNAS 2120 */ -#include "arm/armada-xp-netgear-rn2120.dts" +#include "arm/marvell/armada-xp-netgear-rn2120.dts" / { chosen { - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; }; diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb.dts b/arch/arm/dts/at91-microchip-ksz9477-evb.dts index 3762361b53..9c2f6d97a6 100644 --- a/arch/arm/dts/at91-microchip-ksz9477-evb.dts +++ b/arch/arm/dts/at91-microchip-ksz9477-evb.dts @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; -#include <arm/at91-sama5d3_ksz9477_evb.dts> +#include <arm/microchip/at91-sama5d3_ksz9477_evb.dts> #include "sama5d3.dtsi" / { @@ -13,10 +13,6 @@ }; }; -&{/memory@20000000} { - reg = <0x20000000 0x10000000>; -}; - ®_vcc_mmc0 { status = "disabled"; }; diff --git a/arch/arm/dts/at91-microchip-sama5d3-eds.dts b/arch/arm/dts/at91-microchip-sama5d3-eds.dts new file mode 100644 index 0000000000..d35c8c3c6e --- /dev/null +++ b/arch/arm/dts/at91-microchip-sama5d3-eds.dts @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/dts-v1/; +#include <arm/microchip/at91-sama5d3_eds.dts> +#include "sama5d3.dtsi" + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &mmc0, "partname:0"; + file-path = "barebox.env"; + }; + }; +}; diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts index 99fc5a8d4d..3aa28ed501 100644 --- a/arch/arm/dts/at91-sama5d27_giantboard.dts +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -11,8 +11,8 @@ /dts-v1/; -#include <arm/sama5d2.dtsi> -#include <arm/sama5d2-pinfunc.h> +#include <arm/microchip/sama5d2.dtsi> +#include <arm/microchip/sama5d2-pinfunc.h> #include <dt-bindings/mfd/atmel-flexcom.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/active-semi,8945a-regulator.h> diff --git a/arch/arm/dts/at91-sama5d27_som1.dtsi b/arch/arm/dts/at91-sama5d27_som1.dtsi index 0d84c45f92..357f46e309 100644 --- a/arch/arm/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/dts/at91-sama5d27_som1.dtsi @@ -7,7 +7,7 @@ nvmem-cell-names = "mac-address"; }; -&{/ahb/apb/i2c@f8028000/at24@50} { +&{i2c0/at24@50} { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index 1a704b4268..44e6305449 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -3,7 +3,7 @@ * Copyright (C) 2019 Oleksij Rempel - Pengutronix */ -#include <arm/at91-sama5d27_som1_ek.dts> +#include <arm/microchip/at91-sama5d27_som1_ek.dts> #include "at91-sama5d27_som1.dtsi" / { @@ -30,9 +30,8 @@ }; }; +/delete-node/ &{qspi1/flash@0}; &qspi1 { - /delete-node/ flash@0; - flash@0 { compatible = "jedec,spi-nor"; reg = <0>; diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts index cdb29ca666..de47ede7c6 100644 --- a/arch/arm/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/dts/at91-sama5d3_xplained.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include <arm/at91-sama5d3_xplained.dts> +#include <arm/microchip/at91-sama5d3_xplained.dts> #include "sama5d3.dtsi" / { @@ -19,32 +19,3 @@ }; }; }; - -/* Will be automatically read back from HW */ -/delete-node/ &{/memory@20000000}; - -&nand_controller { - nand@3 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x60000000 0x01000000 /* EBI CS3 */ - 0xffffc070 0x00000490 /* SMC PMECC regs */ - 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ - 0x00110000 0x00018000 /* ROM code */ - >; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand0_ale_cle>; - atmel,pmecc-lookup-table-offset = <0x10000 0x8000>; - - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - status = "okay"; - }; -}; - diff --git a/arch/arm/dts/at91-sama5d4_wifx_l1.dts b/arch/arm/dts/at91-sama5d4_wifx_l1.dts new file mode 100644 index 0000000000..91c8073343 --- /dev/null +++ b/arch/arm/dts/at91-sama5d4_wifx_l1.dts @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// SPDX-FileCopyrightText: 2021 Wifx +// SPDX-FileCopyrightText: 2021 Yannick Lanz <yannick.lanz@wifx.net> +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix + +/dts-v1/; + +#include <arm/microchip/sama5d4.dtsi> +#include "sama5d4.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Wifx L1"; + compatible = "wifx,l1", "atmel,sama5d4", "atmel,sama5"; + + chosen { + stdout-path = &usart3; + + environment-microsd { + compatible = "barebox,environment"; + device-path = &mmc1; + file-path = "barebox.env"; + status = "disabled"; + }; + + environment-nand { + compatible = "barebox,environment"; + device-path = &env_nand; + status = "disabled"; + }; + }; + + aliases { + rtc0 = &ds1339; + rtc1 = &rtc_internal; + serial1 = &usart1; + serial4 = &usart4; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + status_internal { + gpios = <&pioE 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gnss_pps>; + + gpios = <&pioC 24 GPIO_ACTIVE_HIGH>; + /* assert-falling-edge; */ + }; + + vddbu_2v_reg: regulator-vddbu-2v { + compatible = "regulator-fixed"; + regulator-name = "VDDBU_2V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&spi0 { + status = "okay"; + cs-gpios = <&pioC 3 GPIO_ACTIVE_HIGH>; + + sx1302@0 { + compatible = "semtech,sx1301"; + spi-max-frequency = <10000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + i2c-digital-filter; + i2c-analog-filter; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-digital-filter; + i2c-analog-filter; + + stts751: temp_sensor@38 { + compatible = "stts751"; + reg = <0x38>; + }; + + m24c08: eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + + mac_at24mac402: eeprom@58 { + compatible = "atmel,24mac402"; + reg = <0x58>; + #address-cells = <1>; + #size-cells = <1>; + + ethaddr: mac-address@9a { + reg = <0x9a 6>; + }; + }; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-resistor-ohms = <250>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + i2c-digital-filter; + i2c-analog-filter; + + ec@2a { + compatible = "wifx,wgw-ec-i2c"; + reg = <0x2a>; + + interrupt-parent = <&pioE>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_irq &pinctrl_mcu_cpu_state>; + + cpu-state-gpios = <&pioA 19 0>; + + usb_typec: usbc { + compatible = "wifx,wgw-ec-usbc"; + #trigger-source-cells = <0>; + }; + + leds { + compatible = "wifx,wgw-ec-leds"; + #address-cells = <1>; + #size-cells = <0>; + + statusled { + reg = <0>; + label = "status"; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + + serviceled { + reg = <1>; + label = "service"; + max-brightness = <255>; + linux,default-trigger = "wgw-usbc-data-mode"; + trigger-sources = <&usb_typec>; + }; + }; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + nvmem-cells = <ðaddr>; + nvmem-cell-names = "mac-address"; + status = "okay"; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioA>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; +}; + +&usart1 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-0 = <&pinctrl_usart1>; + status = "okay"; +}; + +&usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&tcb0 { + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +/* disable unused TCBs */ +&tcb1 { + status = "disabled"; +}; + +&tcb2 { + status = "disabled"; +}; + +&watchdog { + status = "okay"; +}; + +rtc_internal: &{/ahb/apb/rtc@fc0686b0} { + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + atmel,id-gpio = <&pioD 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 0 0 >; + atmel,id-gpio = <&pioD 11 GPIO_ACTIVE_HIGH 0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_id>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe + &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy + &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "uboot"; + reg = <0x40000 0xC0000>; + }; + + env_nand: uboot-env@100000 { + label = "uboot-env"; + reg = <0x100000 0x80000>; + }; + + ubi@180000 { + label = "ubi"; + reg = <0x180000 0x3FE00000>; + }; + }; + }; +}; + +&pinctrl { + board { + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_usb_vbus: usb_vbus { + atmel,pins = <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_usb_id: usb_id { + atmel,pins = <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_mcu_irq: mcu_irq_0 { + atmel,pins = <AT91_PIOE 27 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_mcu_cpu_state: mcu_cpu_state { + atmel,pins = <AT91_PIOA 19 AT91_PERIPH_GPIO (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(1))>; + }; + pinctrl_macb0_phy_irq: macb0_phy_irq_0 { + atmel,pins = <AT91_PIOA 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_sx130x_rst: sx130x_rst { + atmel,pins = <AT91_PIOA 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_rf_front_pwr_en: rf_front_pwr_en { + atmel,pins = <AT91_PIOA 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_ext_rst: ext_rst { + atmel,pins = <AT91_PIOA 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_ext_pwr_en: ext_pwr_en { + atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; + }; + pinctrl_ext_boot_n: ext_boot_n { + atmel,pins = <AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_ext_wake: ext_wake { + atmel,pins = <AT91_PIOA 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_gnss_pps: gnss_pps { + atmel,pins = <AT91_PIOC 24 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + }; +}; diff --git a/arch/arm/dts/at91-skov-arm9cpu.dts b/arch/arm/dts/at91-skov-arm9cpu.dts index 8e4fddfd3f..d04d031f40 100644 --- a/arch/arm/dts/at91-skov-arm9cpu.dts +++ b/arch/arm/dts/at91-skov-arm9cpu.dts @@ -8,7 +8,7 @@ /dts-v1/; -#include "arm/at91sam9263.dtsi" +#include <arm/microchip/at91sam9263.dtsi> / { model = "SKOV ARM9 CPU"; @@ -17,9 +17,10 @@ chosen { stdout-path = "serial0:115200n8"; - environment { + environment-sd { compatible = "barebox,environment"; - device-path = &environment_nor; + device-path = &mmc1; + file-path = "barebox.env"; }; }; @@ -36,12 +37,12 @@ #address-cells = <1>; #size-cells = <1>; - barebox@0 { + u-boot@0 { label = "bootloader"; reg = <0x00000 0x80000>; }; - environment_nor: env@80000 { + env@80000 { label = "environment"; reg = <0x80000 0x20000>; }; @@ -204,13 +205,11 @@ }; }; -&{/ahb/apb} { - pinctrl: pinctrl@fffff200 { - }; +pinctrl: &{/ahb/apb/pinctrl@fffff200} { +}; - watchdog@fffffd40 { +&{/ahb/apb/watchdog@fffffd40} { status = "okay"; - }; }; &dbgu { diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi new file mode 100644 index 0000000000..828ab6646e --- /dev/null +++ b/arch/arm/dts/at91sam9260.dtsi @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +&ebi { + status = "disabled"; +}; + +&nand_controller { + status = "disabled"; +}; + +&{/ahb/apb} { + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe800 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; +}; + +&usb0 { /* currently hangs with DT-enabled driver */ + status = "disabled"; +}; diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts index 29a615f482..77da4479ab 100644 --- a/arch/arm/dts/at91sam9263ek.dts +++ b/arch/arm/dts/at91sam9263ek.dts @@ -1,4 +1,4 @@ -#include <arm/at91sam9263ek.dts> +#include <arm/microchip/at91sam9263ek.dts> / { chosen { environment { @@ -9,39 +9,37 @@ }; -&nand_controller { - nand@3 { - /delete-node/ partitions; +&{nand_controller/nand@3} { + /delete-node/ partitions; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x100000>; - }; + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x100000>; + }; - environment_nand: bareboxenv@120000 { - label = "barebox-environment"; - reg = <0x120000 0x20000>; - }; + environment_nand: bareboxenv@120000 { + label = "barebox-environment"; + reg = <0x120000 0x20000>; + }; - rootfs@140000 { - label = "root"; - reg = <0x140000 0x0>; - }; + rootfs@140000 { + label = "root"; + reg = <0x140000 0x0>; }; }; }; -&{/ahb/apb/mmc@fff84000} { +&mmc1 { pinctrl-0 = < &pinctrl_board_mmc1 &pinctrl_mmc1_clk diff --git a/arch/arm/dts/at91sam9g20.dtsi b/arch/arm/dts/at91sam9g20.dtsi new file mode 100644 index 0000000000..b8301a8ce7 --- /dev/null +++ b/arch/arm/dts/at91sam9g20.dtsi @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include "at91sam9260.dtsi" diff --git a/arch/arm/dts/at91sam9x5ek.dts b/arch/arm/dts/at91sam9x5ek.dts index 3a6976a7d9..e25fb182cf 100644 --- a/arch/arm/dts/at91sam9x5ek.dts +++ b/arch/arm/dts/at91sam9x5ek.dts @@ -3,11 +3,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/at91.h> -#include <arm/at91sam9x5.dtsi> -#include <arm/at91sam9x5_macb0.dtsi> -#include <arm/at91sam9x5_lcd.dtsi> -#include <arm/at91sam9x5dm.dtsi> -#include <arm/at91sam9x5ek.dtsi> +#include <arm/microchip/at91sam9x5.dtsi> +#include <arm/microchip/at91sam9x5_macb0.dtsi> +#include <arm/microchip/at91sam9x5_lcd.dtsi> +#include <arm/microchip/at91sam9x5dm.dtsi> +#include <arm/microchip/at91sam9x5ek.dtsi> / { aliases { diff --git a/arch/arm/dts/bcm2711-rpi-4.dts b/arch/arm/dts/bcm2711-rpi-4.dts index 3c0caa73f8..6d46dd3b83 100644 --- a/arch/arm/dts/bcm2711-rpi-4.dts +++ b/arch/arm/dts/bcm2711-rpi-4.dts @@ -1,18 +1,4 @@ -#include <arm64/broadcom/bcm2711-rpi-4-b.dts> - -&{/memory@0} { - reg = <0x0 0x0 0x0>; -}; +// SPDX-License-Identifier: GPL-2.0 -&sdhci { - /* no use for SDIO WiFi in barebox */ - status = "disabled"; -}; - -&uart1 { - /* VPU core clock is reported at 200MHz, but needs to be 500Mhz - * for ns16550 driver to set correct baudrate. Until that's - * figured out, hardcode clock frequency to the expected value - */ - clock-frequency = <500000000>; -}; +#include <arm64/broadcom/bcm2711-rpi-4-b.dts> +#include "bcm2711-rpi.dtsi" diff --git a/arch/arm/dts/bcm2711-rpi-400.dts b/arch/arm/dts/bcm2711-rpi-400.dts new file mode 100644 index 0000000000..fb9cccb2b9 --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi-400.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <arm64/broadcom/bcm2711-rpi-400.dts> +#include "bcm2711-rpi.dtsi" diff --git a/arch/arm/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/dts/bcm2711-rpi-cm4-io.dts new file mode 100644 index 0000000000..115491e7a6 --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi-cm4-io.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <arm64/broadcom/bcm2711-rpi-cm4-io.dts> +#include "bcm2711-rpi.dtsi" diff --git a/arch/arm/dts/bcm2711-rpi-cm4s-io.dts b/arch/arm/dts/bcm2711-rpi-cm4s-io.dts new file mode 100644 index 0000000000..8302523e47 --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi-cm4s-io.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "bcm2711-rpi-cm4-io.dts" + +&{/memory@0} { + reg = <0x0 0x0 0x0>; +}; + +/ { + compatible = "raspberrypi,4-compute-module-s", "brcm,bcm2711"; + model = "Raspberry Pi Compute Module 4S IO Board"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart1 { + /delete-property/ clock-frequency; +}; diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi new file mode 100644 index 0000000000..cb2952ccac --- /dev/null +++ b/arch/arm/dts/bcm2711-rpi.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +&{/memory@0} { + reg = <0x0 0x0 0x0>; +}; + +&uart1 { + /* VPU core clock is reported at 200MHz, but needs to be 500Mhz + * for ns16550 driver to set correct baudrate. Until that's + * figured out, hardcode clock frequency to the expected value + */ + clock-frequency = <500000000>; +}; diff --git a/arch/arm/dts/bcm2835-rpi.dts b/arch/arm/dts/bcm2835-rpi.dts index 8d352a457d..ed03a369bd 100644 --- a/arch/arm/dts/bcm2835-rpi.dts +++ b/arch/arm/dts/bcm2835-rpi.dts @@ -1,4 +1,4 @@ -#include <arm/bcm2835-rpi-a.dts> +#include <arm/broadcom/bcm2835-rpi-a.dts> &{/aliases} { usb0 = &usb; diff --git a/arch/arm/dts/bcm2836-rpi-2.dts b/arch/arm/dts/bcm2836-rpi-2.dts index c9106515ee..783128a549 100644 --- a/arch/arm/dts/bcm2836-rpi-2.dts +++ b/arch/arm/dts/bcm2836-rpi-2.dts @@ -1,4 +1,4 @@ -#include <arm/bcm2836-rpi-2-b.dts> +#include <arm/broadcom/bcm2836-rpi-2-b.dts> &{/memory@0} { reg = <0x0 0x0>; diff --git a/arch/arm/dts/bcm2837-rpi-3.dts b/arch/arm/dts/bcm2837-rpi-3.dts index e82d518fa5..38d673aec4 100644 --- a/arch/arm/dts/bcm2837-rpi-3.dts +++ b/arch/arm/dts/bcm2837-rpi-3.dts @@ -3,7 +3,3 @@ &{/memory@0} { reg = <0x0 0x0>; }; - -&sdhci { - status = "disabled"; -}; diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dts b/arch/arm/dts/bcm2837-rpi-cm3.dts index 85a6ac4661..340fc58882 100644 --- a/arch/arm/dts/bcm2837-rpi-cm3.dts +++ b/arch/arm/dts/bcm2837-rpi-cm3.dts @@ -1,4 +1,4 @@ -#include <arm/bcm2837-rpi-cm3-io3.dts> +#include <arm/broadcom/bcm2837-rpi-cm3-io3.dts> / { chosen { diff --git a/arch/arm/dts/calao_nand.dtsi b/arch/arm/dts/calao_nand.dtsi new file mode 100644 index 0000000000..e42d6cdc8c --- /dev/null +++ b/arch/arm/dts/calao_nand.dtsi @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +&nand0 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; +}; diff --git a/arch/arm/dts/digic4.dtsi b/arch/arm/dts/digic4.dtsi index 2db9393b33..051d8aad44 100644 --- a/arch/arm/dts/digic4.dtsi +++ b/arch/arm/dts/digic4.dtsi @@ -31,14 +31,14 @@ * Assume that DIGIC4 has at least 96 pins. * So resource size is 96 * 4 = 0x180. */ - gpio: gpio { + gpio: gpio@c0220000 { compatible = "canon,digic-gpio"; reg = <0xc0220000 0x180>; #gpio-cells = <2>; gpio-controller; }; - uart: uart { + uart: uart@c0800000 { compatible = "canon,digic-uart"; reg = <0xc0800000 0x1c>; }; diff --git a/arch/arm/dts/dove-cubox-bb.dts b/arch/arm/dts/dove-cubox-bb.dts index 06966d9c2e..5b93bfd1a0 100644 --- a/arch/arm/dts/dove-cubox-bb.dts +++ b/arch/arm/dts/dove-cubox-bb.dts @@ -3,7 +3,7 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/dove-cubox.dts" +#include "arm/marvell/dove-cubox.dts" / { chosen { @@ -11,6 +11,6 @@ }; }; -&{/leds/power} { +&{/leds/led-power} { barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/ep7212-clep7212.dts b/arch/arm/dts/ep7212-clep7212.dts index 84c5e79548..37a9399464 100644 --- a/arch/arm/dts/ep7212-clep7212.dts +++ b/arch/arm/dts/ep7212-clep7212.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Author: Alexander Shiyan <shc_work@mail.ru> */ -#include <arm/ep7211.dtsi> +#include <arm/cirrus/ep7211.dtsi> / { model = "Cirrus Logic EP7212"; @@ -17,7 +17,7 @@ environment { compatible = "barebox,environment"; - device-path = &flash, "partname:env"; + device-path = &env_nor; }; }; }; @@ -30,7 +30,7 @@ /* CS3 = WAITSTATE_7_1 | BUS_WIDTH_32 */ barebox,ep7209-memcfg1 = <0x25802b28>; - flash: nor@0,0 { + flash: nor@0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; @@ -45,7 +45,7 @@ reg = <0x00000 0x80000>; }; - partition@80000 { + env_nor: partition@80000 { label = "env"; reg = <0x80000 0x40000>; }; diff --git a/arch/arm/dts/fsl-ls1021a-iot.dts b/arch/arm/dts/fsl-ls1021a-iot.dts new file mode 100644 index 0000000000..47eebcb6a9 --- /dev/null +++ b/arch/arm/dts/fsl-ls1021a-iot.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include <arm/nxp/ls/ls1021a-iot.dts> + +/ { + chosen { + stdout-path = &uart0; + + environment { + compatible = "barebox,environment"; + device-path = &environment_qspi; + }; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + s70fl01gs: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "fixed-partitions"; + + partition@0 { + label = "barebox"; + reg = <0 0x100000>; + }; + + environment_qspi: partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x40000>; + }; + }; + }; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + +/* I2C1 and I2C2 are connected due to Errata on rev1 board */ +&i2c2 { + status = "disabled"; +}; + +&uart0 { + status = "okay"; + clock-frequency = <150000000>; +}; + +&uart1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts new file mode 100644 index 0000000000..671c97413b --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/freescale/fsl-ls1028a-rdb.dts> +#include "fsl-ls1028a.dtsi" + +/ { + chosen { + environment-sd { + status = "disabled"; + compatible = "barebox,environment"; + device-path = &part_env_sd; + }; + + environment-emmc { + status = "disabled"; + compatible = "barebox,environment"; + device-path = &part_env_emmc; + }; + }; + + memory@80000000 { + /* Upstream dts has size 4GiB here which is wrong */ + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +/* SD */ +&esdhc { + #address-cells = <1>; + #size-cells = <1>; + + partition@1000 { + label = "barebox"; + reg = <0x1000 0x1df000>; + }; + + part_env_sd: partition@1e0000 { + label = "barebox-environment"; + reg = <0x1e0000 0x20000>; + }; +}; + +/* eMMC */ +&esdhc1 { + #address-cells = <1>; + #size-cells = <1>; + + partition@1000 { + label = "barebox"; + reg = <0x1000 0x1df000>; + }; + + part_env_emmc: partition@1e0000 { + label = "barebox-environment"; + reg = <0x1e0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi new file mode 100644 index 0000000000..a15a219cfa --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,7 @@ + +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index d842387fa0..37023fae9b 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -3,11 +3,11 @@ /dts-v1/; #include <arm64/freescale/fsl-ls1046a-rdb.dts> +#include "fsl-ls1046a.dtsi" / { aliases { - eeprom = &eeprom; - mmc0 = &esdhc; + eeprom = &{i2c0/eeprom@52}; }; chosen { @@ -47,17 +47,6 @@ status = "okay"; }; -&i2c0 { - eeprom: eeprom@52 { - compatible = "atmel,24c04"; - }; - - non_existent_eeprom: eeprom@53 { - }; -}; - -/delete-node/ &non_existent_eeprom; - &enet0 { status = "disabled"; }; @@ -74,35 +63,35 @@ phy-mode = "rgmii-id"; }; -&{/soc/fman@1a00000/mdio@e1000} { +&{fman0/mdio@e1000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@e3000} { +&{fman0/mdio@e3000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@e5000} { +&{fman0/mdio@e5000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@e7000} { +&{fman0/mdio@e7000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@e9000} { +&{fman0/mdio@e9000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@eb000} { +&{fman0/mdio@eb000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@f1000} { +&{fman0/mdio@f1000} { status = "disabled"; }; -&{/soc/fman@1a00000/mdio@f3000} { +&{fman0/mdio@f3000} { status = "disabled"; }; @@ -120,14 +109,14 @@ dr_mode = "host"; }; -&{/soc/pcie@3400000} { +&pcie1 { status = "okay"; }; -&{/soc/pcie@3500000} { +&pcie2 { status = "okay"; }; -&{/soc/pcie@3600000} { +&pcie3 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts new file mode 100644 index 0000000000..787a85394c --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for TQMLS1046A SoM on MBLS10xxA from TQ + */ + +/dts-v1/; + +#include <arm64/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts> +#include "fsl-ls1046a.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &environment_sd; + status = "disabled"; + }; + + environment-qspi { + compatible = "barebox,environment"; + device-path = &environment_qspi; + status = "disabled"; + }; + }; +}; + +&esdhc { + partitions { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "fixed-partitions"; + + partition@1000 { + label = "barebox"; + reg = <0x1000 0xdf000>; + }; + + environment_sd: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + }; +}; + +&qflash0 { + partitions { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "fixed-partitions"; + + partition@0 { + label = "barebox"; + reg = <0x0 0x200000>; + }; + + environment_qspi: partition@200000 { + label = "barebox-environment"; + reg = <0x200000 0x80000>; + }; + + partition@280000 { + label = "data"; + reg = <0x280000 0x0>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi new file mode 100644 index 0000000000..a661cb0c89 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + aliases { + mmc0 = &esdhc; + }; +}; diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts deleted file mode 100644 index 7f9a764a82..0000000000 --- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for TQMLS1046A SoM on MBLS10xxA from TQ - * - * Copyright 2018 TQ-Systems GmbH - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -#include "fsl-tqmls1046a.dtsi" - -/ { - model = "TQ TQMLS1046A SoM on MBLS10xxA board"; - compatible = "tqc,tqmls1046a", "fsl,ls1046a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - mmc0 = &esdhc; - qspiflash0 = &qflash0; - qspiflash1 = &qflash1; - qsgmii_s1_p1 = &qsgmii1_phy1; - qsgmii_s1_p2 = &qsgmii1_phy2; - qsgmii_s2_p1 = &qsgmii2_phy1; - qsgmii_s2_p2 = &qsgmii2_phy2; - qsgmii_s2_p3 = &qsgmii2_phy3; - qsgmii_s2_p4 = &qsgmii2_phy4; - }; - - chosen { - stdout-path = "serial1:115200n8"; - - environment-sd { - compatible = "barebox,environment"; - device-path = &environment_sd; - status = "disabled"; - }; - - environment-qspi { - compatible = "barebox,environment"; - device-path = &environment_qspi; - status = "disabled"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - gpio-keys,name = "gpio-keys"; - poll-interval = <100>; - autorepeat; - - button0 { - label = "button0"; - gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>; - linux,code = <KEY_F1>; - }; - - button1 { - label = "button1"; - gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>; - linux,code = <KEY_F2>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>; - label = "led:user"; - linux,default-trigger = "heartbeat"; - }; - }; - -}; - -&esdhc { - partitions { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "fixed-partitions"; - - partition@1000 { - label = "barebox"; - reg = <0x1000 0xdf000>; - }; - - environment_sd: partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - mmc-hs200-1_8v; - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; -}; - -&i2c3 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9544"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - gpioexp1: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "sd1_3_lane_a_mux", - "sd1_2_lane_b_mux", - "sd1_0_lane_d_mux", - "sd2_1_lane_b_mux", - "sd2_3_lane_d_mux1", - "sd2_3_lane_d_mux2", - "sd_mux_shdn", - "sd1_ref_clk2_sel", - "mpcie1_disable_n", - "mpcie1_wake_n", - "mpcie2_disable_n", - "mpcie2_wake_n", - "prsnt_n", - "pcie_pwr_en", - "dcdc_pwr_en", - "dcdc_pgood_1v8"; - }; - - gpioexp2: pca9555@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "xfi1_tx_dis", - "xfi1_tx_fault", - "xfi1_moddef_det", - "xfi1_rx_loss", - "retimer1_loss", - "xfi1_ensmb", - "qsgmii1_clk_sel0", - "qsgmii_phy1_config3", - "xfi2_tx_fault", - "xfi2_tx_dis", - "xfi2_moddef_det", - "xfi2_rx_loss", - "retimer2_loss", - "xfi2_ensmb", - "qsgmii2_clk_sel0", - "qsgmii_phy2_config3"; - }; - - gpioexp3: pca9555@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "ec1_phy_pwdn", - "ec2_phy_pwdn", - "usb_c_pwron", - "usb_en_oc_3v3_n", - "usb_h_grst_n", - "gpio_button0", - "gpio_button1", - "sda_pwr_en", - "qsgmii_phy1_int_n", - "qsgmii_phy2_int_n", - "spi_clko_sof", - "spi_int", - "can_sel", - "led_n", - "pcie_rst_3v3_n", - "pcie_wake_3v3_n"; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - }; -}; - -&usb1 { - dr_mode = "otg"; -}; - -#include <arm64/freescale/fsl-ls1046-post.dtsi> -#include <dt-bindings/net/ti-dp83867.h> - -&fman0 { - status = "okay"; -}; - -&enet0 { /* EMAC.1 */ - phy-connection-type = "sgmii"; -}; - -&enet1 { /* EMAC.2 */ - phy-connection-type = "sgmii"; -}; - -&enet2 { /* EMAC.3 */ - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii"; - phy-mode = "rgmii-id"; -}; - -&enet3 { /* EMAC.4 */ - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii"; - phy-mode = "rgmii-id"; -}; - -&enet4 { /* EMAC.5 */ - phy-connection-type = "sgmii"; -}; - -&enet5 { /* EMAC.6 */ - phy-connection-type = "sgmii"; -}; - -&enet6 { /* EMAC.9 */ - phy-connection-type = "sgmii"; -}; - -&enet7 { /* EMAC.10 */ - phy-connection-type = "sgmii"; -}; - -&{/soc/fman@1a00000/mdio@e1000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@e3000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@e5000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@e7000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@e9000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@eb000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@f1000} { - status = "disabled"; -}; - -&{/soc/fman@1a00000/mdio@f3000} { - status = "disabled"; -}; - -&mdio0 { - rgmii_phy1: ethernet-phy@0e { - reg = <0x0e>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - }; - - rgmii_phy2: ethernet-phy@0c { - reg = <0x0c>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - }; - - qsgmii1_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; - - qsgmii1_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; - - qsgmii2_phy1: ethernet-phy@00 { - reg = <0x00>; - }; - - qsgmii2_phy2: ethernet-phy@01 { - reg = <0x01>; - }; - - qsgmii2_phy3: ethernet-phy@02 { - reg = <0x02>; - }; - - qsgmii2_phy4: ethernet-phy@03 { - reg = <0x03>; - }; -}; - -&xmdio0 { - status = "disabled"; -}; - -&qflash0 { - partitions { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "fixed-partitions"; - - partition@0 { - label = "barebox"; - reg = <0x0 0x200000>; - }; - - environment_qspi: partition@200000 { - label = "barebox-environment"; - reg = <0x200000 0x80000>; - }; - - partition@280000 { - label = "data"; - reg = <0x280000 0x0>; - }; - }; -}; diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi deleted file mode 100644 index 0ea2612cbf..0000000000 --- a/arch/arm/dts/fsl-tqmls1046a.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for LS1046A based SoM of TQ - * - * Copyright 2018 TQ-Systems GmbH - */ - -#include <arm64/freescale/fsl-ls1046a.dtsi> - -&i2c0 { - status = "okay"; - - temp-sensor@18 { - compatible = "jc42"; - reg = <0x18>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - rtc@51 { - compatible = "nxp,pcf85063"; - reg = <0x51>; - }; - - eeprom@57 { - compatible = "atmel,24c256"; - reg = <0x57>; - }; -}; - -&qspi { - num-cs = <2>; - bus-num = <0>; - status = "okay"; - - qflash0: mx66u51235f@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <62500000>; - reg = <0>; - }; - - qflash1: mx66u51235f@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <62500000>; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/imx1-scb9328.dts b/arch/arm/dts/imx1-scb9328.dts index aac82d0afd..bcc1598e3b 100644 --- a/arch/arm/dts/imx1-scb9328.dts +++ b/arch/arm/dts/imx1-scb9328.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include <arm/imx1.dtsi> +#include <arm/nxp/imx/imx1.dtsi> / { model = "Synertronix scb9328"; diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts index 2785a3c91a..9de8c5a841 100644 --- a/arch/arm/dts/imx25-karo-tx25.dts +++ b/arch/arm/dts/imx25-karo-tx25.dts @@ -9,14 +9,14 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx25-karo-tx25.dts> +#include <arm/nxp/imx/imx25-karo-tx25.dts> #include "imx25.dtsi" / { chosen { environment { compatible = "barebox,environment"; - device-path = &nfc, "partname:environment"; + device-path = &env_nand; }; }; }; @@ -34,7 +34,7 @@ reg = <0x0 0x80000>; }; - partition@80000 { + env_nand: partition@80000 { label = "environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts index abfbd5061e..d9ba6abae6 100644 --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts @@ -2,7 +2,7 @@ * Barebox specific DT overlay for Phytec PCA100 RDK */ -#include <arm/imx27-phytec-phycard-s-rdk.dts> +#include <arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts> / { chosen { @@ -10,7 +10,7 @@ environment { compatible = "barebox,environment"; - device-path = &nfc, "partname:environment"; + device-path = &env_nand; }; }; }; @@ -21,7 +21,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nand: partition@e0000 { label = "environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/dts/imx27-phytec-phycore-rdk.dts index fff154cb97..04f037bab8 100644 --- a/arch/arm/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/dts/imx27-phytec-phycore-rdk.dts @@ -2,7 +2,7 @@ * Barebox specific DT overlay for Phytec PCM-970 RDK */ -#include <arm/imx27-phytec-phycore-rdk.dts> +#include <arm/nxp/imx/imx27-phytec-phycore-rdk.dts> / { chosen { diff --git a/arch/arm/dts/imx28-duckbill.dts b/arch/arm/dts/imx28-duckbill.dts index 2a995a7938..31e6f43a22 100644 --- a/arch/arm/dts/imx28-duckbill.dts +++ b/arch/arm/dts/imx28-duckbill.dts @@ -1,4 +1,4 @@ -#include <arm/imx28-duckbill.dts> +#include <arm/nxp/mxs/imx28-duckbill.dts> / { chosen { diff --git a/arch/arm/dts/imx28-evk.dts b/arch/arm/dts/imx28-evk.dts index c82dfa4d8c..15159f2d98 100644 --- a/arch/arm/dts/imx28-evk.dts +++ b/arch/arm/dts/imx28-evk.dts @@ -1,4 +1,4 @@ -#include <arm/imx28-evk.dts> +#include <arm/nxp/mxs/imx28-evk.dts> / { chosen { @@ -6,7 +6,7 @@ environment { compatible = "barebox,environment"; - device-path = &gpmi, "partname:environment"; + device-path = &env_nand; }; }; }; @@ -21,7 +21,7 @@ reg = <0x0 0x80000>; }; - partition@80000 { + env_nand: partition@80000 { label = "environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/dts/imx50.dtsi b/arch/arm/dts/imx50.dtsi index b5def2e4f6..e0fe104302 100644 --- a/arch/arm/dts/imx50.dtsi +++ b/arch/arm/dts/imx50.dtsi @@ -1,6 +1,6 @@ -#include <arm/imx50.dtsi> +#include <arm/nxp/imx/imx50.dtsi> -&{/soc/bus@50000000} { /* AIPS1 */ +&aips1 { usbphy1: usbphy@1 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts index f85415f6db..bd8ef0c06a 100644 --- a/arch/arm/dts/imx51-babbage.dts +++ b/arch/arm/dts/imx51-babbage.dts @@ -10,7 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx51-babbage.dts> +#include <arm/nxp/imx/imx51-babbage.dts> / { chosen { diff --git a/arch/arm/dts/imx51-ccxmx51.dts b/arch/arm/dts/imx51-ccxmx51.dts index efe5dbf631..d553644730 100644 --- a/arch/arm/dts/imx51-ccxmx51.dts +++ b/arch/arm/dts/imx51-ccxmx51.dts @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* Author: Alexander Shiyan <shc_work@mail.ru> */ -#include <arm/imx51-digi-connectcore-jsk.dts> +#include <arm/nxp/imx/imx51-digi-connectcore-jsk.dts> / { chosen { @@ -9,7 +9,7 @@ environment { compatible = "barebox,environment"; - device-path = &nfc, "partname:env"; + device-path = &env_nand; }; }; }; @@ -24,7 +24,7 @@ reg = <0x00000 0x80000>; }; - partition@80000 { + env_nand: partition@80000 { label = "env"; reg = <0x80000 0x40000>; }; diff --git a/arch/arm/dts/imx51-genesi-efika-sb.dts b/arch/arm/dts/imx51-genesi-efika-sb.dts index 7e3017f981..1d8183fff1 100644 --- a/arch/arm/dts/imx51-genesi-efika-sb.dts +++ b/arch/arm/dts/imx51-genesi-efika-sb.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "imx51.dtsi" -#include <arm/imx51.dtsi> +#include <arm/nxp/imx/imx51.dtsi> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -24,13 +24,13 @@ environment-sd { compatible = "barebox,environment"; - device-path = &esdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; environment-spi { compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; + device-path = &env_nor; status = "disabled"; }; }; @@ -394,9 +394,10 @@ &ipu_di1 { interface-pix-fmt = "rgb565"; - endpoint { - remote-endpoint = <&mtl017_in>; - }; +}; + +&ipu_di1_disp2 { + remote-endpoint = <&mtl017_in>; }; &esdhc1 { @@ -416,7 +417,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -534,7 +535,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 857c9ad96c..6bb491ec3b 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++ b/arch/arm/dts/imx51-zii-rdu1.dts @@ -11,7 +11,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx51-zii-rdu1.dts> +#include <arm/nxp/imx/imx51-zii-rdu1.dts> / { compatible = "zii,imx51-rdu1", "fsl,imx51-babbage-power", "fsl,imx51"; @@ -21,7 +21,7 @@ environment-spi { compatible = "barebox,environment"; - device-path = &spinor, "partname:barebox-environment"; + device-path = &env_spinor; }; ubootenv { @@ -53,33 +53,31 @@ * the switch shared DT node with it, so we use that * fact to create a desirable naming */ - switch-eeprom = &switch; - microwire-eeprom = µwire_eeprom; + switch-eeprom = &{mdio_gpio/switch@0}; + microwire-eeprom = &{spi_gpio/eeprom@0}; }; }; -&ecspi1 { - spinor: flash@1 { - partition@0 { - /* - * Do not change the size of this - * partition. RDU1's BBU code relies on - * "barebox" partition starting at 1024 byte - * mark to function properly - */ - label = "config"; - reg = <0x0 0x400>; - }; +spinor: &{ecspi1/flash@1} { + partition@0 { + /* + * Do not change the size of this + * partition. RDU1's BBU code relies on + * "barebox" partition starting at 1024 byte + * mark to function properly + */ + label = "config"; + reg = <0x0 0x400>; + }; - partition@400 { - label = "barebox"; - reg = <0x400 0xdfc00>; - }; + partition@400 { + label = "barebox"; + reg = <0x400 0xdfc00>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; + env_spinor: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; }; }; @@ -99,33 +97,21 @@ }; }; -&mdio_gpio { - switch: switch@0 {}; +&{uart3/mcu/watchdog} { + nvmem-cells = <&boot_source>; + nvmem-cell-names = "boot-source"; }; -&spi_gpio { - microwire_eeprom: eeprom@0 {}; -}; - -&uart3 { - rave-sp { - watchdog { - nvmem-cells = <&boot_source>; - nvmem-cell-names = "boot-source"; - }; +&{uart3/mcu/eeprom@a4} { + nvmem-cells = <&shadow_config>; + nvmem-cell-names = "shadow-config"; - eeprom@a4 { - nvmem-cells = <&shadow_config>; - nvmem-cell-names = "shadow-config"; - - boot_source: boot-source@83 { - reg = <0x83 1>; - }; + boot_source: boot-source@83 { + reg = <0x83 1>; + }; - shadow_config: shadow-config@1000 { - reg = <0x1000 0x400>; - }; - }; + shadow_config: shadow-config@1000 { + reg = <0x1000 0x400>; }; }; @@ -133,44 +119,41 @@ status = "disabled"; }; -&iomuxc { - pinctrl_usbh1: usbh1grp { - - /* - * Overwrite upstream USBH1,2 iomux settings to match - * the setting U-Boot would set these to. Remove this - * once this is fixed upstream. - */ - fsl,pins = < - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - >; - }; +&pinctrl_usbh1 { + /* + * Overwrite upstream USBH1,2 iomux settings to match + * the setting U-Boot would set these to. Remove this + * once this is fixed upstream. + */ + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + >; +}; - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX51_PAD_EIM_A26__USBH2_STP 0x1e5 - MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 - MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 - MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 - MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 - MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 - MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 - MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 - MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 - MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 - MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 - MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 - >; - }; +&pinctrl_usbh2 { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x1e5 + MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 + MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 + MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 + MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 + MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 + MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 + MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 + MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 + MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 + MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 + MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 + >; }; diff --git a/arch/arm/dts/imx51-zii-scu2-mezz.dts b/arch/arm/dts/imx51-zii-scu2-mezz.dts index 68a374bb2b..e44f7f999e 100644 --- a/arch/arm/dts/imx51-zii-scu2-mezz.dts +++ b/arch/arm/dts/imx51-zii-scu2-mezz.dts @@ -4,7 +4,7 @@ * Copyright (C) 2018 Zodiac Inflight Innovations */ -#include <arm/imx51-zii-scu2-mezz.dts> +#include <arm/nxp/imx/imx51-zii-scu2-mezz.dts> &iim { barebox,provide-mac-address = <&fec 1 9>; diff --git a/arch/arm/dts/imx51-zii-scu3-esb.dts b/arch/arm/dts/imx51-zii-scu3-esb.dts index c83bf17316..a7cffb60a9 100644 --- a/arch/arm/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/dts/imx51-zii-scu3-esb.dts @@ -5,7 +5,7 @@ */ -#include <arm/imx51-zii-scu3-esb.dts> +#include <arm/nxp/imx/imx51-zii-scu3-esb.dts> &iim { barebox,provide-mac-address = <&fec 1 9>; diff --git a/arch/arm/dts/imx51.dtsi b/arch/arm/dts/imx51.dtsi index 828a6c2e1b..521f182d20 100644 --- a/arch/arm/dts/imx51.dtsi +++ b/arch/arm/dts/imx51.dtsi @@ -3,4 +3,11 @@ pwm0 = &pwm1; pwm1 = &pwm2; }; + + chosen { + barebox,bootsource-mmc0 = &esdhc1; + barebox,bootsource-mmc1 = &esdhc2; + barebox,bootsource-mmc2 = &esdhc3; + barebox,bootsource-mmc3 = &esdhc4; + }; }; diff --git a/arch/arm/dts/imx53-ccxmx53.dtsi b/arch/arm/dts/imx53-ccxmx53.dtsi index d925ba44d7..6024785ff6 100644 --- a/arch/arm/dts/imx53-ccxmx53.dtsi +++ b/arch/arm/dts/imx53-ccxmx53.dtsi @@ -11,7 +11,7 @@ */ #include "imx53.dtsi" -#include <arm/imx53.dtsi> +#include <arm/nxp/imx/imx53.dtsi> / { @@ -20,18 +20,11 @@ environment { compatible = "barebox,environment"; - device-path = &nfc, "partname:environment"; + device-path = &env_nand; }; }; }; -/ { - memory { - reg = <0x0 0x0>; - }; - -}; - &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -236,7 +229,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nand: partition@e0000 { label = "environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts index d14c0dbf9c..a56a534653 100644 --- a/arch/arm/dts/imx53-guf-vincell-lt.dts +++ b/arch/arm/dts/imx53-guf-vincell-lt.dts @@ -13,7 +13,7 @@ /dts-v1/; #include "imx53.dtsi" -#include <arm/imx53.dtsi> +#include <arm/nxp/imx/imx53.dtsi> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/dts/imx53-guf-vincell.dts b/arch/arm/dts/imx53-guf-vincell.dts index a5f86ccf7e..f5922c2bf1 100644 --- a/arch/arm/dts/imx53-guf-vincell.dts +++ b/arch/arm/dts/imx53-guf-vincell.dts @@ -13,7 +13,7 @@ /dts-v1/; #include "imx53.dtsi" -#include <arm/imx53.dtsi> +#include <arm/nxp/imx/imx53.dtsi> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/dts/imx53-mba53.dts b/arch/arm/dts/imx53-mba53.dts index 53b98e30cf..02fdc6fdb3 100644 --- a/arch/arm/dts/imx53-mba53.dts +++ b/arch/arm/dts/imx53-mba53.dts @@ -10,7 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx53-mba53.dts> +#include <arm/nxp/imx/imx53-mba53.dts> #include "imx53-tqma53.dtsi" #include "imx53.dtsi" @@ -20,7 +20,7 @@ environment-sd { compatible = "barebox,environment"; - device-path = &esdhc2, "partname:environment"; + device-path = &env_sd2; status = "disabled"; }; }; @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@e0000 { + env_sd2: partition@e0000 { label = "environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx53-qsb.dts b/arch/arm/dts/imx53-qsb.dts index 773bc0b578..e035f4fcb9 100644 --- a/arch/arm/dts/imx53-qsb.dts +++ b/arch/arm/dts/imx53-qsb.dts @@ -10,6 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx53-qsb.dts> +#include <arm/nxp/imx/imx53-qsb.dts> #include "imx53.dtsi" #include "imx53-qsb-common.dtsi" diff --git a/arch/arm/dts/imx53-qsrb.dts b/arch/arm/dts/imx53-qsrb.dts index b3312786b1..358583ed07 100644 --- a/arch/arm/dts/imx53-qsrb.dts +++ b/arch/arm/dts/imx53-qsrb.dts @@ -10,6 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx53-qsrb.dts> +#include <arm/nxp/imx/imx53-qsrb.dts> #include "imx53.dtsi" #include "imx53-qsb-common.dtsi" diff --git a/arch/arm/dts/imx53-tx53-1011.dts b/arch/arm/dts/imx53-tx53-1011.dts index e9b1b3a221..9f2ad398bf 100644 --- a/arch/arm/dts/imx53-tx53-1011.dts +++ b/arch/arm/dts/imx53-tx53-1011.dts @@ -1,5 +1,5 @@ /dts-v1/; -#include <arm/imx53-tx53.dtsi> +#include <arm/nxp/imx/imx53-tx53.dtsi> / { model = "Ka-Ro electronics TX53 module"; diff --git a/arch/arm/dts/imx53-tx53-xx30.dts b/arch/arm/dts/imx53-tx53-xx30.dts index b9d1c65a2a..cf0fface21 100644 --- a/arch/arm/dts/imx53-tx53-xx30.dts +++ b/arch/arm/dts/imx53-tx53-xx30.dts @@ -1,5 +1,5 @@ /dts-v1/; -#include <arm/imx53-tx53.dtsi> +#include <arm/nxp/imx/imx53-tx53.dtsi> / { model = "Ka-Ro electronics TX53 module"; diff --git a/arch/arm/dts/imx53-voipac-bsb.dts b/arch/arm/dts/imx53-voipac-bsb.dts index 12ce592a47..316f662f27 100644 --- a/arch/arm/dts/imx53-voipac-bsb.dts +++ b/arch/arm/dts/imx53-voipac-bsb.dts @@ -9,6 +9,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx53-voipac-bsb.dts> +#include <arm/nxp/imx/imx53-voipac-bsb.dts> #include "imx53-voipac-dmm-668.dtsi" #include "imx53.dtsi" diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/dts/imx53-voipac-dmm-668.dtsi index c4c17c2e8e..16ab865d68 100644 --- a/arch/arm/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi @@ -4,7 +4,7 @@ environment { compatible = "barebox,environment"; - device-path = &nfc, "partname:environment"; + device-path = &env_nand; }; }; }; @@ -18,7 +18,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nand: partition@e0000 { label = "environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index 96fdd73ed0..0fd05f9b51 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -4,4 +4,11 @@ pwm1 = &pwm2; ipu0 = &ipu; }; + + chosen { + barebox,bootsource-mmc0 = &esdhc1; + barebox,bootsource-mmc1 = &esdhc2; + barebox,bootsource-mmc2 = &esdhc3; + barebox,bootsource-mmc3 = &esdhc4; + }; }; diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts index f0e3f4aa1f..9a1f3a2bf8 100755 --- a/arch/arm/dts/imx6dl-advantech-rom-7421.dts +++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts @@ -12,7 +12,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" / { @@ -24,19 +24,19 @@ environment-sd2 { /* Micro SD */ compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; environment-sd4 { /* eMMC */ compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &env_sd4; status = "disabled"; }; environment-spi { /* spi nor */ compatible = "barebox,environment"; - device-path = &ecspi1, "partname:barebox-environment"; + device-path = &env_nor; status = "disabled"; }; }; @@ -63,7 +63,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -115,7 +115,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -147,7 +147,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd4: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6dl-alti6p.dts b/arch/arm/dts/imx6dl-alti6p.dts index 04a6368f93..93ff66ee9c 100644 --- a/arch/arm/dts/imx6dl-alti6p.dts +++ b/arch/arm/dts/imx6dl-alti6p.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-alti6p.dts> +#include <arm/nxp/imx/imx6dl-alti6p.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-cm-fx6.dts b/arch/arm/dts/imx6dl-cm-fx6.dts index cc426e2a3c..202f4db7d6 100644 --- a/arch/arm/dts/imx6dl-cm-fx6.dts +++ b/arch/arm/dts/imx6dl-cm-fx6.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-cm-fx6.dtsi" diff --git a/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts b/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts index b6df37f373..b766611279 100644 --- a/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts +++ b/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts @@ -14,7 +14,7 @@ /dts-v1/; #endif -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-dfi-fs700-m60.dtsi" diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts index ce2af4051c..ff13c6679c 100644 --- a/arch/arm/dts/imx6dl-eltec-hipercam.dts +++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" / { diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts index 5bfa4704b2..a0e8ac84c6 100644 --- a/arch/arm/dts/imx6dl-hummingboard.dts +++ b/arch/arm/dts/imx6dl-hummingboard.dts @@ -5,7 +5,7 @@ * License version 2. */ -#include <arm/imx6dl-hummingboard.dts> +#include <arm/nxp/imx/imx6dl-hummingboard.dts> #include "imx6qdl.dtsi" / { @@ -14,7 +14,7 @@ environment { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; }; }; }; @@ -32,7 +32,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6dl-hummingboard2.dts b/arch/arm/dts/imx6dl-hummingboard2.dts index 40ef174411..c8ac4cb8eb 100644 --- a/arch/arm/dts/imx6dl-hummingboard2.dts +++ b/arch/arm/dts/imx6dl-hummingboard2.dts @@ -43,7 +43,7 @@ */ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6qdl-hummingboard2.dtsi" / { diff --git a/arch/arm/dts/imx6dl-lanmcu.dts b/arch/arm/dts/imx6dl-lanmcu.dts index 1a1fbad326..4780985da0 100644 --- a/arch/arm/dts/imx6dl-lanmcu.dts +++ b/arch/arm/dts/imx6dl-lanmcu.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-lanmcu.dts> +#include <arm/nxp/imx/imx6dl-lanmcu.dts> #include "imx6qdl-prti6q-emmc.dtsi" diff --git a/arch/arm/dts/imx6dl-mba6x.dts b/arch/arm/dts/imx6dl-mba6x.dts index dddc3d384c..612acba323 100644 --- a/arch/arm/dts/imx6dl-mba6x.dts +++ b/arch/arm/dts/imx6dl-mba6x.dts @@ -27,6 +27,19 @@ }; }; +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; diff --git a/arch/arm/dts/imx6dl-nitrogen6x.dts b/arch/arm/dts/imx6dl-nitrogen6x.dts index bc199c3167..7607090876 100644 --- a/arch/arm/dts/imx6dl-nitrogen6x.dts +++ b/arch/arm/dts/imx6dl-nitrogen6x.dts @@ -11,6 +11,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6dl-nitrogen6x.dts> +#include <arm/nxp/imx/imx6dl-nitrogen6x.dts> #include "imx6dl.dtsi" #include "imx6qdl-nitrogen6x.dtsi" diff --git a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi index d951c0bb8d..97586906af 100644 --- a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-pfla02.dtsi" diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts index 03df77f41d..133b75f5a7 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts index 0ef6f96bbe..7bb6acb556 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts index 0a4c2e6fb6..6add672644 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index fa518286c3..ddecfbc2b2 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6dl-plybas.dts b/arch/arm/dts/imx6dl-plybas.dts index b0e1595a41..20ff7fdf13 100644 --- a/arch/arm/dts/imx6dl-plybas.dts +++ b/arch/arm/dts/imx6dl-plybas.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-plybas.dts> +#include <arm/nxp/imx/imx6dl-plybas.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-plym2m.dts b/arch/arm/dts/imx6dl-plym2m.dts index bf29fc1bce..e1ae8d48b7 100644 --- a/arch/arm/dts/imx6dl-plym2m.dts +++ b/arch/arm/dts/imx6dl-plym2m.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-plym2m.dts> +#include <arm/nxp/imx/imx6dl-plym2m.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-prtmvt.dts b/arch/arm/dts/imx6dl-prtmvt.dts index 64e2f90110..6c49bbf606 100644 --- a/arch/arm/dts/imx6dl-prtmvt.dts +++ b/arch/arm/dts/imx6dl-prtmvt.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-prtmvt.dts> +#include <arm/nxp/imx/imx6dl-prtmvt.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-prtrvt.dts b/arch/arm/dts/imx6dl-prtrvt.dts index e0d9261d27..ee97fa8a65 100644 --- a/arch/arm/dts/imx6dl-prtrvt.dts +++ b/arch/arm/dts/imx6dl-prtrvt.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-prtrvt.dts> +#include <arm/nxp/imx/imx6dl-prtrvt.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-prtvt7.dts b/arch/arm/dts/imx6dl-prtvt7.dts index 19794add17..a9e0589c2c 100644 --- a/arch/arm/dts/imx6dl-prtvt7.dts +++ b/arch/arm/dts/imx6dl-prtvt7.dts @@ -1,13 +1,15 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-prtvt7.dts> +#include <arm/nxp/imx/imx6dl-prtvt7.dts> #include "imx6qdl-prti6q-emmc.dtsi" &state_emmc { magic = <0x72766467>; + #address-cells = <1>; + #size-cells = <1>; - brand { + brand@1b0 { reg = <0x1b0 0x4>; type = "enum32"; names = "unbranded", "agco", "vermeer"; diff --git a/arch/arm/dts/imx6dl-sabrelite.dts b/arch/arm/dts/imx6dl-sabrelite.dts index 849bcdd61a..051100ef42 100644 --- a/arch/arm/dts/imx6dl-sabrelite.dts +++ b/arch/arm/dts/imx6dl-sabrelite.dts @@ -11,7 +11,7 @@ */ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-sabrelite.dtsi" diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts new file mode 100644 index 0000000000..6de132a64e --- /dev/null +++ b/arch/arm/dts/imx6dl-sabresd.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <arm/nxp/imx/imx6dl-sabresd.dts> + +/ { + model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; + compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; + + chosen { + stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &environment_usdhc3; + }; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + environment_usdhc3: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx6dl-samx6i.dts b/arch/arm/dts/imx6dl-samx6i.dts index da648ef5b8..5a752296d0 100644 --- a/arch/arm/dts/imx6dl-samx6i.dts +++ b/arch/arm/dts/imx6dl-samx6i.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include <arm/imx6dl-kontron-samx6i.dtsi> +#include <arm/nxp/imx/imx6dl-kontron-samx6i.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-smarc-samx6i.dtsi" diff --git a/arch/arm/dts/imx6dl-skov-imx6.dts b/arch/arm/dts/imx6dl-skov-imx6.dts index c2dac68204..304068cbdb 100644 --- a/arch/arm/dts/imx6dl-skov-imx6.dts +++ b/arch/arm/dts/imx6dl-skov-imx6.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-skov-imx6.dtsi" diff --git a/arch/arm/dts/imx6dl-tqma6s.dtsi b/arch/arm/dts/imx6dl-tqma6s.dtsi index 63459ce7ea..13754a6790 100644 --- a/arch/arm/dts/imx6dl-tqma6s.dtsi +++ b/arch/arm/dts/imx6dl-tqma6s.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-tqma6x.dtsi" diff --git a/arch/arm/dts/imx6dl-tx6u.dts b/arch/arm/dts/imx6dl-tx6u.dts index 6c26feb978..a41773780c 100644 --- a/arch/arm/dts/imx6dl-tx6u.dts +++ b/arch/arm/dts/imx6dl-tx6u.dts @@ -1,7 +1,7 @@ /dts-v1/; -#include <arm/imx6dl.dtsi> -#include <arm/imx6qdl-tx6.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> +#include <arm/nxp/imx/imx6qdl-tx6.dtsi> #include "imx6qdl.dtsi" #include "imx6qdl-tx6x.dtsi" diff --git a/arch/arm/dts/imx6dl-victgo.dts b/arch/arm/dts/imx6dl-victgo.dts index 250cd761d4..e3bbda5632 100644 --- a/arch/arm/dts/imx6dl-victgo.dts +++ b/arch/arm/dts/imx6dl-victgo.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-victgo.dts> +#include <arm/nxp/imx/imx6dl-victgo.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-vicut1.dts b/arch/arm/dts/imx6dl-vicut1.dts index 99cc7af2e6..4a2965518c 100644 --- a/arch/arm/dts/imx6dl-vicut1.dts +++ b/arch/arm/dts/imx6dl-vicut1.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6dl-vicut1.dts> +#include <arm/nxp/imx/imx6dl-vicut1.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6dl-wandboard.dts b/arch/arm/dts/imx6dl-wandboard.dts index c4695fb8d8..e8d4a90032 100644 --- a/arch/arm/dts/imx6dl-wandboard.dts +++ b/arch/arm/dts/imx6dl-wandboard.dts @@ -1,4 +1,4 @@ -#include <arm/imx6dl-wandboard.dts> +#include <arm/nxp/imx/imx6dl-wandboard.dts> #include <dt-bindings/gpio/gpio.h> #include "imx6dl.dtsi" diff --git a/arch/arm/dts/imx6q-cm-fx6.dts b/arch/arm/dts/imx6q-cm-fx6.dts index aaaa7189d8..d661c074dd 100644 --- a/arch/arm/dts/imx6q-cm-fx6.dts +++ b/arch/arm/dts/imx6q-cm-fx6.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6qdl-cm-fx6.dtsi" / { diff --git a/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts b/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts index 8ecd667e9e..58927097cd 100644 --- a/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts +++ b/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts @@ -14,7 +14,7 @@ /dts-v1/; #endif -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-dfi-fs700-m60.dtsi" diff --git a/arch/arm/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/dts/imx6q-dmo-edmqmx6.dts index fcf8ad8993..1280837db6 100644 --- a/arch/arm/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/dts/imx6q-dmo-edmqmx6.dts @@ -11,7 +11,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6q-dmo-edmqmx6.dts> +#include <arm/nxp/imx/imx6q-dmo-edmqmx6.dts> / { chosen { @@ -19,19 +19,19 @@ environment-sd { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &env_sd3; status = "disabled"; }; environment-emmc { compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &env_sd4; status = "disabled"; }; environment-spi { compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; + device-path = &env_nor; status = "disabled"; }; }; @@ -46,7 +46,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -77,7 +77,8 @@ label = "barebox"; reg = <0x0 0xe0000>; }; - partition@e0000 { + + env_sd3: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -91,7 +92,8 @@ label = "barebox"; reg = <0x0 0xe0000>; }; - partition@e0000 { + + env_sd4: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts index 76c940b709..7ab2b22e95 100644 --- a/arch/arm/dts/imx6q-embedsky-e9.dts +++ b/arch/arm/dts/imx6q-embedsky-e9.dts @@ -12,7 +12,7 @@ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6q-embedsky-e9.dtsi" diff --git a/arch/arm/dts/imx6q-gk802.dts b/arch/arm/dts/imx6q-gk802.dts index 310d6f0f5e..d40f503936 100644 --- a/arch/arm/dts/imx6q-gk802.dts +++ b/arch/arm/dts/imx6q-gk802.dts @@ -6,7 +6,7 @@ * kind, whether express or implied. */ -#include <arm/imx6q-gk802.dts> +#include <arm/nxp/imx/imx6q-gk802.dts> #include "imx6q.dtsi" /* External USB-A port (USBOTG) */ diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts index e72aacc59b..96ea1dda3b 100644 --- a/arch/arm/dts/imx6q-guf-santaro.dts +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -13,7 +13,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" / { diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts index ec0f3632ba..316fe3790f 100644 --- a/arch/arm/dts/imx6q-gw54xx.dts +++ b/arch/arm/dts/imx6q-gw54xx.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-gw54xx.dtsi" diff --git a/arch/arm/dts/imx6q-h100.dts b/arch/arm/dts/imx6q-h100.dts index bfee186f28..7fda9f1222 100644 --- a/arch/arm/dts/imx6q-h100.dts +++ b/arch/arm/dts/imx6q-h100.dts @@ -39,13 +39,13 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <arm/imx6q-h100.dts> +#include <arm/nxp/imx/imx6q-h100.dts> / { chosen { environment { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; }; }; }; @@ -63,7 +63,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6q-hummingboard.dts b/arch/arm/dts/imx6q-hummingboard.dts index b10acf2cbb..0bb4a6b48e 100644 --- a/arch/arm/dts/imx6q-hummingboard.dts +++ b/arch/arm/dts/imx6q-hummingboard.dts @@ -5,7 +5,7 @@ * License version 2. */ -#include <arm/imx6q-hummingboard.dts> +#include <arm/nxp/imx/imx6q-hummingboard.dts> #include "imx6qdl.dtsi" / { @@ -14,7 +14,7 @@ environment { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; }; }; }; @@ -32,7 +32,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6q-hummingboard2.dts b/arch/arm/dts/imx6q-hummingboard2.dts index 6c41ab7396..6ef7f935e3 100644 --- a/arch/arm/dts/imx6q-hummingboard2.dts +++ b/arch/arm/dts/imx6q-hummingboard2.dts @@ -43,7 +43,7 @@ */ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6qdl-hummingboard2.dtsi" #include "imx6q.dtsi" @@ -54,7 +54,7 @@ chosen { environment { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &env_sd3; }; }; }; @@ -80,7 +80,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd3: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6q-marsboard.dts b/arch/arm/dts/imx6q-marsboard.dts index cc5edfff66..b6fce7c898 100644 --- a/arch/arm/dts/imx6q-marsboard.dts +++ b/arch/arm/dts/imx6q-marsboard.dts @@ -3,7 +3,7 @@ * Copyright (C) 2019 Ahmad Fatoum - Pengutronix */ -#include <arm/imx6q-marsboard.dts> +#include <arm/nxp/imx/imx6q-marsboard.dts> #include "imx6q.dtsi" / { @@ -18,7 +18,7 @@ }; &ecspi1 { - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6q-mba6x.dts b/arch/arm/dts/imx6q-mba6x.dts index 64635b9582..5154580fae 100644 --- a/arch/arm/dts/imx6q-mba6x.dts +++ b/arch/arm/dts/imx6q-mba6x.dts @@ -27,6 +27,19 @@ }; }; +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts index 14f7ba2190..294b9d8ce2 100644 --- a/arch/arm/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/dts/imx6q-nitrogen6x.dts @@ -11,7 +11,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6q-nitrogen6x.dts> +#include <arm/nxp/imx/imx6q-nitrogen6x.dts> #include "imx6q.dtsi" #include "imx6qdl-nitrogen6x.dtsi" diff --git a/arch/arm/dts/imx6q-novena.dts b/arch/arm/dts/imx6q-novena.dts new file mode 100644 index 0000000000..554b66fb5a --- /dev/null +++ b/arch/arm/dts/imx6q-novena.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR X11 +// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org> + +#include <arm/nxp/imx/imx6q-novena.dts> + +/ { + aliases { + eeprom0 = &eeprom; + }; +}; + +&i2c3 { + eeprom: eeprom@56 { + compatible = "24c512"; + reg = <0x56>; + pagesize = <128>; + }; +}; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi index 48f1da3cad..10e2c9dc11 100644 --- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-pfla02.dtsi" diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts b/arch/arm/dts/imx6q-phytec-phycard.dts index b0e47e9b62..0fbd62af7b 100644 --- a/arch/arm/dts/imx6q-phytec-phycard.dts +++ b/arch/arm/dts/imx6q-phytec-phycard.dts @@ -10,7 +10,7 @@ #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-phycard-som.dtsi" diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index 2414befd35..167d68cc8c 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index 864dc190bc..188197d5b6 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6q-prti6q.dts b/arch/arm/dts/imx6q-prti6q.dts index 71606b892c..caf1ea746d 100644 --- a/arch/arm/dts/imx6q-prti6q.dts +++ b/arch/arm/dts/imx6q-prti6q.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6q-prti6q.dts> +#include <arm/nxp/imx/imx6q-prti6q.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6q-prtwd2.dts b/arch/arm/dts/imx6q-prtwd2.dts index 78ea4bc15c..a2315f6e2c 100644 --- a/arch/arm/dts/imx6q-prtwd2.dts +++ b/arch/arm/dts/imx6q-prtwd2.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6q-prtwd2.dts> +#include <arm/nxp/imx/imx6q-prtwd2.dts> #include "imx6qdl-prti6q-emmc.dtsi" diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts index b6d1c09b77..74060f3e79 100644 --- a/arch/arm/dts/imx6q-sabrelite.dts +++ b/arch/arm/dts/imx6q-sabrelite.dts @@ -11,7 +11,7 @@ */ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-sabrelite.dtsi" diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts index 21180df324..c4456e322e 100644 --- a/arch/arm/dts/imx6q-sabresd.dts +++ b/arch/arm/dts/imx6q-sabresd.dts @@ -12,7 +12,7 @@ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-sabresd.dtsi" diff --git a/arch/arm/dts/imx6q-samx6i.dts b/arch/arm/dts/imx6q-samx6i.dts index a2ea076edf..6069db4397 100644 --- a/arch/arm/dts/imx6q-samx6i.dts +++ b/arch/arm/dts/imx6q-samx6i.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include <arm/imx6q-kontron-samx6i.dtsi> +#include <arm/nxp/imx/imx6q-kontron-samx6i.dtsi> #include "imx6q.dtsi" #include "imx6qdl-smarc-samx6i.dtsi" diff --git a/arch/arm/dts/imx6q-skov-imx6.dts b/arch/arm/dts/imx6q-skov-imx6.dts index fea84cb498..7a2063a416 100644 --- a/arch/arm/dts/imx6q-skov-imx6.dts +++ b/arch/arm/dts/imx6q-skov-imx6.dts @@ -10,17 +10,13 @@ */ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-skov-imx6.dtsi" / { model = "Skov IMX6"; compatible = "skov,imx6", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; }; &i2c2 { diff --git a/arch/arm/dts/imx6q-tqma6q.dtsi b/arch/arm/dts/imx6q-tqma6q.dtsi index c2382b07db..cdb486cdff 100644 --- a/arch/arm/dts/imx6q-tqma6q.dtsi +++ b/arch/arm/dts/imx6q-tqma6q.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-tqma6x.dtsi" diff --git a/arch/arm/dts/imx6q-tx6q.dts b/arch/arm/dts/imx6q-tx6q.dts index 6063dd4fe5..b5602fa4fd 100644 --- a/arch/arm/dts/imx6q-tx6q.dts +++ b/arch/arm/dts/imx6q-tx6q.dts @@ -1,7 +1,7 @@ /dts-v1/; -#include <arm/imx6q.dtsi> -#include <arm/imx6qdl-tx6.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> +#include <arm/nxp/imx/imx6qdl-tx6.dtsi> #include "imx6q.dtsi" #include "imx6qdl-tx6x.dtsi" diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts index c8a12a38dd..1d2b05c19e 100644 --- a/arch/arm/dts/imx6q-udoo.dts +++ b/arch/arm/dts/imx6q-udoo.dts @@ -13,7 +13,7 @@ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-udoo.dtsi" diff --git a/arch/arm/dts/imx6q-utilite.dts b/arch/arm/dts/imx6q-utilite.dts index 14b65d64a7..79465975d1 100644 --- a/arch/arm/dts/imx6q-utilite.dts +++ b/arch/arm/dts/imx6q-utilite.dts @@ -1,5 +1,5 @@ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6qdl-cm-fx6.dtsi" / { diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts index ddb220fb0a..cbfe4da7e1 100644 --- a/arch/arm/dts/imx6q-var-custom.dts +++ b/arch/arm/dts/imx6q-var-custom.dts @@ -83,7 +83,7 @@ fsl,data-width = <24>; status = "okay"; display-timings { - native-mode = &claawvga; + native-mode = <&claawvga>; claawvga: claawvga { native-mode; clock-frequency = <35714000>; diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi index 7dbaa1e3d4..6dc6c51f84 100644 --- a/arch/arm/dts/imx6q-var-som.dtsi +++ b/arch/arm/dts/imx6q-var-som.dtsi @@ -10,7 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" / { diff --git a/arch/arm/dts/imx6q-vicut1.dts b/arch/arm/dts/imx6q-vicut1.dts index 61fb56d401..cd882b0ed1 100644 --- a/arch/arm/dts/imx6q-vicut1.dts +++ b/arch/arm/dts/imx6q-vicut1.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6q-vicut1.dts> +#include <arm/nxp/imx/imx6q-vicut1.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6q-wandboard.dts b/arch/arm/dts/imx6q-wandboard.dts index d182faf217..2cbaa8d830 100644 --- a/arch/arm/dts/imx6q-wandboard.dts +++ b/arch/arm/dts/imx6q-wandboard.dts @@ -1,4 +1,4 @@ -#include <arm/imx6q-wandboard.dts> +#include <arm/nxp/imx/imx6q-wandboard.dts> #include <dt-bindings/gpio/gpio.h> #include "imx6q.dtsi" diff --git a/arch/arm/dts/imx6q-zii-rdu2.dts b/arch/arm/dts/imx6q-zii-rdu2.dts index db75e29f87..dadba5be37 100644 --- a/arch/arm/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/dts/imx6q-zii-rdu2.dts @@ -42,7 +42,7 @@ /dts-v1/; -#include <arm/imx6q.dtsi> +#include <arm/nxp/imx/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-zii-rdu2.dtsi" diff --git a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi index 73878cde0d..3ce8d0a534 100644 --- a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -1,4 +1,4 @@ -#include <arm/imx6qdl-dfi-fs700-m60.dtsi> +#include <arm/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi> / { chosen { diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index 23e08f7d92..569d2cbffe 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ - #include <arm/imx6qdl-gw54xx.dtsi> + #include <arm/nxp/imx/imx6qdl-gw54xx.dtsi> / { chosen { @@ -17,7 +17,7 @@ environment { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; }; }; }; @@ -31,7 +31,7 @@ reg = <0x0 0x400000>; }; - partition@400000 { + env_nand: partition@400000 { label = "barebox-environment"; reg = <0x400000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/dts/imx6qdl-hummingboard2.dtsi index 6f37d5afa5..7da33306c6 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2.dtsi @@ -40,7 +40,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include <arm/imx6qdl-sr-som.dtsi> +#include <arm/nxp/imx/imx6qdl-sr-som.dtsi> / { chosen { diff --git a/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi index 19fe7881b3..0f6d17ad6c 100644 --- a/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi @@ -39,12 +39,12 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - + / { chosen { environment { compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; + device-path = &env_nor; }; }; }; @@ -58,7 +58,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -66,4 +66,4 @@ &ocotp { barebox,provide-mac-address = <&fec 0x620>; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi index 5c43b16ab1..4411e89ded 100644 --- a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -10,7 +10,7 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6qdl-nitrogen6x.dtsi> +#include <arm/nxp/imx/imx6qdl-nitrogen6x.dtsi> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -18,7 +18,7 @@ chosen { environment { compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; + device-path = &env_nor; }; }; }; @@ -35,7 +35,7 @@ /delete-node/ partition@c0000; /delete-node/ partition@c2000; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/dts/imx6qdl-phytec-mira.dtsi index 49cbd25fc3..bcda7dd82a 100644 --- a/arch/arm/dts/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-mira.dtsi @@ -4,7 +4,7 @@ * Author: Stefan Riedmueller <s.riedmueller@phytec.de> */ -#include <arm/imx6qdl-phytec-mira.dtsi> +#include <arm/nxp/imx/imx6qdl-phytec-mira.dtsi> #include <dt-bindings/gpio/gpio.h> / { @@ -36,7 +36,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd1: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi index 88db962535..7d5b3bae05 100644 --- a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6qdl-phytec-pbab01.dtsi> +#include <arm/nxp/imx/imx6qdl-phytec-pbab01.dtsi> &uart1 { status = "okay"; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index ada1607688..56b42cd1ef 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -9,43 +9,25 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6qdl-phytec-pfla02.dtsi> +#include <arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi> / { chosen { environment-nand { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; status = "disabled"; }; environment-spinor { compatible = "barebox,environment"; - device-path = &som_flash, "partname:barebox-environment"; - status = "disabled"; - }; - - environment-sd1 { - compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; - status = "disabled"; - }; - - environment-sd2 { - compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_nor; status = "disabled"; }; environment-sd3 { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; - status = "disabled"; - }; - - environment-sd4 { - compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &env_sd3; status = "disabled"; }; }; @@ -64,7 +46,7 @@ reg = <0x0 0x100000>; }; - partition@100000 { + env_nor: partition@100000 { label = "barebox-environment"; reg = <0x100000 0x20000>; }; @@ -92,7 +74,7 @@ reg = <0x0 0x1000000>; }; - partition@1000000 { + env_nand: partition@1000000 { label = "barebox-environment"; reg = <0x1000000 0x100000>; }; @@ -138,7 +120,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd3: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index 2c333ce8fe..c66a6a529d 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -4,32 +4,32 @@ * Author: Christian Hemp <c.hemp@phytec.de> */ -#include <arm/imx6qdl-phytec-phycore-som.dtsi> +#include <arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi> #include <dt-bindings/gpio/gpio.h> / { chosen { environment-sd1 { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; + device-path = &env_sd1; status = "disabled"; }; environment-sd4 { compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &env_sd4; status = "disabled"; }; environment-nand { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; status = "disabled"; }; environment-spinor { compatible = "barebox,environment"; - device-path = &m25p80, "partname:barebox-environment"; + device-path = &env_nor; status = "disabled"; }; }; @@ -53,7 +53,7 @@ reg = <0x0 0x1000000>; }; - partition@400000 { + env_nand: partition@400000 { label = "barebox-environment"; reg = <0x1000000 0x100000>; }; @@ -90,7 +90,7 @@ reg = <0x0 0x100000>; }; - partition@100000 { + env_nor: partition@100000 { label = "barebox-environment"; reg = <0x100000 0x20000>; }; @@ -122,7 +122,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd4: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi index 094b0b09d7..c9c75a9ade 100644 --- a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi +++ b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi @@ -8,9 +8,9 @@ chosen { stdout-path = &uart4; - environment@0 { + environment { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &env_sd3; }; }; @@ -20,8 +20,6 @@ backend-type = "raw"; backend = <&state_backend_emmc>; backend-stridesize = <0x400>; - #address-cells = <1>; - #size-cells = <1>; bootstate { #address-cells = <1>; @@ -31,13 +29,13 @@ #address-cells = <1>; #size-cells = <1>; - remaining_attempts { + remaining_attempts@0 { reg = <0x0 0x4>; type = "uint32"; default = <3>; }; - priority { + priority@4 { reg = <0x4 0x4>; type = "uint32"; default = <21>; @@ -48,20 +46,20 @@ #address-cells = <1>; #size-cells = <1>; - remaining_attempts { + remaining_attempts@10 { reg = <0x10 0x4>; type = "uint32"; default = <3>; }; - priority { + priority@14 { reg = <0x14 0x4>; type = "uint32"; default = <20>; }; }; - last_chosen { + last_chosen@20 { reg = <0x20 0x4>; type = "uint32"; }; @@ -71,7 +69,7 @@ #address-cells = <1>; #size-cells = <1>; - data_partitions { + data_partitions@26 { reg = <0x26 0x100>; type = "string"; }; @@ -88,24 +86,13 @@ compatible = "ramoops"; }; }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address will be determined by the bootloader */ - ramoops { - compatible = "ramoops"; - }; - }; }; &usdhc3 { #address-cells = <1>; #size-cells = <1>; - partition@40000 { + env_sd3: partition@40000 { label = "barebox-environment"; reg = <0x40000 0x80000>; }; diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi index ec3d364bde..07e3879d85 100644 --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi @@ -11,7 +11,7 @@ */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <arm/imx6qdl-sabrelite.dtsi> +#include <arm/nxp/imx/imx6qdl-sabrelite.dtsi> / { @@ -20,7 +20,7 @@ environment { compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; + device-path = &env_nor; }; }; }; @@ -34,7 +34,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_nor: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index 6b10229c88..4e3366f4fe 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -10,7 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6qdl-sabresd.dtsi> +#include <arm/nxp/imx/imx6qdl-sabresd.dtsi> &ocotp { barebox,provide-mac-address = <&fec 0x620>; diff --git a/arch/arm/dts/imx6qdl-skov-imx6.dtsi b/arch/arm/dts/imx6qdl-skov-imx6.dtsi index 371a931e53..b8fc1ec0bc 100644 --- a/arch/arm/dts/imx6qdl-skov-imx6.dtsi +++ b/arch/arm/dts/imx6qdl-skov-imx6.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <dt-bindings/gpio/gpio.h> +#include <arm/nxp/imx/imx6qdl-skov-cpu.dtsi> / { aliases { @@ -30,29 +30,6 @@ }; }; - leds { - compatible = "gpio-leds"; - - led0: D1 { - label = "D1"; - gpios = <&gpio1 2 0>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: D2 { - label = "D2"; - gpios = <&gpio1 0 0>; - default-state = "off"; - }; - - led2: D3 { - label = "D3"; - gpios = <&gpio1 4 0>; - default-state = "on"; - }; - }; - /* State: mutable part */ state: state { magic = <0x34a0fc27>; @@ -136,7 +113,7 @@ #address-cells = <1>; #size-cells = <1>; - eth2 { + eth2@1e { reg = <0x1E 0x6>; type = "mac"; default = [00 11 22 33 44 55]; @@ -169,7 +146,7 @@ }; display-timings { - native-mode = &l2rt; + native-mode = <&l2rt>; l2rt: l2rt { native-mode; @@ -213,7 +190,7 @@ /* power-supply = <®_3p3v>; */ display-timings { - native-mode = &mi1010ait_1cp1; + native-mode = <&mi1010ait_1cp1>; mi1010ait_1cp1: mi1010ait-1cp1 { native-mode; @@ -241,20 +218,6 @@ }; }; -&pwm2 { - /* used for backlight brightness */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2_2>; - status = "okay"; -}; - -&pwm3 { - /* used for LCD contrast control */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3_2>; - status = "okay"; -}; - &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -278,21 +241,6 @@ status = "okay"; }; -/* no usbh2 */ -&usbphynop1 { - status = "disabled"; -}; - -/* no usbh3 */ -&usbphynop2 { - status = "disabled"; -}; - -&usbotg { - disable-over-current; - status = "okay"; -}; - &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -300,10 +248,6 @@ pinctrl_hog: hoggrp { /* we need a few pins as GPIOs */ fsl,pins = < - /* MMC IO voltage select */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40000058 - /* MMC Power Supply Switch (since revision C) - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x40000058 /* Backlight Power Supply Switch (since revision B) MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x40000058 /* Backlight Brightness */ @@ -313,70 +257,6 @@ >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x40000058 /* CS# signal */ - >; - }; - - /* pins for eth0 */ - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x400000c0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 /* WP */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 /* CD */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - pinctrl_i2c2_2: i2c2grp-2 { fsl,pins = < /* internal 22 k pull up required */ @@ -424,18 +304,6 @@ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x40000058 >; }; - - pinctrl_pwm2_2: pwm2grp-2 { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x00058 - >; - }; - - pinctrl_pwm3_2: pwm3grp-2 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x00058 - >; - }; }; &clks { @@ -445,43 +313,34 @@ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - /* spi */ &ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 24 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; + flash@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - norflash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <54000000>; - reg = <0>; - }; -}; + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; -/* eth0 */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - status = "okay"; - phy-reset-gpios = <&gpio1 5 0>; - phy-reset-duration = <100>; - #address-cells = <0>; - #size-cells = <1>; - fixed-link { - speed = <100>; - full-duplex; + /* space left to let barebox grow */ + + /* placed near the end of the NOR memory */ + barebox_env: partition@780000 { + label = "barebox-environment"; + reg = <0x780000 0x40000>; + }; + + /* placed at the end of the NOR memory */ + state_storage: partition@7C0000 { + label = "barebox-state"; + /* four times mirrored */ + reg = <0x7C0000 0x40000>; + }; + }; }; }; @@ -506,21 +365,7 @@ status = "okay"; }; -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - wp-gpios = <&gpio7 1 0>; - cd-gpios = <&gpio7 0 0>; - status = "okay"; - fsl,delay-line; -}; - &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -533,34 +378,6 @@ }; }; -/* define the SPI based 8 MiB NOR flash layout */ -&norflash { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x100000>; - }; - - /* space left to let barebox grow */ - - /* placed near the end of the NOR memory */ - barebox_env: partition@780000 { - label = "barebox-environment"; - reg = <0x780000 0x40000>; - }; - - /* placed at the end of the NOR memory */ - state_storage: partition@7C0000 { - label = "barebox-state"; - reg = <0x7C0000 0x40000>; /* four times mirrored */ - }; - }; -}; - &ocotp { barebox,provide-mac-address = <&fec 0x620>; }; diff --git a/arch/arm/dts/imx6qdl-tx6x.dtsi b/arch/arm/dts/imx6qdl-tx6x.dtsi index 13102168f7..139b735b6d 100644 --- a/arch/arm/dts/imx6qdl-tx6x.dtsi +++ b/arch/arm/dts/imx6qdl-tx6x.dtsi @@ -5,7 +5,7 @@ environment-nand { status = "disabled"; compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; }; environment-emmc { @@ -14,10 +14,10 @@ device-path = &usdhc4, "partname:boot1"; }; }; +}; - gpio-keys { - status = "disabled"; - }; +&{/gpio-keys} { + status = "disabled"; }; &fec { @@ -34,7 +34,7 @@ reg = <0x0 0x400000>; }; - partition@400000 { + env_nand: partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi index b593545ffe..a01962d0e6 100644 --- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi @@ -39,13 +39,13 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <arm/imx6qdl-zii-rdu2.dtsi> +#include <arm/nxp/imx/imx6qdl-zii-rdu2.dtsi> / { chosen { environment { compatible = "barebox,environment"; - device-path = &nor_flash, "partname:barebox-environment"; + device-path = &env_nor; }; ubootenv { @@ -178,34 +178,27 @@ }; }; -&uart4 { - rave-sp { - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - nvmem-cells = <&boot_source>; - nvmem-cell-names = "boot-source"; - }; +&{uart4/mcu/watchdog} { + nvmem-cells = <&boot_source>; + nvmem-cell-names = "boot-source"; +}; - eeprom@a4 { - lru_part_number: lru-part-number@21 { - reg = <0x21 15>; - read-only; - }; +&{uart4/mcu/eeprom@a4} { + lru_part_number: lru-part-number@21 { + reg = <0x21 15>; + read-only; + }; - boot_source: boot-source@83 { - reg = <0x83 1>; - }; + boot_source: boot-source@83 { + reg = <0x83 1>; + }; - mac_address_0: mac-address@180 { - reg = <0x180 6>; - }; + mac_address_0: mac-address@180 { + reg = <0x180 6>; + }; - mac_address_1: mac-address@190 { - reg = <0x190 6>; - }; - }; + mac_address_1: mac-address@190 { + reg = <0x190 6>; }; }; @@ -219,7 +212,7 @@ reg = <0x0 0xc0000>; }; - partition@c0000 { + env_nor: partition@c0000 { label = "barebox-environment"; reg = <0xc0000 0x40000>; }; @@ -231,36 +224,16 @@ nvmem-cell-names = "mac-address"; }; -&i2c1 { - edp-bridge@68 { - pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>; - - ports { - port@1 { - reg = <1>; - - tc358767_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; +&{i2c1/edp-bridge@68} { + pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>; }; -&i2c2 { - temp-sense@48 { - barebox,sensor-name = "Temp Sensor 1"; - }; +&{i2c2/temp-sense@48} { + barebox,sensor-name = "Temp Sensor 1"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&tc358767_in>; -}; - -&ldb { - lvds-channel@0 { - fsl,data-width = <24>; - }; +&{ldb/lvds-channel@0} { + fsl,data-width = <24>; }; &i210 { diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index c3e02d2117..6f58804ed3 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -8,6 +8,13 @@ ipu0 = &ipu1; gpr.reboot_mode = &reboot_mode_gpr; }; + + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; + barebox,bootsource-mmc3 = &usdhc4; + }; }; &src { diff --git a/arch/arm/dts/imx6qp-nitrogen6_max.dts b/arch/arm/dts/imx6qp-nitrogen6_max.dts index 93f0741062..17ae7c1bd3 100644 --- a/arch/arm/dts/imx6qp-nitrogen6_max.dts +++ b/arch/arm/dts/imx6qp-nitrogen6_max.dts @@ -40,5 +40,5 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <arm/imx6qp-nitrogen6_max.dts> +#include <arm/nxp/imx/imx6qp-nitrogen6_max.dts> #include "imx6qdl-nitrogen6_max.dtsi" diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts index 378806df53..8ed5635199 100644 --- a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6qp.dtsi> +#include <arm/nxp/imx/imx6qp.dtsi> #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" diff --git a/arch/arm/dts/imx6qp-prtwd3.dts b/arch/arm/dts/imx6qp-prtwd3.dts index 8c56d70b5a..dc52eebc85 100644 --- a/arch/arm/dts/imx6qp-prtwd3.dts +++ b/arch/arm/dts/imx6qp-prtwd3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6qp-prtwd3.dts> +#include <arm/nxp/imx/imx6qp-prtwd3.dts> #include "imx6qdl-prti6q-emmc.dtsi" diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts index 1fb20cb0b4..1811044d94 100644 --- a/arch/arm/dts/imx6qp-sabresd.dts +++ b/arch/arm/dts/imx6qp-sabresd.dts @@ -10,7 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6qp-sabresd.dts> +#include <arm/nxp/imx/imx6qp-sabresd.dts> / { model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; diff --git a/arch/arm/dts/imx6qp-vicutp.dts b/arch/arm/dts/imx6qp-vicutp.dts index 1411071fb3..8827ffdebb 100644 --- a/arch/arm/dts/imx6qp-vicutp.dts +++ b/arch/arm/dts/imx6qp-vicutp.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6qp-vicutp.dts> +#include <arm/nxp/imx/imx6qp-vicutp.dts> #include "imx6qdl-prti6q-nor.dtsi" diff --git a/arch/arm/dts/imx6qp-zii-rdu2.dts b/arch/arm/dts/imx6qp-zii-rdu2.dts index fcf2ee5a10..007428640f 100644 --- a/arch/arm/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/dts/imx6qp-zii-rdu2.dts @@ -42,7 +42,7 @@ /dts-v1/; -#include <arm/imx6qp.dtsi> +#include <arm/nxp/imx/imx6qp.dtsi> #include "imx6q.dtsi" #include "imx6qdl-zii-rdu2.dtsi" diff --git a/arch/arm/dts/imx6s-phytec-pfla02.dtsi b/arch/arm/dts/imx6s-phytec-pfla02.dtsi index 7ef27fb941..d8af37c045 100644 --- a/arch/arm/dts/imx6s-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6s-phytec-pfla02.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-pfla02.dtsi" diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts index 9efef039a7..5ddd30fb96 100644 --- a/arch/arm/dts/imx6s-riotboard.dts +++ b/arch/arm/dts/imx6s-riotboard.dts @@ -5,7 +5,7 @@ * License version 2. */ -#include <arm/imx6dl-riotboard.dts> +#include <arm/nxp/imx/imx6dl-riotboard.dts> #include "imx6qdl.dtsi" / { diff --git a/arch/arm/dts/imx6s-skov-imx6.dts b/arch/arm/dts/imx6s-skov-imx6.dts index 9061563e45..e05abd3dab 100644 --- a/arch/arm/dts/imx6s-skov-imx6.dts +++ b/arch/arm/dts/imx6s-skov-imx6.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include <arm/imx6dl.dtsi> +#include <arm/nxp/imx/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-skov-imx6.dtsi" diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index 8cf412a39f..f58df62cbd 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -7,14 +7,14 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx6sx-sdb.dts> +#include <arm/nxp/imx/imx6sx-sdb.dts> #include "imx6sx.dtsi" / { chosen { environment { compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &env_sd4; }; }; }; @@ -31,7 +31,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@e0000 { + env_sd4: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6sx-udoo-neo-full.dts b/arch/arm/dts/imx6sx-udoo-neo-full.dts index 1609781b7f..12fd5073db 100644 --- a/arch/arm/dts/imx6sx-udoo-neo-full.dts +++ b/arch/arm/dts/imx6sx-udoo-neo-full.dts @@ -1,6 +1,10 @@ -#include <arm/imx6sx-udoo-neo-full.dts> +#include <arm/nxp/imx/imx6sx-udoo-neo-full.dts> +#include "imx6sx.dtsi" / { + + /delete-node/ memory@80000000; + chosen { environment { compatible = "barebox,environment"; @@ -27,3 +31,15 @@ &ocotp { barebox,provide-mac-address = <&fec1 0x620>; }; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 + MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts index 1139c4b7d6..a9a2581c0e 100644 --- a/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts @@ -1,4 +1,4 @@ -#include <arm/imx6ul-ccimx6ulsbcpro.dts> +#include <arm/nxp/imx/imx6ul-ccimx6ulsbcpro.dts> /{ chosen { @@ -6,7 +6,7 @@ environment-nand { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; status = "okay"; }; }; @@ -28,7 +28,7 @@ reg = <0x0 0x400000>; }; - partition@400000 { + env_nand: partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; diff --git a/arch/arm/dts/imx6ul-liteboard.dts b/arch/arm/dts/imx6ul-liteboard.dts index eb34e11ddb..f9ea9fc023 100644 --- a/arch/arm/dts/imx6ul-liteboard.dts +++ b/arch/arm/dts/imx6ul-liteboard.dts @@ -41,7 +41,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <arm/imx6ul-liteboard.dts> +#include <arm/nxp/imx/imx6ul-liteboard.dts> #include "imx6ul-litesom.dtsi" / { diff --git a/arch/arm/dts/imx6ul-mba6ulx.dtsi b/arch/arm/dts/imx6ul-mba6ulx.dtsi deleted file mode 100644 index da73248084..0000000000 --- a/arch/arm/dts/imx6ul-mba6ulx.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2016 TQ Systems GmbH - * Author: Marco Felsch - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "imx6ul-tqma6ulx.dtsi" - -/ { - model = "TQ TQMa6ULx SoM on MBa6ULx"; - compatible = "tq,mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - reg_mba6ul_3v3: regulator-mba6ul-3v3 { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6ul-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_mba6ul_5v0: regulator-mba6ul-5v0 { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6ul-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { - compatible = "regulator-fixed"; - gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "otg2-vbus-supply-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_mba6ul_5v0>; - }; - - reg_otg1vbus_5v0: regulator-otg1-vbus-5v0 { - compatible = "regulator-fixed"; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "otg1-vbus-supply-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_mba6ul_5v0>; - }; - - reg_fec_3v3: regulator-fec-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_mba6ul_3v3>; - }; - - reg_mpcie: regulator-mpcie-1v5 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - regulator-name = "mpcie-1v5"; - /* gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; */ - enable-active-high; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - vin-supply = <®_mba6ul_3v3>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <26>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - phy-reset-duration = <26>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <0>; - /* ToDo: check if following 2 lines are required */ - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <1>; - /* ToDo: check if following 2 lines are required */ - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander_io: gpio-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - - expander_in: gpio-expander@21 { - compatible = "nxp,pca9554"; - reg = <0x21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_expander_irq>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - - expander_out: gpio-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - - - /* NXP SE97BTP with temperature sensor + eeprom */ - jc42_1b: eeprom-temperature-sensor@1b { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x1b>; - status = "okay"; - }; - - se97_53: eeprom-temperature-sensor@53 { - compatible = "nxp,spd"; - reg = <0x53>; - pagesize = <16>; - status = "okay"; - }; - -}; - - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001b8b0 - MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001b8b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 - /* mdio */ - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_expander_irq: expanderirqgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 - MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 - /* PWR */ - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x0001b099 - >; - }; - - pinctrl_usb_otg2: usbotg2grp { - fsl,pins = < - /* reset */ - MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0001b099 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 - /* CD */ - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* otg-port */ -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - vbus-supply = <®_otg1vbus_5v0>; - dr_mode = "otg"; - status = "okay"; -}; - -/* 7-port usb hub */ -/* id, pwr, oc pins not connected */ -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - disable-over-current; - vbus-supply = <®_otg2vbus_5v0>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - vmmc-supply = <®_mba6ul_3v3>; - vqmmc-supply = <®_vccsd>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts index 50ce75f12b..b30cd60aa6 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6ul.dtsi> +#include <arm/nxp/imx/imx6ul.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-state.dtsi" diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts index c8d43c5e25..c8be386e7f 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6ul.dtsi> +#include <arm/nxp/imx/imx6ul.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-state.dtsi" diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index c7c657bcd4..4aea8c1d38 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -16,19 +16,19 @@ environment-nand { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &env_nand; status = "disabled"; }; environment-sd1 { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; + device-path = &env_sd1; status = "disabled"; }; environment-sd2 { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; }; @@ -67,7 +67,7 @@ reg = <0x0 0x400000>; }; - partition@400000 { + env_nand: partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; @@ -125,7 +125,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd1: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -146,7 +146,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi index 78a32ed96b..d0cad1b516 100644 --- a/arch/arm/dts/imx6ul-phytec-state.dtsi +++ b/arch/arm/dts/imx6ul-phytec-state.dtsi @@ -18,29 +18,27 @@ backend-stridesize = <54>; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; bootstate { #address-cells = <1>; #size-cells = <1>; - last_chosen { + last_chosen@0 { reg = <0x0 0x4>; type = "uint32"; }; system0 { #address-cells = <1>; #size-cells = <1>; - remaining_attempts { + remaining_attempts@4 { reg = <0x4 0x4>; type = "uint32"; default = <3>; }; - priority { + priority@8 { reg = <0x8 0x4>; type = "uint32"; default = <21>; }; - ok { + ok@c { reg = <0xc 0x4>; type = "uint32"; default = <0>; @@ -49,17 +47,17 @@ system1 { #address-cells = <1>; #size-cells = <1>; - remaining_attempts { + remaining_attempts@10 { reg = <0x10 0x4>; type = "uint32"; default = <3>; }; - priority { + priority@14 { reg = <0x14 0x4>; type = "uint32"; default = <20>; }; - ok { + ok@18 { reg = <0x18 0x4>; type = "uint32"; default = <0>; diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts index 0c543de8c9..3deb89c448 100644 --- a/arch/arm/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/dts/imx6ul-pico-hobbit.dts @@ -1,4 +1,4 @@ -#include <arm/imx6ul-pico-hobbit.dts> +#include <arm/nxp/imx/imx6ul-pico-hobbit.dts> / { chosen { diff --git a/arch/arm/dts/imx6ul-prti6g.dts b/arch/arm/dts/imx6ul-prti6g.dts index f720a2518c..262a96742b 100644 --- a/arch/arm/dts/imx6ul-prti6g.dts +++ b/arch/arm/dts/imx6ul-prti6g.dts @@ -1,26 +1,15 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include <arm/imx6ul-prti6g.dts> +#include <arm/nxp/imx/imx6ul-prti6g.dts> / { chosen { stdout-path = &uart4; - environment@0 { + environment { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address will be determined by the bootloader */ - ramoops { - compatible = "ramoops"; + device-path = &env_sd2; }; }; @@ -52,7 +41,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@40000 { + env_sd2: partition@40000 { label = "barebox-environment"; reg = <0x40000 0x80000>; }; diff --git a/arch/arm/dts/imx6ul-mba6ulx.dts b/arch/arm/dts/imx6ul-tqma6ul-common.dtsi index e2ed694ff9..5ff318fcfc 100644 --- a/arch/arm/dts/imx6ul-mba6ulx.dts +++ b/arch/arm/dts/imx6ul-tqma6ul-common.dtsi @@ -1,13 +1,10 @@ - // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright 2021 Pengutronix e.K. * Author: Rouven Czerwinski */ -/dts-v1/; - -#include "imx6ul-mba6ulx.dtsi" +#include "imx6ul.dtsi" / { chosen { @@ -30,11 +27,6 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - environment_emmc: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; diff --git a/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 0000000000..2d49c0e763 --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts> +#include "imx6ul-tqma6ul-common.dtsi" diff --git a/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 0000000000..2d49c0e763 --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts> +#include "imx6ul-tqma6ul-common.dtsi" diff --git a/arch/arm/dts/imx6ul-tqma6ulx.dtsi b/arch/arm/dts/imx6ul-tqma6ulx.dtsi deleted file mode 100644 index 77112e1974..0000000000 --- a/arch/arm/dts/imx6ul-tqma6ulx.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018 TQ Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include <arm/imx6ul.dtsi> -#include "tqma6ul-common.dtsi" -#include "tqma6ulx-common.dtsi" - -/ { - model = "TQMa6ULx SOM"; -}; - -&cpu0 { - cooling-min-level = <0>; - cooling-max-level = <3>; - #cooling-cells = <2>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; - -&usdhc2 { - fsl,tuning-step= <6>; - max-frequency = <99000000>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; -}; diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dts b/arch/arm/dts/imx6ul-webasto-ccbv2.dts index 93e9445b48..198088bd44 100644 --- a/arch/arm/dts/imx6ul-webasto-ccbv2.dts +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dts @@ -32,8 +32,6 @@ }; state_emmc: state { - #address-cells = <1>; - #size-cells = <1>; compatible = "barebox,state"; magic = <0x290cf8c6>; backend-type = "raw"; diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi index 829485de32..5207abea0c 100644 --- a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi @@ -6,7 +6,7 @@ /dts-v1/; -#include <arm/imx6ul.dtsi> +#include <arm/nxp/imx/imx6ul.dtsi> / { model = "Webasto common communication board version 2"; diff --git a/arch/arm/dts/imx6ul-webasto-marvel.dts b/arch/arm/dts/imx6ul-webasto-marvel.dts index b8ecb00c8c..7b5641afbc 100644 --- a/arch/arm/dts/imx6ul-webasto-marvel.dts +++ b/arch/arm/dts/imx6ul-webasto-marvel.dts @@ -8,7 +8,7 @@ /dts-v1/; -#include <arm/imx6ul.dtsi> +#include <arm/nxp/imx/imx6ul.dtsi> / { model = "Webasto common communication board Marvel MK3"; @@ -38,8 +38,6 @@ }; state_emmc: state { - #address-cells = <1>; - #size-cells = <1>; compatible = "barebox,state"; magic = <0x290cf8c6>; backend-type = "raw"; diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi new file mode 100644 index 0000000000..7d600f505b --- /dev/null +++ b/arch/arm/dts/imx6ul.dtsi @@ -0,0 +1,6 @@ +/ { + aliases { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + }; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 6712e10739..ad283ca968 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -1,4 +1,4 @@ -#include <arm/imx6ull-14x14-evk.dts> +#include <arm/nxp/imx/imx6ull-14x14-evk.dts> /{ chosen { diff --git a/arch/arm/dts/imx6ull-jozacp.dts b/arch/arm/dts/imx6ull-jozacp.dts index f41028455a..612dac67ca 100644 --- a/arch/arm/dts/imx6ull-jozacp.dts +++ b/arch/arm/dts/imx6ull-jozacp.dts @@ -7,20 +7,9 @@ chosen { stdout-path = &uart1; - environment@0 { + environment { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address will be determined by the bootloader */ - ramoops { - compatible = "ramoops"; + device-path = &env_sd1; }; }; @@ -40,7 +29,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@40000 { + env_sd1: partition@40000 { label = "barebox-environment"; reg = <0x40000 0x80000>; }; diff --git a/arch/arm/dts/imx6ull-jozacp.dtsi b/arch/arm/dts/imx6ull-jozacp.dtsi index f7d35684f8..b3529795b8 100644 --- a/arch/arm/dts/imx6ull-jozacp.dtsi +++ b/arch/arm/dts/imx6ull-jozacp.dtsi @@ -14,7 +14,7 @@ /dts-v1/; -#include <arm/imx6ull.dtsi> +#include <arm/nxp/imx/imx6ull.dtsi> #include <dt-bindings/gpio/gpio.h> / { @@ -30,48 +30,42 @@ reg = <0x80000000 0x10000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_5v: 5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "regulator-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_5v: 5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - reg_3p3v: 3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "regulator-3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_5v>; - regulator-always-on; - }; + reg_3p3v: 3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v>; + regulator-always-on; + }; - reg_1p4v: 1p4-regulator { - compatible = "regulator-fixed"; - regulator-name = "regulator-1P4V"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <1400000>; - vin-supply = <®_5v>; - regulator-always-on; - }; + reg_1p4v: 1p4-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-1P4V"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <1400000>; + vin-supply = <®_5v>; + regulator-always-on; + }; - reg_vbus: vbus-regulator { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vbus>; - compatible = "regulator-fixed"; - regulator-name = "regulator-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_vbus: vbus-regulator { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vbus>; + compatible = "regulator-fixed"; + regulator-name = "regulator-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; }; usdhc2_pwrseq: usdhc2-pwrseq { diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts index afd99a3fd9..81f8aea245 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6ull.dtsi> +#include <arm/nxp/imx/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-state.dtsi" diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts index 9c912df4de..b76b60220d 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6ull.dtsi> +#include <arm/nxp/imx/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" / { diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts index 224e853e1a..3906e554d5 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts @@ -8,7 +8,7 @@ #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY #include CONFIG_BOOTM_FITIMAGE_PUBKEY #endif -#include <arm/imx6ull.dtsi> +#include <arm/nxp/imx/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-state.dtsi" diff --git a/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 0000000000..20eb7a7c1d --- /dev/null +++ b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts> +#include "imx6ul-tqma6ul-common.dtsi" diff --git a/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 0000000000..58df3349c7 --- /dev/null +++ b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts> +#include "imx6ul-tqma6ul-common.dtsi" diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi new file mode 100644 index 0000000000..1c67bdc546 --- /dev/null +++ b/arch/arm/dts/imx7.dtsi @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include "imx7d-ddrc.dtsi" + +/ { + aliases { + gpr.reboot_mode = &reboot_mode_gpr; + }; +}; + +&src { + compatible = "fsl,imx7d-src", "syscon", "simple-mfd"; + + reboot_mode_gpr: reboot-mode { + compatible = "barebox,syscon-reboot-mode"; + offset = <0x94>, <0x98>; /* SRC_GPR{9,10} */ + mask = <0xffffffff>, <0x40000000>; + mode-normal = <0>, <0>; + mode-serial = <0x00000010>, <0x40000000>; + }; + + ca7_reset: cortex-a7-reboot { + compatible = "syscon-reboot"; + regmap = <&src>; + offset = <0x4>; + mask = <1>; + value = <1>; + /* This is not fit for use as general purpose reset */ + restart-priority = <5>; + /* + * Can't use imxwd-warm due to errata e10574: + * Watchdog: A watchdog timeout or software trigger will + * not reset the SOC + */ + barebox,restart-warm-bootrom; + }; +}; diff --git a/arch/arm/dts/imx7d-ac-sxb.dtsi b/arch/arm/dts/imx7d-ac-sxb.dtsi index 00b0fd11c6..7154508d07 100644 --- a/arch/arm/dts/imx7d-ac-sxb.dtsi +++ b/arch/arm/dts/imx7d-ac-sxb.dtsi @@ -6,7 +6,7 @@ /dts-v1/; -#include <arm/imx7d.dtsi> +#include <arm/nxp/imx/imx7d.dtsi> / { model = "Atlas Copco SXB Board"; @@ -41,9 +41,15 @@ keep-power-in-suspend; status = "okay"; - usdhc1_sdcard: state@4100000 { - reg = <0x4100000 0xffffff>; - label = "state-sdcard"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + usdhc1_sdcard: state@4100000 { + reg = <0x0 0x4100000 0x0 0xffffff>; + label = "state-sdcard"; + }; }; }; @@ -56,11 +62,16 @@ non-removable; status = "okay"; - usdhc3_emmc: usdhc3_emmc@1e800000 { - reg = <0x1e800000 0xffffff>; - label = "state-emmc"; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + usdhc3_emmc: usdhc3_emmc@1e800000 { + reg = <0x0 0x1e800000 0x0 0xffffff>; + label = "state-emmc"; + }; + }; }; &wdog1 { diff --git a/arch/arm/dts/imx7d-ddrc.dtsi b/arch/arm/dts/imx7d-ddrc.dtsi index b4cd597be9..875fff690b 100644 --- a/arch/arm/dts/imx7d-ddrc.dtsi +++ b/arch/arm/dts/imx7d-ddrc.dtsi @@ -1,10 +1,12 @@ /* * Include file to switch board DTS form using hardcoded memory node - * to dynamic memory size detection based on DDR controller settings + * (if specified) to dynamic memory size detection based on DDR + * controller settings */ / { /delete-node/ memory; + /delete-node/ memory@80000000; }; &aips2 { @@ -12,4 +14,4 @@ compatible = "fsl,imx7d-ddrc"; reg = <0x307a0000 0x10000>; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/dts/imx7d-flex-concentrator-mfg.dts index d174ef7250..4b150ba48c 100644 --- a/arch/arm/dts/imx7d-flex-concentrator-mfg.dts +++ b/arch/arm/dts/imx7d-flex-concentrator-mfg.dts @@ -7,7 +7,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx7d-flex-concentrator-mfg.dts> +#include <arm/nxp/imx/imx7d-flex-concentrator-mfg.dts> / { chosen { diff --git a/arch/arm/dts/imx7d-gome-e143_01.dts b/arch/arm/dts/imx7d-gome-e143_01.dts new file mode 100644 index 0000000000..ea118ddc76 --- /dev/null +++ b/arch/arm/dts/imx7d-gome-e143_01.dts @@ -0,0 +1,119 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix + */ + +/dts-v1/; + +#include "imx7d-gome-e143_01.kernel.dts" + +/ { + compatible = "gome,e143_01", "variscite,var-som-mx7", "fsl,imx7d"; + + aliases { + state = &state; + }; + + chosen { + stdout-path = &uart1; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &emmc_env; + }; + }; + + state: state { + #address-cells = <1>; + #size-cells = <1>; + magic = <0x1929603f>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&emmc_state>; + backend-stridesize = <0x80>; + backend-storage-type = "direct"; + + bootstate: bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <10>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&usdhc3 { + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + /** original storage layout: + offset size label + 000000000 512 MBR + 000000200 512 (empty) + 000000400 68k SPL + 000011400 800k u-boot + 0000E0000 3.2M u-boot-env (only first 8k are used) + 000400000 2.9G rootfs1 + 0BA400000 2.9G rootfs2 + 174400000 1.5G data + 1D2000000 (end) + + Keep the original layout for now for possible fallback to u-boot + later; put the storage for barebox-env and barebox-state + somewhere where it doesn't conflict with u-boot. + */ + + emmc_state: partition@200000 { + label = "barebox-state"; + reg = <0x200000 0x100000>; + }; + + emmc_env: partition@300000 { + label = "barebox-environment"; + reg = <0x300000 0x100000>; + }; + }; +}; + +&{/leds2/led_netz_rt} { + barebox,default-trigger = "default-on"; +}; diff --git a/arch/arm/dts/imx7d-gome-e143_01.kernel.dts b/arch/arm/dts/imx7d-gome-e143_01.kernel.dts new file mode 100644 index 0000000000..19c7a3d426 --- /dev/null +++ b/arch/arm/dts/imx7d-gome-e143_01.kernel.dts @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0-only +/** + * Copyright (C) 2022 Gossen Metrawatt GmbH + * Copyright (C) 2022 Marco Felsch, Pengutronix + * Copyright (C) 2022 Philipp Zabel, Pengutronix + * Copyright (C) 2022 Roland Hieber, Pengutronix + */ +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "imx7d-var-som-mx7.dtsi" + +/ { + model = "Gossen Metrawatt Profitest MF (e143_01)"; + compatible = "gome,e143_01", "variscite,var-som-mx7", "fsl,imx7d"; + + aliases { + gpio7 = &gpio8; + rtc0 = &rtc0; + }; + + max98357a: audio-codec { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmode>; + sdmode-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; // Pin 60 AUDIO_SHDN_B + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>, <&pinctrl_gpio_keys_2>; + autorepeat; + + button-0 { + label = "S0"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; // Pin 183 BTN_S0_ESC + linux,code = <KEY_ESC>; + wakeup-source; + }; + + button-1 { + label = "S1"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; // Pin 185 BTN_S1_MEM + linux,code = <KEY_DOCUMENTS>; + wakeup-source; + }; + + button-2 { + label = "S2"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; // Pin 181 BTN_S2_HLP + linux,code = <KEY_HELP>; + wakeup-source; + }; + + button-3 { + label = "S3"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; // Pin 1 BTN_S3_STA + linux,code = <KEY_PROG1>; + wakeup-source; + }; + + button-4 { + label = "S4"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; // Pin 168 BTN_S4_IDN + linux,code = <KEY_PROG2>; + wakeup-source; + }; + + button-5 { + label = "S5"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; // Pin 28 BTN_S5 + linux,code = <KEY_F5>; + }; + + button-6 { + label = "S6"; + gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; // Pin 40 BTN_S6 + linux,code = <KEY_F6>; + }; + + button-7 { + label = "S7"; + gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; // Pin 38 BTN_S7 + linux,code = <KEY_F7>; + }; + + button-8 { + label = "S8"; + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; // Pin 36 BTN_S8 + linux,code = <KEY_F8>; + }; + + button-9 { + label = "S9"; + gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; // Pin 20 BTN_S9 + linux,code = <KEY_F9>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_poweroff>; + gpios = <&gpio7 14 GPIO_ACTIVE_LOW>; // Pin 7 POWER_OFF_B + input; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc2 0>, // ARS_VAL + <&adc2 1>, // VBAT_VAL + <&adc2 2>, // LCD_BACKLIGHT_VAL + <&adc2 3>; // VCC_5V0_FB + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_debug_led>; + + test-led-1 { + label = "test-led-1:red"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; // Pin 44 LED_TEST1_B + color = <LED_COLOR_ID_RED>; + linux,default-trigger = "disk-activity"; + }; + + test-led-2 { + label = "test-led-2:red"; + gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; // Pin 46 LED_TEST2_B + color = <LED_COLOR_ID_RED>; + linux,default-trigger = "heartbeat"; + }; + }; + + leds2 { + compatible = "gpio-leds"; + + led_netz_gn { + label = "mains:green"; + gpios = <&gpio8 9 GPIO_ACTIVE_LOW>; // LED_NETZ_GN + color = <LED_COLOR_ID_GREEN>; + }; + + led_netz_rt { + label = "mains:red"; + gpios = <&gpio8 8 GPIO_ACTIVE_LOW>; // LED_NETZ_RT + color = <LED_COLOR_ID_RED>; + default-state = "on"; + }; + + led_debug_gn { + label = "debug:green"; + gpios = <&gpio8 0 GPIO_ACTIVE_LOW>; // LED_DEBUG_GN + color = <LED_COLOR_ID_GREEN>; + }; + + led_debug_rt { + label = "debug:red"; + gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; // LED_DEBUG_RT + color = <LED_COLOR_ID_RED>; + }; + + led_ul_gn { + label = "ulrl:green"; + gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; // LED_UL_GN + color = <LED_COLOR_ID_GREEN>; + }; + + led_ul_rt { + label = "ulrl:red"; + gpios = <&gpio8 6 GPIO_ACTIVE_LOW>; // LED_UL_RT + color = <LED_COLOR_ID_RED>; + default-state = "on"; + }; + + led_rcd_gn { + label = "rcd:green"; + gpios = <&gpio8 3 GPIO_ACTIVE_LOW>; // LED_RCD_GN + color = <LED_COLOR_ID_GREEN>; + }; + + led_rcd_rt { + label = "rcd:red"; + gpios = <&gpio8 7 GPIO_ACTIVE_LOW>; // LED_RCD_RT + color = <LED_COLOR_ID_RED>; + default-state = "on"; + }; + }; + + reg_vled_backlight: regulator-vled-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_backlight>; + regulator-name = "VLED_BACKLIGHT"; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <20000000>; + regulator-max-microvolt = <20000000>; + enable-active-high; + }; + + reg_vcc_3v3_per: regulator-vcc-3v3-per { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vcc_3v3_per>; + regulator-name = "VCC_3V3_PER"; + gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; // Pin 83 VCC_3V3_PER_EN + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <30000>; + enable-active-high; + regulator-always-on; + }; + + reg_vcc_5v0_per: regulator-vcc-5v0-per { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vcc_5v0_per>; + regulator-name = "VCC_5V0_PER"; + gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; // Pin 75 VCC_5V0_PER_EN + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + reg_imt: regulator-imt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_imt>; + regulator-name = "VCC_IMT"; + gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; // Pin 66 MT_EN + regulator-min-microvolt = <9000000>; + regulator-max-microvolt = <9000000>; + enable-active-high; + }; + + reg_vcc_1v8_alg: regulator-vcc-1v8-alg { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_ALG"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vcc_3v3_per>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "max98357aaudio"; + /delete-property/ simple-audio-card,widgets; + /delete-property/ simple-audio-card,routing; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&max98357a>; + }; + }; + + uc-imt-power { + compatible = "reg-userspace-consumer"; + regulator-name = "reg_imt-consumer"; + regulator-supplies = "vcc"; + vcc-supply = <®_imt>; + }; +}; + +&adc2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c2 { + /delete-node/ wm8731@1a; + + /* DS1339 RTC module */ + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + trickle-resistor-ohms = <250>; + interrupt-parent = <&gpio1>; + interrupts = <13 GPIO_ACTIVE_LOW>; // Pin 120 RTC_INT_B + wakeup-source; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; // Pin 175 I2C4_SCL + sda-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; // Pin 173 I2C4_SDA + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + gpio8: max7312@23 { + compatible = "maxim,max7312"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "LED_DEBUG_GN", "LED_DEBUG_RT", "LED_UL_GN", "LED_RCD_GN", + "", "", "LED_UL_RT", "LED_RCD_RT", + "LED_NETZ_RT", "LED_NETZ_GN", "", "", + "DP_HW_CODE_1", "DP_HW_CODE_2", "DP_HW_CODE_3", "DP_HW_CODE_4"; + vcc-supply = <®_vcc_3v3_per>; + }; +}; + +&gpio1 { + gpio-line-names = "GWDOG_RST_B", "BTN_S3_STA", "BTN_S4_IDN", "", + "", "", "", "USB_HOST_PWR_EN", + "", "", "BTN_S2_HLP", "BTN_S1_MEM", + "BTN_S0_ESC", "RTC_INT_B", "SOM: bt reg on"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "DBG_GPIO1", "DBG_GPIO2", "DBG_GPIO3", "DBG_GPIO4", + "", "", "", "", + "MT_RXD", "MT_TXD", "", "", + "", "", "", "", + "", "", "", "", + "", "", "VCC_3V3_PER_EN", "", + "DSI_RESET", "VCC_5V0_PER_EN"; +}; + +&gpio3 { + gpio-line-names = "", "", "LED_TEST1_B", "LED_TEST2_B", + "BTN_S8", "BTN_S6", "MT_RESET", "", + "", "", "MT_EN", "", + "", "", "", "", + "", "", "", "", + "AUDIO_SHDN_B", "", "BTN_S7", "", + "BTN_S5", "", "", "BTN_S9", + "BATT_LOW"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "I2C1_SCL", "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", + "", "", "I2C4_SCL", "I2C4_SDA", + "", "", "", "", + "", "", "", "HIL_SPI_CS0"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "SOM: ethphy0 reset"; +}; + +&gpio6 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "SOM: sd3_pwr (eMMC)"; +}; + +&gpio7 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "LCD_BACKLIGHT_EN", "", "POWER_OFF_B"; +}; + +&lcdif { + assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>, + <&clks IMX7D_PLL_VIDEO_POST_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; + assigned-clock-rates = <0>, <128000000>; + fsl,ocram = <&ocram>; + fsl,pxp = <&pxp>; + status = "okay"; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <850000000>; + status = "okay"; + + panel@0 { + compatible = "tianma,tm050jdhg33", "ilitek,ili9881c"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_panel>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; // Pin 73 DSI_RESET + power-supply = <®_vcc_3v3_per>; + dsi-lanes = <2>; + + rotation = <90>; + + ilitek,enable-internal-backlight; + default-brightness = <2047>; + ilitek,pwm-frequency = <50000>; + ilitek,backlight-supply = <®_vled_backlight>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl_gpio_keys_2: pinctrl_gpio_keys_2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0C + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0C + >; + }; + + pinctrl_usbotg2_pwr: pinctrl_usbotg2_pwrgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: pinctrl-gpio-keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x0000000C + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0000000C + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0000000C + MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x0000000C + MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x0000000C + MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0000000C + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0000000C + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x0000000C + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x4000007f + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x4000007f + >; + }; + + pinctrl_mipi_backlight: mipi-backlightgrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x0000001B + >; + }; + + pinctrl_mipi_panel: mipi-panelgrp { + fsl,pins = < + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x0000001B /* DSI_RESET */ + >; + }; + + pinctrl_poweroff: pinctrl_poweroffgrp { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0000001B + >; + }; + + pinctrl_reg_vcc_3v3_per: pinctrl_reg_vcc_3v3_pergrp { + fsl,pins = < + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x0000001B + >; + }; + + pinctrl_reg_vcc_5v0_per: pinctrl_reg_vcc_5v0_pergrp { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x0000001B + >; + }; + + pinctrl_reg_imt: pinctrl_reg_imtgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x0000001B + >; + }; + + pinctrl_rtc: pinctrl_rtcgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0000001B + >; + }; + + pinctrl_sai3: pinctrl_sai3grp { + fsl,pins = < + MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x0000001F + MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x0000001F + MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x00000030 + >; + }; + + pinctrl_sdmode: pinctrl_sdmodegrp { + fsl,pins = < + MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0000001F + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 /* DEBUG_UART1_TXD */ + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 /* DEBUG_UART1_RXD */ + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x79 + >; + }; + + pinctrl_debug_led: pinctrl_debug_ledgrp { + fsl,pins = < + MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00000003 + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00000003 + >; + }; +}; diff --git a/arch/arm/dts/imx7d-meerkat96.dts b/arch/arm/dts/imx7d-meerkat96.dts new file mode 100644 index 0000000000..da3a3a6dfc --- /dev/null +++ b/arch/arm/dts/imx7d-meerkat96.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +#include <arm/nxp/imx/imx7d-meerkat96.dts> + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &bareboxenv; + }; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x0 0x180000>; + }; + + bareboxenv: bareboxenv@180000 { + label = "bareboxenv"; + reg = <0x180000 0x80000>; + }; +}; + +/* FIXME: barebox serial is broken when barebox applies requested reparenting */ +&uart1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; + +&uart3 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; + +&uart6 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; diff --git a/arch/arm/dts/imx7d-peb-av-02.dtsi b/arch/arm/dts/imx7d-peb-av-02.dtsi index dcf117c71a..2e5af755bb 100644 --- a/arch/arm/dts/imx7d-peb-av-02.dtsi +++ b/arch/arm/dts/imx7d-peb-av-02.dtsi @@ -72,7 +72,7 @@ lcd-supply = <&lcd_3v3>; status = "disabled"; - display0: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/dts/imx7d-peb-eval-02.dtsi b/arch/arm/dts/imx7d-peb-eval-02.dtsi index 8bde5b13e7..fee0c5972d 100644 --- a/arch/arm/dts/imx7d-peb-eval-02.dtsi +++ b/arch/arm/dts/imx7d-peb-eval-02.dtsi @@ -13,21 +13,21 @@ pinctrl-0 = <&pinctrl_leds_eval>; status = "disabled"; - led@0 { + led-0 { label = "eval_led_1"; gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "on"; }; - led@1 { + led-1 { label = "eval_led_2"; gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "on"; }; - led@2 { + led-2 { label = "eval_led_3"; gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; @@ -41,18 +41,18 @@ pinctrl-0 = <&pinctrl_btns_eval>; status = "disabled"; - userbtn@0 { + userbtn-0 { label = "eval_button_1"; gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; /* BTN_MISC */ }; - userbtn@1 { + userbtn-1 { label = "eval_button_2"; gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; /* BTN_MISC */ }; - userbtn@2 { + userbtn-2 { label = "eval_button_3"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; /* BTN_MISC */ diff --git a/arch/arm/dts/imx7d-phycore-som.dtsi b/arch/arm/dts/imx7d-phycore-som.dtsi index e892a54bdd..2dedac83bd 100644 --- a/arch/arm/dts/imx7d-phycore-som.dtsi +++ b/arch/arm/dts/imx7d-phycore-som.dtsi @@ -7,7 +7,7 @@ */ #include <dt-bindings/input/input.h> -#include <arm/imx7d.dtsi> +#include <arm/nxp/imx/imx7d.dtsi> / { model = "Phytec i.MX7D phyCORE"; diff --git a/arch/arm/dts/imx7d-pinfunc.kernel.h b/arch/arm/dts/imx7d-pinfunc.kernel.h new file mode 100644 index 0000000000..141192404b --- /dev/null +++ b/arch/arm/dts/imx7d-pinfunc.kernel.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DTS_IMX7D_PINFUNC_KERNEL_H +#define __DTS_IMX7D_PINFUNC_KERNEL_H + +#define MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT 0x000C 0x003C 0x0000 0x4 0x0 + +#endif /* __DTS_IMX7D_PINFUNC_KERNEL_H */ diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 7beb065920..b947e44634 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -7,7 +7,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx7d-sdb.dts> +#include <arm/nxp/imx/imx7d-sdb.dts> / { chosen { diff --git a/arch/arm/dts/imx7d-var-som-mx7.dtsi b/arch/arm/dts/imx7d-var-som-mx7.dtsi new file mode 100644 index 0000000000..029f874e89 --- /dev/null +++ b/arch/arm/dts/imx7d-var-som-mx7.dtsi @@ -0,0 +1,6 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * SPDX-FileCopyrightText: 2023 Roland Hieber, Pengutronix <rhi@pengutronix.de> + */ +#include "imx7d-var-som-mx7.kernel.dtsi" +#include "imx7d-ddrc.dtsi" diff --git a/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi b/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi new file mode 100644 index 0000000000..591436ffc6 --- /dev/null +++ b/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2016-2017 Variscite Ltd. + * Copyright (C) 2022 Philipp Zabel, Pengutronix + * Copyright (C) 2022 Roland Hieber, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/input/input.h> +#include "imx7d.kernel.dtsi" + +/ { + model = "Variscite i.MX7 Dual VAR-SOM-MX7"; + compatible = "variscite,var-som-mx7", "fsl,imx7d"; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usbotg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wlreg_on: regulator-wlreg-on { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlreg_on"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8731audio"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Jack", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line Jack", + "RLINEIN", "Line Jack", + "MICIN", "Mic Bias", + "Mic Bias", "Mic Jack"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + sound_master: simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8731>; + system-clock-frequency = <12288000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <&vgen3_reg>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <20>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-supply = <&vgen3_reg>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <20>; +}; + +&gpio6 { + sd3-pwr-hog { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "sd3_pwr"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + status = "disabled"; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "rohm,br24g04", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + num-addresses = <2>; + address-width = <8>; + read-only; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8731: wm8731@1a { + #sound-dai-cells = <0>; + AVDD-supply = <&vgen6_reg>; + HPVDD-supply = <&vgen6_reg>; + DBVDD-supply = <&vgen6_reg>; + DCVDD-supply = <&vgen6_reg>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <12288000>; + }; +}; + +&sai1 { + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <12288000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&uart2 { + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&uart3 { + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_wlan>, <&pinctrl_bt>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_wlan>, <&pinctrl_bt>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_wlan>, <&pinctrl_bt>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_wlan_sleep>, <&pinctrl_bt_sleep>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <&wlreg_on>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&vgen3_reg>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + no-1-8-v; + no-sdio; + no-sd; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc_lpsr { + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2-vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x09 /* WL_REG_ON */ + MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT 0xb0 /* WIFI Slow clock */ + >; + }; + + pinctrl_wlan_sleep: wlan-sleepgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x10 /* WL_REG_ON */ + MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT 0x10 /* WIFI Slow clock */ + >; + }; +}; + +&iomuxc { + + pinctrl_bt: btgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x80000000 /* bt reg on */ + >; + }; + + pinctrl_bt_sleep: bt-sleepgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x10 /* bt reg on */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 /* ethphy0 reset */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x59 /* ethphy1 reset */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x10 + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x10 + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x10 + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x10 + MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x10 + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x10 + >; + }; + + pinctrl_usdhc3_ctrl: usdhc3-ctrlgrp { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; +}; diff --git a/arch/arm/dts/imx7d-zii-rmu2.dts b/arch/arm/dts/imx7d-zii-rmu2.dts index 41566f54a1..64da9cf55d 100644 --- a/arch/arm/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/dts/imx7d-zii-rmu2.dts @@ -4,7 +4,7 @@ * Copyright (C) 2019 Zodiac Inflight Innovations */ -#include <arm/imx7d-zii-rmu2.dts> +#include <arm/nxp/imx/imx7d-zii-rmu2.dts> #include "imx7d-ddrc.dtsi" /* FIXME: barebox serial is broken when barebox applies requested reparenting */ @@ -18,37 +18,28 @@ /delete-property/ assigned-clock-parents; }; -&ecspi1 { - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; +nor_flash: &{ecspi1/flash@0} { + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xc0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xc0000>; + }; - partition@c0000 { - label = "barebox-environment"; - reg = <0xc0000 0x40000>; - }; + partition@c0000 { + label = "barebox-environment"; + reg = <0xc0000 0x40000>; }; }; -&uart4 { - rave-sp { - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - nvmem-cells = <&boot_source>; - nvmem-cell-names = "boot-source"; - }; - - eeprom@a3 { - boot_source: boot-source@83 { - reg = <0x83 1>; - }; - }; +&{uart4/mcu/watchdog} { + nvmem-cells = <&boot_source>; + nvmem-cell-names = "boot-source"; +}; + +&{uart4/mcu/eeprom@a3} { + boot_source: boot-source@83 { + reg = <0x83 1>; }; }; diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts index 58b22aa8e8..d8a5ffd194 100644 --- a/arch/arm/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/dts/imx7d-zii-rpu2.dts @@ -3,7 +3,7 @@ /* * Copyright (C) 2018 Zodiac Inflight Innovations */ -#include <arm/imx7d-zii-rpu2.dts> +#include <arm/nxp/imx/imx7d-zii-rpu2.dts> #include "imx7d-ddrc.dtsi" diff --git a/arch/arm/dts/imx7d.kernel.dtsi b/arch/arm/dts/imx7d.kernel.dtsi new file mode 100644 index 0000000000..bc066b71a3 --- /dev/null +++ b/arch/arm/dts/imx7d.kernel.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Freescale Semiconductor, Inc. +// Copyright 2016 Toradex AG + +#include "imx7s.kernel.dtsi" +#include <dt-bindings/reset/imx7-reset.h> + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + + cpus { + cpu0: cpu@0 { + clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&fuse_grade>; + nvmem-cell-names = "speed_grade"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep_wait>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xd>, <0x7>; + opp-suspend; + }; + + opp-996000000 { + opp-hz = /bits/ 64 <996000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xc>, <0x7>; + opp-suspend; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0x8>, <0x3>; + opp-suspend; + }; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + soc: soc { + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx7d-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + /* + * Reference manual lists pci irqs incorrectly + * Real hardware ordering is same as imx6: D+MSI, C, B, A + */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + }; +}; + +&aips2 { + pcie_phy: pcie-phy@306d0000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x306d0000 0x10000>; + status = "disabled"; + }; + + pxp: pxp@30700000 { + compatible = "fsl,imx7d-pxp"; + reg = <0x30700000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PXP_CLK>; + clock-names = "axi"; + }; +}; + +&aips3 { + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; +}; + +&ca_funnel_in_ports { + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; +}; diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts index 8e645999cf..3cae11b6a2 100644 --- a/arch/arm/dts/imx7s-warp.dts +++ b/arch/arm/dts/imx7s-warp.dts @@ -7,7 +7,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx7s-warp.dts> +#include <arm/nxp/imx/imx7s-warp.dts> / { chosen { diff --git a/arch/arm/dts/imx7s.kernel.dtsi b/arch/arm/dts/imx7s.kernel.dtsi new file mode 100644 index 0000000000..6ea9e05f7b --- /dev/null +++ b/arch/arm/dts/imx7s.kernel.dtsi @@ -0,0 +1,1354 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2015 Freescale Semiconductor, Inc. +// Copyright 2016 Toradex AG + +#include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/power/imx7-power.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/imx7-reset.h> +#include <arm/nxp/imx/imx7d-pinfunc.h> +#include "imx7d-pinfunc.kernel.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_sleep_wait: cpu-sleep-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <50>; + min-residency-us = <1000>; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <792000000>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_CLK_ARM>; + cpu-idle-states = <&cpu_sleep_wait>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&fuse_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xf>, <0xf>; + }; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + power-domains = <&pgc_hsic_phy>; + #phy-cells = <0>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + funnel@30041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ca_funnel_in_ports: in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M4 input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + aips1: bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 13 32>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 45 29>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 74 24>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 98 18>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 116 23>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 139 16>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: watchdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: watchdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: pinctrl@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + gpt1: timer@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_GPT2_ROOT_CLK>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: timer@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_GPT3_ROOT_CLK>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: timer@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; + reg = <0x30300000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_GPT4_ROOT_CLK>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + kpp: keypad@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_KPP_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; + reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x14 0x00000010>; + }; + + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; + }; + + ocotp: efuse@30350000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + + tempmon_calib: calib@3c { + reg = <0x3c 0x4>; + }; + + fuse_grade: fuse-grade@10 { + reg = <0x10 0x4>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + reg_1p0d: regulator-vdd1p0d { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <0>; + }; + + reg_1p2: regulator-vdd1p2 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&fuse_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + status = "disabled"; + }; + }; + + clks: clock-controller@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: reset-controller@30390000 { + compatible = "fsl,imx7d-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = <1>; + power-supply = <®_1p0d>; + }; + + pgc_hsic_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + power-supply = <®_1p2>; + }; + }; + }; + }; + + aips2: bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc@30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc2: adc@30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + ecspi4: spi@30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ftm1: pwm@30640000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0x30640000 0x10000>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; + status = "disabled"; + }; + + ftm2: pwm@30650000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0x30650000 0x10000>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, + <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <3>; + status = "disabled"; + }; + + csi: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>; + clock-names = "mclk"; + status = "disabled"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; + + lcdif: lcdif@30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; + clock-names = "pix", "axi"; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + lcdif_out_mipi_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_dsi_in_lcdif>; + }; + }; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; + }; + + mipi_dsi: dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30760000 0x400>; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>, + <&clks IMX7D_PLL_SYS_PFD5_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>; + assigned-clock-rates = <0>, <333000000>; + power-domains = <&pgc_mipi_phy>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dsi_in_lcdif: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out_mipi_dsi>; + }; + }; + }; + }; + }; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; + }; + + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + flexcan1: can@30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1>; + status = "disabled"; + }; + + flexcan2: can@30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2>; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + mu0a: mailbox@30aa0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu0b: mailbox@30ab0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30ab0000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + fsl,mu-side-b; + status = "disabled"; + }; + + usbotg1: usb@30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbh: usb@30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc1: usbmisc@30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc3: usbmisc@30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + qspi: spi@30bb0000 { + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + sdma: dma-controller@30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_SDMA_CORE_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 3>; + status = "disabled"; + }; + }; + + dma_apbh: dma-controller@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: nand-controller@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts index 6c06ad7e47..abe0a2e450 100644 --- a/arch/arm/dts/imx8mm-evk.dts +++ b/arch/arm/dts/imx8mm-evk.dts @@ -8,56 +8,4 @@ #include <arm64/freescale/imx8mm-evk.dts> #include "imx8mm.dtsi" - -/ { - chosen { - environment-sd { - compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; - status = "disabled"; - }; - environment-emmc { - compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; - status = "disabled"; - }; - }; -}; - -®_usdhc2_vmmc { - off-on-delay-us = <20000>; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&ocotp { - barebox,provide-mac-address = <&fec1 0x640>; -}; +#include "imx8mm-evk.dtsi" diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi new file mode 100644 index 0000000000..a657faa6bc --- /dev/null +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd2; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_sd3; + status = "disabled"; + }; + }; +}; + +&{flexspi/flash@0} { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + }; + +}; + +®_usdhc2_vmmc { + off-on-delay-us = <20000>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd2: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd3: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +}; diff --git a/arch/arm/dts/imx8mm-evkb.dts b/arch/arm/dts/imx8mm-evkb.dts new file mode 100644 index 0000000000..b7d3be7a84 --- /dev/null +++ b/arch/arm/dts/imx8mm-evkb.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mm-evk.dts> +#include "imx8mm.dtsi" +#include "imx8mm-evk.dtsi" + +/ { + model = "FSL i.MX8MM EVKB"; + compatible = "fsl,imx8mm-evkb", "fsl,imx8mm"; +}; + +&i2c1 { + /delete-node/ pmic@4b; + + pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <820000>; + nxp,dvs-standby-voltage = <800000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts new file mode 100644 index 0000000000..ac7e5a1cb1 --- /dev/null +++ b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include <arm64/freescale/imx8mm-innocomm-wb15-evk.dts> + +/ { + chosen { + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_sd1; + status = "disabled"; + }; + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd2; + status = "disabled"; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +}; + +&usdhc1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_sd1: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_sd2: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 0000000000..0a6183f092 --- /dev/null +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include <arm64/freescale/imx8mm-phyboard-polis-rdk.dts> + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd2; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + status = "disabled"; + }; + }; + + aliases { + state = &state_emmc; + }; + + state_emmc: state { + compatible = "barebox,state"; + magic = <0xabff4b1f>; + backend-type = "raw"; + backend = <&usdhc3>; + backend-storage-type="direct"; + /* + * barebox-state partition size: 1 MiB + * nr. of redundant copies: 4 + * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte + * + * stride size: 262144 Byte + * raw-header: - 16 Byte + * direct-storage: - 8 Byte + * ------------ + * max state size: 262120 Byte + * =========== + */ + backend-stridesize = <0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@4 { + reg = <0x4 0x4>; + type= "uint32"; + default = <21>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@c { + reg = <0xc 0x4>; + type= "uint32"; + default = <20>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_sd2: partition@100000 { + label = "dt-barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; + +&usdhc3 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_emmc: partition@100000 { + label = "dt-barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 78bbacb2b1..01f74c1074 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -1,10 +1,28 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/features/imx8m.h> + / { aliases { gpr.reboot_mode = &reboot_mode_gpr; + pwm0 = &pwm1; + pwm1 = &pwm2; + pwm2 = &pwm3; + pwm3 = &pwm4; + }; + + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; }; }; +feat: &ocotp { + #feature-cells = <1>; + barebox,feature-controller; +}; + &src { compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon", "simple-mfd"; @@ -16,3 +34,47 @@ mode-serial = <0x00000010>, <0x40000000>; }; }; + +&A53_1 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>; +}; + +&A53_2 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&A53_3 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&gpc { + barebox,feature-gates = <&feat 0>; +}; + +&vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_blk_ctrl { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpumix { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_h1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts new file mode 100644 index 0000000000..6ebb4d15e4 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-evk.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include <arm64/freescale/imx8mn-ddr4-evk.dts> +#include "imx8mn-evk.dtsi" diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts index b8e7e1acf5..eb6e1312f4 100644 --- a/arch/arm/dts/imx8mn-evk.dts +++ b/arch/arm/dts/imx8mn-evk.dts @@ -1,92 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> - */ /dts-v1/; #include <arm64/freescale/imx8mn-evk.dts> - -/ { - chosen { - environment-sd { - compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; - status = "disabled"; - }; - environment-emmc { - compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; - status = "disabled"; - }; - }; -}; - -&fec1 { - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&ocotp { - barebox,provide-mac-address = <&fec1 0x640>; -}; - -&iomuxc { - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 - MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 - MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 - MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 - MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 - MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 - >; - }; -}; - -&flexspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - - system_flash: flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - +#include "imx8mn-evk.dtsi" diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi new file mode 100644 index 0000000000..c23075216e --- /dev/null +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#include "imx8mn.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd2; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_sd3; + status = "disabled"; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + }; + +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd2: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd3: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +}; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; +}; + +&flexspi { + pinctrl-0 = <&pinctrl_flexspi0>; +}; + +&flash0 { + spi-max-frequency = <80000000>; +}; diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi new file mode 100644 index 0000000000..9aa787ea25 --- /dev/null +++ b/arch/arm/dts/imx8mn.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/features/imx8m.h> + +/ { + aliases { + pwm0 = &pwm1; + pwm1 = &pwm2; + pwm2 = &pwm3; + pwm3 = &pwm4; + }; + + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; + }; +}; + +feat: &ocotp { + #feature-cells = <1>; + barebox,feature-controller; +}; + +&A53_1 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>; +}; + +&A53_2 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&A53_3 { + barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>; +}; + +&gpc { + barebox,feature-gates = <&feat 0>; +}; + +&gpu { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&pgc_gpumix { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; diff --git a/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi b/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi new file mode 100644 index 0000000000..b2e8fa968a --- /dev/null +++ b/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-FileCopyrightText: 2019 NXP +// SPDX-FileCopyrightText: 2022 congatec GmbH +// SPDX-FileCopyrightText: 2023 Pengutronix + +&w25q64fw { /* FlexSPI NOR Flash */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x400000>; + }; + + partition@400000 { + label = "failsafe"; + reg = <0x400000 0x3e0000>; + }; + + partition@7e0000 { + label = "reserved"; + reg = <0x7e0000 0x20000>; + read-only; + }; +}; diff --git a/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi b/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi new file mode 100644 index 0000000000..57010bd6f5 --- /dev/null +++ b/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi @@ -0,0 +1,1040 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-FileCopyrightText: 2019 NXP +// SPDX-FileCopyrightText: 2022 congatec GmbH +// SPDX-FileCopyrightText: 2023 Pengutronix, Johannes Zink <j.zink@pengutronix.de> + +#include <arm64/freescale/imx8mp.dtsi> +#include "imx8mp.dtsi" +#include <dt-bindings/usb/pd.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "conga-QMX8-Plus"; + compatible = "congatec,qmx8p", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + rtc0 = &rtc_ext; /* external I2C RTC M4162 */ + rtc1 = &snvs_rtc; /* internal in SoC */ + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells= <0>; + clock-frequency = <100000000>; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + regulator-name = "usb1_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_usb2_host_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_vbus>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + regulator-name = "usb2_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + /* reset line for SD1 (Qseven SD Card) interface */ + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_vmmc>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + regulator-name = "3v3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + /* reset line for SD2 (on-SoM µSD) interface */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-name = "3v3-sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + /* reset line for SD3 (on-SoM eMMC) interface */ + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_vmmc>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + regulator-name = "3v3-sd3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_lfp_vdd: regulator-lfp-vdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display_vdd_en>; + gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; // LFP0_VDD_EN + regulator-name = "Display_Panel_Vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight_enable: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_backlight>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + lvds0_backlight: lvds0-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + power-supply = <®_backlight_enable>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <80>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 4 100000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_interrupt_fan_in>; + #cooling-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_gbe0_rst>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* on-SoM PHY */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + w25q64fw: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; /* PMIC_nINT */ + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* i2c-5: RTC */ +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + rtc_ext: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + }; +}; + +/* i2c-6: I2C splitter */ +&i2c6 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* MIPI-CSI 1 */ + imux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* MIPI-CSI 2 */ + imux1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Qseven LVDS_DID */ + imux2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Qseven LVDS_BLC */ + imux3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Ports 4 .. 7 not used */ + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; + fsl,max-link-speed = <2>; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + clocks = <&pcie0_refclk>; + clock-names= "ref"; +}; + +&uart1 { /* UART0 connector on Qseven */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; +}; + +&uart2 { + /* on-SoM UART connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { /* on-SoM hub */ + fsl,phy-tx-vref-tune = <8>; // note: downstream + fsl,phy-tx-preemp-amp-tune = <3>; // note: downstream + vbus-supply = <®_usb1_host_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { /* Qseven USB_P1 */ + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb_overcurrent>; + }; +}; + +&usb3_phy1 { + vbus-supply = <®_usb2_host_vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { /* Qseven USB_P0 */ + dr_mode = "host"; + status = "okay"; +}; + +/* Qseven SD Card interface */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc1_vmmc>; + bus-width = <4>; +}; + +/* on-SoM µSD Card slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* on-SoM eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gbe0_phy_reg>; +}; + +&gpio4 { + stby_en-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CB_STBY_EN"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = + <&pinctrl_hog>, + <&pinctrl_android_buttons>, + <&pinctrl_pm>, + <&pinctrl_q7_suspend>, + <&pinctrl_q7_wdt>; + + pinctrl_hog: hog-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x01c0 /* PM_WAKE# (X19:32) */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x01c0 /* SMB_ALERT# (X19:20) */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x01c0 /* I2S_RST# */ + >; + }; + + pinctrl_display_vdd_en: lvds-vdd-enable-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x0100 /* LFP_VDD_EN */ + >; + }; + + pinctrl_hdmi: hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + /* On module Android buttons (X7) */ + pinctrl_android_buttons: androidbutton-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x01c0 /* X7-2: Btn Vol Up */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x01c0 /* X7-3: Btn Home */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x01c0 /* X7-4: Btn Search */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x01c0 /* X7-5: Btn Back */ + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x01c0 /* X7-6: Btn Menu */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x01c0 /* X7-7: Btn Vol Down */ + >; + }; + + /* Qseven PM signals */ + pinctrl_pm: pm-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x01c0 /* Q7-21: Sleep Btn */ + MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x01c0 /* Q7-22: Lid Btn */ + MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x01c0 /* Q7-27: Bat Low */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x01c0 /* Q7-69: Thrm */ + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x01c0 /* Q7-71: Thrm Trip (X19:19) */ + >; + }; + + /* Qseven WDT */ + pinctrl_q7_wdt: q7-wdt-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x01c0 /* Q7-70: WDT Trig */ + MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x0100 /* Q7-72: WDT Out */ + >; + }; + + /* Qseven suspend signals */ + pinctrl_q7_suspend: q7-suspend-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x0100 /* Q7-18: SUS_S3# (enable signal from PMIC) */ + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x0100 /* Q7-19: SUS_STAT | GP_OUT0*/ + >; + }; + + /* USB overcurrent */ + pinctrl_usb_overcurrent: usb-overcurrent-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x01c0 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x01c0 /* USB1 OC as GPIO */ + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x01c0 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs0: ecspi2cs0-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x01c0 + >; + }; + + pinctrl_ecspi2_cs1: ecspi2cs1-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x01c0 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + + /* PTP capture INT */ + MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0 + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x150 + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x150 + >; + }; + + pinctrl_flexspi0: flexspi0-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c0 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_i2c5_gpio: i2c5grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c3 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c3 + >; + }; + + pinctrl_i2c6_gpio: i2c6grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c3 + >; + }; + + pinctrl_pcie: pcie-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x160 /* #OE of on-SoM PCIe CLK generator */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x41 /* WAKE */ + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x0100 /* reset */ + >; + }; + + pinctrl_pmic: pmicirq-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x41 + >; + }; + + pinctrl_sai5: sai5-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* USB1 ID */ + >; + }; + + /* Qseven SD Card interface */ + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c4 /* Q7-43: SD CD */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x1c4 /* Q7-46: SD WP */ + >; + }; + + pinctrl_usdhc1_vmmc: usdhc1-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 /* reset */ + >; + }; + + /* on-SoM µSD Card slot */ + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + /* on-SoM eMMC */ + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_usdhc3_vmmc: usdhc3-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x41 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_gpt1_capture1: gpt1-capture1-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x01C0 + >; + }; + + pinctrl_interrupt_fan_in: interrupt-fan-in-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x01C0 + >; + }; + + pinctrl_usb1_vbus: usb1-vbus-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x0100 /* USB1_PWR */ + >; + }; + + pinctrl_usb2_vbus: usb2-vbus-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x0100 /* USB0S_PWR */ + >; + }; + + pinctrl_gbe0_phy_reg: gbe0-phy-reg-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x01C0 /* GBE0_PWR_EN# */ + >; + }; + + pinctrl_gbe0_rst: gbe0-rst-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x01C0 /* GBE0_RST# */ + >; + }; + + pinctrl_lvds0_backlight: lvds0-backlight-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x0100 /* BL_EN */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-debix-model-a-upstream.dts b/arch/arm/dts/imx8mp-debix-model-a-upstream.dts new file mode 100644 index 0000000000..48014748c5 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a-upstream.dts @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2022 Ideas on Board Oy + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/usb/pd.h> + +#include <arm64/freescale/imx8mp.dtsi> + +/ { + model = "Polyhex Debix Model A i.MX8MPlus board"; + compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-connection-type = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { /* RTL8211E */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <200000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts new file mode 100644 index 0000000000..a58b40ec86 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-debix-model-a-upstream.dts" +#include "imx8mp.dtsi" + +/ { + /* + * Switch the ethernet aliases compared to usual i.MX8MP ordering + * as the EQOS interface is on the main board, the FEC interface + * is located on the extension board. + */ + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + status = "disabled"; + }; + }; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_sd: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; + +&usdhc3 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_emmc: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts new file mode 100644 index 0000000000..59334ce30c --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include "imx8mp-debix-som-a-upstream.dtsi" + +/ { + model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; + compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", + "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "BB_VDD3V3"; + /* Required timings for ethernet phy's */ + startup-delay-us = <50000>; + off-on-delay-us = <110000>; + gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "BB_VDD5V"; + gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + regulator-som-vdd1v8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "SOM_VDD1V8_SW"; + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-som-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "SOM_VDD3V3_SW"; + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-vbus-usb20 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB20_5V"; + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_baseboard_vdd5v0>; + }; + + regulator-vbus-usb30 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB30_5V"; + gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_baseboard_vdd5v0>; + }; + + reg_vdd5v0: regulator-vdd5v0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VDD_5V"; + gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + nvmem-cells = <ðmac1>; + nvmem-cell-names = "mac-address"; + phy-supply = <®_baseboard_vdd3v3>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <150000>; + eee-broken-1000t; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + nvmem-cells = <ðmac2>; + nvmem-cell-names = "mac-address"; + phy-supply = <®_baseboard_vdd3v3>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <150000>; + eee-broken-1000t; + realtek,clkout-disable; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vdd5v0>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vdd5v0>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&i2c4 { + expander0: gpio@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <0x02>; + }; + + expander1: gpio@23 { + compatible = "nxp,pca9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <0x02>; + + /* + * Since USB1 is bound to peripheral mode we need to ensure + * that VBUS is turned off. + */ + usb30-otg-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "USB30_OTG_EN"; + }; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + #clock-cells = <0>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + #address-cells = <1>; + #size-cells = <0>; + + /* MACs stored in ASCII */ + ethmac1: mac-address@0 { + reg = <0x0 0xc>; + }; + + ethmac2: mac-address@c { + reg = <0xc 0xc>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Debug */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* 2.x hub on port 1 */ + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vdd5v0>; + peer-hub = <&usb_hub_3_x>; + }; + + /* 3.x hub on port 2 */ + usb_hub_3_x: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vdd5v0>; + peer-hub = <&usb_hub_2_x>; + }; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* µSD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + disable-wp; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts b/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts new file mode 100644 index 0000000000..88ad897f34 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-debix-som-a-bmb-08-upstream.dts" +#include "imx8mp.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + status = "disabled"; + }; + }; +}; + +/* Disable peer hub to avoid warnings */ +&usb_hub_2_x { + status = "disabled"; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_sd: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; + +&usdhc3 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_emmc: partition@100000 { + label = "barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi new file mode 100644 index 0000000000..9e0d19a2a7 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#include <arm64/freescale/imx8mp.dtsi> + +/ { + model = "Polyhex i.MX8MPlus Debix SOM A"; + compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + adc@48 { + compatible = "ti,ads1115"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index 3264ade4b8..0376743068 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -13,12 +13,12 @@ chosen { environment-sd { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; environment-emmc { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &env_sd3; status = "disabled"; }; }; @@ -30,11 +30,53 @@ }; }; +/delete-node/ &{/memory@40000000}; + ðphy1 { reset-assert-us = <15000>; reset-deassert-us = <100000>; }; +&{flexspi/flash@0} { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + }; + +}; + +®_usdhc2_vmmc { + off-on-delay-us = <20000>; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + &usdhc2 { #address-cells = <1>; #size-cells = <1>; @@ -44,7 +86,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -59,12 +101,8 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd3: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; }; - -&ocotp { - barebox,provide-mac-address = <&fec 0x640>; -}; diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts new file mode 100644 index 0000000000..eec42954dc --- /dev/null +++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de> + * + */ + +/dts-v1/; + +#include "imx8mp-karo-qsxp-ml81.dtsi" + +/ { + model = "Ka-Ro electronics QSXP-ML81-QSBASE4 (NXP i.MX8MP) Board"; + compatible = "karo,imx8mp-qsxp-ml81-qsbase4", "karo,imx8mp-qsxp-ml81", "fsl,imx8mp"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-connection-type = "rgmii-id"; + phy-handle = <ðphy1>; + phy-supply = <&ldo5_reg>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <100>; + reset-deassert-us = <250000>; + }; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x140 /* PHY reset */ + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x40000016 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x016 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x016 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x016 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x016 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x016 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x110 /* MODE0 */ + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x150 /* MODE1 */ + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x150 /* MODE2 */ + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x150 /* MODE3 */ + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x156 /* PHYAD2 */ + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x000 /* CLK125_EN */ + MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x110 /* LED_MODE */ + >; + }; + + pinctrl_eqos_sleep: eqos-sleep-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x120 + MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x120 + MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x120 + MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x120 + MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x120 + MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x120 + MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x120 + MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x120 + MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x120 + MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x120 + MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x120 + MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x120 + MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x120 + MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x120 + MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x120 + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x120 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi b/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi new file mode 100644 index 0000000000..4115fcf2f5 --- /dev/null +++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de> + * + */ + +/dts-v1/; + +#include "imx8mp-karo.dtsi" + +/ { + model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module"; + compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp"; + + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + regulator-name = "3v3-etn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ldo5_reg>; + }; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + hnp-disable; + srp-disable; + adp-disable; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&ldo5_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x140 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x140 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x140 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi new file mode 100644 index 0000000000..e47623a1a5 --- /dev/null +++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de> + * + */ + +/dts-v1/; + +#include "imx8mp-karo-qsxp-ml81-upstream.dtsi" + +/ { + chosen { + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + status = "disabled"; + }; + }; + + aliases { + state = &state_emmc; + }; + + state_emmc: state { + compatible = "barebox,state"; + magic = <0xabff4b1f>; + backend-type = "raw"; + backend = <&usdhc3>; + backend-storage-type="direct"; + /* + * barebox-state partition size: 1 MiB + * nr. of redundant copies: 4 + * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte + * + * stride size: 262144 Byte + * raw-header: - 16 Byte + * direct-storage: - 8 Byte + * ------------ + * max state size: 262120 Byte + * =========== + */ + backend-stridesize = <0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@4 { + reg = <0x4 0x4>; + type= "uint32"; + default = <21>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@c { + reg = <0xc 0x4>; + type= "uint32"; + default = <20>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usdhc3 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x0 0x0 0x100000>; + }; + + env_emmc: partition@100000 { + label = "dt-barebox-environment"; + reg = <0x0 0x100000 0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-karo.dtsi b/arch/arm/dts/imx8mp-karo.dtsi new file mode 100644 index 0000000000..d034f14533 --- /dev/null +++ b/arch/arm/dts/imx8mp-karo.dtsi @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de> + * + */ + +#include <arm64/freescale/imx8mp.dtsi> +#include "imx8mp.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "vdd-soc"; + regulator-min-microvolt = <805000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <805000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_nand: BUCK5 { + regulator-name = "nvcc-nand"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "nvcc-dram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_snvs_1v8: LDO1 { + regulator-name = "snvs-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + reg_vdda_1v8: LDO3 { + regulator-name = "vdda-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_rtscts>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_usdhc2_cd>; + bus-width = <4>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + fsl,wp-controller; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + no-sd; + no-sdio; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_nand>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart1_rtscts: uart1-rtsctsgrp { + fsl,pins = < + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts b/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts new file mode 100644 index 0000000000..5f8c83f2a2 --- /dev/null +++ b/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-FileCopyrightText: 2023 Pengutronix, Johannes Zink <j.zink@pengutronix.de> + +#include "imx8mp-koenigbauer-alphajet.kernel.dts" +#include "imx8mp-congatec-qmx8p.dtsi" + +/ { + aliases { + state = &state_emmc; + }; + + chosen { + stdout-path = &uart1; /* baseboard UART0, connector J12 */ + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + }; + }; + + state_emmc: state { + compatible = "barebox,state"; + magic = <0xabff4b1f>; + backend-type = "raw"; + backend = <&backend_state_emmc>; + backend-storage-type="direct"; + backend-stridesize = <0x40>; + #address-cells = <1>; + #size-cells = <1>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@4 { + reg = <0x4 0x4>; + type= "uint32"; + default = <21>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <2>; + }; + + priority@c { + reg = <0xC 0x4>; + type= "uint32"; + default = <20>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + + }; + + }; +}; + +&usdhc3 { /* on-SoM eMMC */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_emmc: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + + backend_state_emmc: partition@100000 { + label = "state"; + reg = <0x100000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts b/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts new file mode 100644 index 0000000000..3f958ddf78 --- /dev/null +++ b/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-FileCopyrightText: 2023 Pengutronix + +/dts-v1/; + +#include "imx8mp-congatec-qmx8p.kernel.dtsi" + +/ { + model = "Koenig+Bauer Alphajet"; + compatible = "koenigbauer,alphajet", "congatec,qmxp8p", "fsl,imx8mp"; + + display { + compatible = "innolux,g101ice-l01"; + backlight = <&lvds0_backlight>; + power-supply = <®_lfp_vdd>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&eqos { /* baseboard connects to on-SoM PHY */ + status = "okay"; +}; + +&gpu2d { + status = "okay"; +}; + +&gpu3d { + status = "okay"; +}; + +&lcdif2 { + /* pin IMX8MP_VIDEO_PLL1 to provide bitclock needed by LVDS panel */ + assigned-clock-rates = <0>, <995400000>; + status = "okay"; +}; + +&lvds0_backlight { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pwm2 { /* PWM Backlight */ + status = "okay"; +}; + +&uart1 { /* Baseboard UART0 */ + /delete-property/ uart-has-rtscts; /* not connected on baseboard */ + status = "okay"; +}; + +&usb_dwc3_0 { /* Baseboard J13 – Top Connector */ + /* FIXME: overcurrent pin is handled via TUSB8041 (which one?) */ + status = "okay"; +}; + +&usdhc1 { /* Baseboard J8 - µSD Card slot */ + status = "okay"; + /delete-property/ cd-gpios; /* no CD is tied to GND on baseboard */ + /delete-property/ wp-gpios; /* no WP is tied to GND on baseboard */ + broken-cd; /* do not wait for CD interrupt */ +}; + +&usdhc2 { /* on-SoM µSD Card slot is not used */ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-skov.dts b/arch/arm/dts/imx8mp-skov.dts new file mode 100644 index 0000000000..254e68feca --- /dev/null +++ b/arch/arm/dts/imx8mp-skov.dts @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include <arm64/freescale/imx8mp.dtsi> +#include "imx8mp.dtsi" + +#include <dt-bindings/leds/common.h> + +/ { + model = "Skov i.MX8MP"; + compatible = "skov,imx8mp", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + + environment-sd { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + status = "disabled"; + }; + }; + + aliases { + ethernet0 = &eqos; + ethernet1 = &lan1; + ethernet2 = &lan2; + state = &state; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "D1"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_STATUS; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "D2"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "D3"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops { + compatible = "ramoops"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + state: state { + #address-cells = <1>; + #size-cells = <1>; + magic = <0x1c5b3f49>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&usdhc3>; + /* + * barebox-state partition size: 1 MiB + * nr. of redundant copies: 4 + * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte + * + * stride size: 262144 Byte + * raw-header: - 16 Byte + * direct-storage: - 8 Byte + * ------------ + * max state size: 262120 Byte + * =========== + */ + backend-stridesize = <0x40000>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <30>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + priority@C { + reg = <0xC 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + + display { + #address-cells = <1>; + #size-cells = <1>; + + xres@14 { + reg = <0x14 0x4>; + type = "uint32"; + default = <0>; + }; + + yres@18 { + reg = <0x18 0x4>; + type = "uint32"; + default = <0>; + }; + + brightness@1C { + reg = <0x1C 0x1>; + type = "uint8"; + default = <8>; + }; + + external@1D { + reg = <0x1D 0x1>; + type = "uint8"; + default = <0>; + }; + }; + + ethaddr { + #address-cells = <1>; + #size-cells = <1>; + + eth2@1e { + reg = <0x1E 0x6>; + type = "mac"; + default = [00 11 22 33 44 55]; + }; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-connection-type = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + reset-source-priority = <500>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + switch@5f { + compatible = "microchip,ksz9893"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + reg = <0x5f>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + phy-mode = "internal"; + label = "lan1"; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + }; + + lan2: port@1 { + reg = <1>; + phy-mode = "internal"; + label = "lan2"; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&eqos>; + /* 2ns rgmii-rxid is implemented on PCB. + * Switch should add only rgmii-txid. + */ + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* varaint id */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x100 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x100 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x100 + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x100 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x100 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x100 + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x100 + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x100 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts new file mode 100644 index 0000000000..bf23e40489 --- /dev/null +++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts> +#include "imx8mp.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd2; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_sd3; + status = "disabled"; + }; + }; +}; + +/delete-node/ &{/memory@40000000}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd2: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + env_sd3: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts b/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts new file mode 100644 index 0000000000..ab4c5790cf --- /dev/null +++ b/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts @@ -0,0 +1,680 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2020-2021 Variscite Ltd. + * Copyright 2023 VAHLE Automation GmbH + */ + +#include "imx8mp-var-dart.dtsi" + +/ { + model = "Variscite DART-MX8M-PLUS on DT8MCustomBoard 2.x"; + + chosen { + stdout-path = &uart1; + + environment-sd { + compatible = "barebox,environment"; + device-path = &env_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &env_emmc; + status = "disabled"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + back { + label = "Back"; + linux,code = <KEY_BACK>; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + up { + label = "Up"; + linux,code = <KEY_UP>; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + home { + label = "Home"; + linux,code = <KEY_HOME>; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + down { + label = "Down"; + linux,code = <KEY_DOWN>; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + gp-led1 { + label = "led1"; + gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + gp-led2 { + label = "led2"; + gpios = <&pca6408_2 6 GPIO_ACTIVE_HIGH>; + }; + + gp-led3 { + label = "led3"; + gpios = <&pca6408_2 5 GPIO_ACTIVE_HIGH>; + }; + + gp-led4 { + label = "eMMC"; + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 1000000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + can0_osc: can0_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + eee-broken-1000t; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + irq-is-id-quirk; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + /* Capacitive touch controller */ + ft5x06_ts: ft5x06_ts@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + standard-regs-fallback; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + standard-regs-fallback; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + l1ss-disabled; + status = "okay"; +}; + +&pcie_phy { + ext_osc = <1>; + status = "okay"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune = <0xe>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vboost-level = <5>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "none"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vref-tune = <0xb>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +&usdhc2 { + #address-cells = <2>; + #size-cells = <1>; + + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + + partition@0 { + compatible = "fixed-partitions"; + label = "barebox"; + reg = <0x00000000 0x00000000 0x000e0000>; + }; + + env_sd: partition@e0000 { + compatible = "fixed-partitions"; + label = "barebox-environment"; + reg = <0x00000000 0x000e0000 0x00020000>; + }; +}; + +&usdhc3 { + #address-cells = <2>; + #size-cells = <1>; + + env_emmc: partition@e0000 { + label = "barebox-environment"; + reg = <0x00000000 0x000e0000 0x00020000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>, + <&gpio2 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; + + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + clocks = <&can0_osc>; + spi-max-frequency = <20000000>; + }; + + spidev@2 { + compatible = "var,spidev"; + reg = <2>; + spi-max-frequency = <12000000>; + }; +}; + +&ldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x12 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x12 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x12 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16 + >; + }; + + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xc0 + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x1c6 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0xc6 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c0 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-var-dart.dtsi b/arch/arm/dts/imx8mp-var-dart.dtsi new file mode 100644 index 0000000000..75c31b07f1 --- /dev/null +++ b/arch/arm/dts/imx8mp-var-dart.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2020-2021 Variscite Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include <arm64/freescale/imx8mp.dtsi> +#include "imx8mp.dtsi" + +/ { + compatible = "variscite,imx8mp-var-dart", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + reg_eqos_phy: regulator-eqos-phy { + compatible = "regulator-fixed"; + regulator-name = "eqos-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_audio: regulator-audio-vdd { + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + eee-broken-1000t; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +/* WIFI */ +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x10 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x150 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0xc0 /* WIFI_EN */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 /* WIFI_PWR */ + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0xc0 /* BT_EN */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 /* BT_BUF */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index b251ebeada..4d1f1bf588 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -1,9 +1,112 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include <dt-bindings/features/imx8m.h> + / { remoteproc_cm7: remoteproc-cm7 { compatible = "fsl,imx8mp-cm7"; clocks = <&clk IMX8MP_CLK_M7_CORE>; syscon = <&src>; }; + + aliases { + pwm0 = &pwm1; + pwm1 = &pwm2; + pwm2 = &pwm3; + pwm3 = &pwm4; + }; + + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; + }; +}; + +/* + * The DSP reserved memory will collide with the Barebox malloc area for some + * DRAM sizes, even though the DSP itself is disabled in most configurations. + */ +/delete-node/ &dsp_reserved; +&dsp { + barebox,feature-gates = <&feat IMX8M_FEAT_DSP>; + /delete-property/ memory-region; + status = "disabled"; +}; + +&edacmc { + compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a"; +}; + +feat: &ocotp { + #feature-cells = <1>; + barebox,feature-controller; +}; + +&pgc_gpu2d { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&pgc_gpu3d { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&pgc_gpumix { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&mipi_dsi { + barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>; +}; + +&lcdif1 { + barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>; +}; + +&gpu3d { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&gpu2d { + barebox,feature-gates = <&feat IMX8M_FEAT_GPU>; +}; + +&pgc_vpumix { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_vpu_vc8000e { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_g1 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpu_g2 { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&vpumix_blk_ctrl { + barebox,feature-gates = <&feat IMX8M_FEAT_VPU>; +}; + +&pgc_mlmix { + barebox,feature-gates = <&feat IMX8M_FEAT_NPU>; +}; + +&lcdif2 { + barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>; +}; + +&lvds_bridge { + barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>; }; diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 8ef2c984ac..2e753aeb0f 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -14,12 +14,12 @@ chosen { environment-emmc { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; + device-path = &env_sd1; status = "disabled"; }; environment-sd { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; }; @@ -34,7 +34,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd1: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -49,7 +49,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts index deb31abe54..b048faa2b1 100644 --- a/arch/arm/dts/imx8mq-mnt-reform2.dts +++ b/arch/arm/dts/imx8mq-mnt-reform2.dts @@ -14,13 +14,13 @@ chosen { environment-emmc { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; + device-path = &env_sd1; status = "disabled"; }; environment-sd { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; }; @@ -39,7 +39,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd1: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -54,7 +54,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi index 896993a0e2..d45c243027 100644 --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi @@ -10,12 +10,12 @@ chosen { environment-emmc { compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; + device-path = &env_sd1; status = "disabled"; }; environment-sd { compatible = "barebox,environment"; - device-path = &usdhc2, "partname:barebox-environment"; + device-path = &env_sd2; status = "disabled"; }; }; @@ -64,31 +64,27 @@ nvmem-cell-names = "mac-address"; }; -&uart2 { - rave-sp { - watchdog { - nvmem-cells = <&boot_source>; - nvmem-cell-names = "boot-source"; - }; +&{uart2/mcu/watchdog} { + nvmem-cells = <&boot_source>; + nvmem-cell-names = "boot-source"; +}; - eeprom@a4 { - lru_part_number: lru-part-number@21 { - reg = <0x21 15>; - read-only; - }; +&{uart2/mcu/eeprom@a4} { + lru_part_number: lru-part-number@21 { + reg = <0x21 15>; + read-only; + }; - boot_source: boot-source@83 { - reg = <0x83 1>; - }; + boot_source: boot-source@83 { + reg = <0x83 1>; + }; - mac_address_0: mac-address@180 { - reg = <0x180 6>; - }; + mac_address_0: mac-address@180 { + reg = <0x180 6>; + }; - mac_address_1: mac-address@190 { - reg = <0x190 6>; - }; - }; + mac_address_1: mac-address@190 { + reg = <0x190 6>; }; }; @@ -101,7 +97,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd1: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; @@ -116,7 +112,7 @@ reg = <0x0 0xe0000>; }; - partition@e0000 { + env_sd2: partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index e56cdfe130..7cdbafcffe 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -5,6 +5,11 @@ */ / { + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + }; + remoteproc_cm4: remoteproc-cm4 { compatible = "fsl,imx8mq-cm4"; clocks = <&clk IMX8MQ_CLK_M4_CORE>; diff --git a/arch/arm/dts/imx93-tqma9352-mba93xxca.dts b/arch/arm/dts/imx93-tqma9352-mba93xxca.dts new file mode 100644 index 0000000000..b77f8b9f9a --- /dev/null +++ b/arch/arm/dts/imx93-tqma9352-mba93xxca.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm64/freescale/imx93-tqma9352-mba93xxca.dts> +#include "imx93.dtsi" +#include "imx93-tqma93xx.dtsi" diff --git a/arch/arm/dts/imx93-tqma9352-mba93xxla.dts b/arch/arm/dts/imx93-tqma9352-mba93xxla.dts new file mode 100644 index 0000000000..d1d68a55e1 --- /dev/null +++ b/arch/arm/dts/imx93-tqma9352-mba93xxla.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +#include <arm64/freescale/imx93-tqma9352-mba93xxla.dts> +#include "imx93.dtsi" +#include "imx93-tqma93xx.dtsi" diff --git a/arch/arm/dts/imx93-tqma93xx.dtsi b/arch/arm/dts/imx93-tqma93xx.dtsi new file mode 100644 index 0000000000..40425e39a7 --- /dev/null +++ b/arch/arm/dts/imx93-tqma93xx.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +/{ + chosen { + environment-spi-nor { + compatible = "barebox,environment"; + device-path = &environment_spi_nor; + }; + }; +}; + +&lpi2c1 { + pca9451a: pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9451>; + }; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; + dr_mode = "host"; +}; + +&{flexspi1/flash@0} { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + environment_spi_nor: partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi new file mode 100644 index 0000000000..b931586d74 --- /dev/null +++ b/arch/arm/dts/imx93.dtsi @@ -0,0 +1,88 @@ +/{ + chosen { + barebox,bootsource-mmc0 = &usdhc1; + barebox,bootsource-mmc1 = &usdhc2; + barebox,bootsource-mmc2 = &usdhc3; + }; + + soc@0 { + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + + ddrc: memory-controller@4e300000 { + compatible = "fsl,imx93-ddrc"; + reg = <0x4e300000 0x400000>; + }; + }; +}; + +&fec { + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; +}; + +&eqos { + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; +}; + +&ocotp { + eth_mac1: mac-address@4ec { + reg = <0x4ec 6>; + }; + + eth_mac2: mac-address@4f2 { + reg = <0x4f2 6>; + }; +}; diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts new file mode 100644 index 0000000000..b4606ff129 --- /dev/null +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -0,0 +1,30 @@ +/dts-v1/; + +#include <arm64/ti/k3-am625-beagleplay.dts> + +/ { + chosen { + stdout-path = &main_uart0; + }; +}; + +&sd_pins_default { + pinctrl-single,pins = < + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + /* + * The upstream dts configures this as MMC1_SDCD.GPIO1_48 and + * uses main_gpio1 48 as card detect GPIO. With this the + * MMC driver doesn't doesn't detect the card. Upstream + * dts has the ti,fails-without-test-cd property which + * purpose seems to be to work around this issue. This + * doesn't work either in barebox. For now configure the + * pin as native SDHCI card detect. + */ + AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; +}; diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts index 1be03a7ac0..7374c23c2b 100644 --- a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts +++ b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts @@ -3,7 +3,7 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/kirkwood-guruplug-server-plus.dts" +#include "arm/marvell/kirkwood-guruplug-server-plus.dts" &{/gpio-leds/health-r} { barebox,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts index b13ab2ab93..748a57f924 100644 --- a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts +++ b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts @@ -2,7 +2,7 @@ * Barebox specific DT overlay for OpenBlocks A6 board */ -#include "arm/kirkwood-openblocks_a6.dts" +#include "arm/marvell/kirkwood-openblocks_a6.dts" &{/gpio-leds/led-green} { barebox,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/kirkwood-topkick-bb.dts b/arch/arm/dts/kirkwood-topkick-bb.dts index c70d654c52..d99eba0274 100644 --- a/arch/arm/dts/kirkwood-topkick-bb.dts +++ b/arch/arm/dts/kirkwood-topkick-bb.dts @@ -3,7 +3,7 @@ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> */ -#include "arm/kirkwood-topkick.dts" +#include "arm/marvell/kirkwood-topkick.dts" &{/gpio-leds/system} { barebox,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index daa75b831f..35aba4f5a6 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include <arm/rk3188-radxarock.dts> +#include <arm/rockchip/rk3188-radxarock.dts> / { chosen { @@ -20,8 +20,7 @@ environment { compatible = "barebox,environment"; - device-path = &mmc0, "partname:barebox-environment"; - status = "okay"; + device-path = &env_mmc0; }; }; }; @@ -34,7 +33,8 @@ label = "barebox"; reg = <0x0 0x80000>; }; - partition@80000 { + + env_mmc0: partition@80000 { label = "barebox-environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/dts/rk3288-phycore-som.dts b/arch/arm/dts/rk3288-phycore-som.dts index 67073b2d83..2e4fe44479 100644 --- a/arch/arm/dts/rk3288-phycore-som.dts +++ b/arch/arm/dts/rk3288-phycore-som.dts @@ -14,7 +14,7 @@ /dts-v1/; -#include <arm/rk3288.dtsi> +#include <arm/rockchip/rk3288.dtsi> / { model = "phycore-rk3288"; @@ -49,13 +49,13 @@ environment-emmc { compatible = "barebox,environment"; - device-path = &emmc, "partname:barebox-environment"; + device-path = &env_emmc; status = "disabled"; }; environment-sdmmc { compatible = "barebox,environment"; - device-path = &sdmmc, "partname:barebox-environment"; + device-path = &env_sdmmc; status = "disabled"; }; }; @@ -100,7 +100,7 @@ reg = <0x20000 0x80000>; }; - partition@a0000 { + env_emmc: partition@a0000 { label = "barebox-environment"; reg = <0xa0000 0x20000>; }; @@ -131,7 +131,7 @@ reg = <0x20000 0x80000>; }; - partition@a0000 { + env_sdmmc: partition@a0000 { label = "barebox-environment"; reg = <0xa0000 0x20000>; }; diff --git a/arch/arm/dts/rk3566-cm3-io.dts b/arch/arm/dts/rk3566-cm3-io.dts new file mode 100644 index 0000000000..39cef5e797 --- /dev/null +++ b/arch/arm/dts/rk3566-cm3-io.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/rockchip/rk3566-radxa-cm3-io.dts> +#include "rk356x.dtsi" + +/ { + chosen: chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &environment_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &environment_emmc; + status = "disabled"; + }; + }; +}; + +&sdhci { + no-sd; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_emmc: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; + +&sdmmc0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_sd: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts index 8639ca0886..0036ef31f1 100644 --- a/arch/arm/dts/rk3566-quartz64-a.dts +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -3,6 +3,7 @@ /dts-v1/; #include <arm64/rockchip/rk3566-quartz64-a.dts> +#include "rk356x.dtsi" / { memory@a00000 { diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts index da76ab64c1..58a2bc442f 100644 --- a/arch/arm/dts/rk3568-bpi-r2-pro.dts +++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts @@ -5,23 +5,9 @@ */ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3568.dtsi" - +#include "arm64/rockchip/rk3568-bpi-r2-pro.dts" / { - model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; - compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; - - aliases { - emmc = &sdhci; - sd = &sdmmc0; - }; - chosen { - stdout-path = "serial2:1500000n8"; - environment-sd { compatible = "barebox,environment"; device-path = &environment_sd; @@ -39,422 +25,10 @@ device_type = "memory"; reg = <0x0 0x00a00000 0x0 0x7f600000>; }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin &green_led_pin>; - - blue_led: led-0 { - color = <LED_COLOR_ID_BLUE>; - default-state = "off"; - function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - }; - - green_led: led-1 { - color = <LED_COLOR_ID_GREEN>; - default-state = "on"; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_lcd1_n: vcc3v3-lcd1-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-always-on; - }; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - - snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x3c>; - rx_delay = <0x2f>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - /* 1: rst regs (default in codes), 0: rst the pmic */ - pmic-reset-func = <0>; - - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c5 { - /* pin 3 (SDA) + 4 (SCL) of header con2 */ - status = "disabled"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pinctrl { - leds { - blue_led_pin: blue-led-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - green_led_pin: green-led-pin { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm8 { - /* fan 5v - gnd - pwm */ - status = "okay"; -}; - -&pwm10 { - /* pin 7 of header con2 */ - status = "disabled"; -}; - -&pwm11 { - /* pin 15 of header con2 */ - status = "disabled"; -}; - -&pwm12 { - /* pin 21 of header con2 */ - /* shared with uart9 + spi3 */ - pinctrl-0 = <&pwm12m1_pins>; - status = "disabled"; -}; - -&pwm13 { - /* pin 24 of header con2 */ - /* shared with uart9 */ - pinctrl-0 = <&pwm13m1_pins>; - status = "disabled"; -}; - -&pwm14 { - /* pin 23 of header con2 */ - /* shared with spi3 */ - pinctrl-0 = <&pwm14m1_pins>; - status = "disabled"; -}; - -&pwm15 { - /* pin 19 of header con2 */ - /* shared with spi3 */ - pinctrl-0 = <&pwm15m1_pins>; - status = "disabled"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; }; &sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; no-sd; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; partitions { compatible = "fixed-partitions"; @@ -469,18 +43,6 @@ }; &sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; - partitions { compatible = "fixed-partitions"; #address-cells = <2>; @@ -493,87 +55,6 @@ }; }; -&uart0 { - /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */ - status = "disabled"; -}; - -&uart2 { - /* debug-uart */ - status = "okay"; -}; - -&uart7 { - /* pin 11 (TX) + 13 (RX) of header con2 */ - pinctrl-0 = <&uart7m1_xfer>; - status = "disabled"; -}; - -&uart9 { - /* pin 21 (TX) + 24 (RX) of header con2 */ - /* shared with pwm13 and pwm12/spi3 */ - pinctrl-0 = <&uart9m1_xfer>; - status = "disabled"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&combphy0_us { - status = "okay"; -}; - -&combphy1_usq { - status = "okay"; }; diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts index d2c1fc89a8..82186ff86e 100644 --- a/arch/arm/dts/rk3568-evb1-v10.dts +++ b/arch/arm/dts/rk3568-evb1-v10.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <arm64/rockchip/rk3568-evb1-v10.dts> +#include "rk356x.dtsi" / { chosen: chosen { diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi deleted file mode 100644 index a588ca95ac..0000000000 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ /dev/null @@ -1,3111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include <dt-bindings/pinctrl/rockchip.h> -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - acodec { - /omit-if-no-ref/ - acodec_pins: acodec-pins { - rockchip,pins = - /* acodec_adc_sync */ - <1 RK_PB1 5 &pcfg_pull_none>, - /* acodec_adcclk */ - <1 RK_PA1 5 &pcfg_pull_none>, - /* acodec_adcdata */ - <1 RK_PA0 5 &pcfg_pull_none>, - /* acodec_dac_datal */ - <1 RK_PA7 5 &pcfg_pull_none>, - /* acodec_dac_datar */ - <1 RK_PB0 5 &pcfg_pull_none>, - /* acodec_dacclk */ - <1 RK_PA3 5 &pcfg_pull_none>, - /* acodec_dacsync */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - }; - - audiopwm { - /omit-if-no-ref/ - audiopwm_lout: audiopwm-lout { - rockchip,pins = - /* audiopwm_lout */ - <1 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutn: audiopwm-loutn { - rockchip,pins = - /* audiopwm_loutn */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutp: audiopwm-loutp { - rockchip,pins = - /* audiopwm_loutp */ - <1 RK_PA0 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_rout: audiopwm-rout { - rockchip,pins = - /* audiopwm_rout */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routn: audiopwm-routn { - rockchip,pins = - /* audiopwm_routn */ - <1 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routp: audiopwm-routp { - rockchip,pins = - /* audiopwm_routp */ - <1 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - bt656 { - /omit-if-no-ref/ - bt656m0_pins: bt656m0-pins { - rockchip,pins = - /* bt656_clkm0 */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* bt656_d0m0 */ - <2 RK_PD0 2 &pcfg_pull_none>, - /* bt656_d1m0 */ - <2 RK_PD1 2 &pcfg_pull_none>, - /* bt656_d2m0 */ - <2 RK_PD2 2 &pcfg_pull_none>, - /* bt656_d3m0 */ - <2 RK_PD3 2 &pcfg_pull_none>, - /* bt656_d4m0 */ - <2 RK_PD4 2 &pcfg_pull_none>, - /* bt656_d5m0 */ - <2 RK_PD5 2 &pcfg_pull_none>, - /* bt656_d6m0 */ - <2 RK_PD6 2 &pcfg_pull_none>, - /* bt656_d7m0 */ - <2 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - bt656m1_pins: bt656m1-pins { - rockchip,pins = - /* bt656_clkm1 */ - <4 RK_PB4 5 &pcfg_pull_none>, - /* bt656_d0m1 */ - <3 RK_PC6 5 &pcfg_pull_none>, - /* bt656_d1m1 */ - <3 RK_PC7 5 &pcfg_pull_none>, - /* bt656_d2m1 */ - <3 RK_PD0 5 &pcfg_pull_none>, - /* bt656_d3m1 */ - <3 RK_PD1 5 &pcfg_pull_none>, - /* bt656_d4m1 */ - <3 RK_PD2 5 &pcfg_pull_none>, - /* bt656_d5m1 */ - <3 RK_PD3 5 &pcfg_pull_none>, - /* bt656_d6m1 */ - <3 RK_PD4 5 &pcfg_pull_none>, - /* bt656_d7m1 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clk */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <3 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <3 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <3 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <3 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <3 RK_PC1 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <3 RK_PC2 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - cam { - /omit-if-no-ref/ - cam_clkout0: cam-clkout0 { - rockchip,pins = - /* cam_clkout0 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cam_clkout1: cam-clkout1 { - rockchip,pins = - /* cam_clkout1 */ - <4 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rxm0 */ - <0 RK_PB4 2 &pcfg_pull_none>, - /* can0_txm0 */ - <0 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rxm1 */ - <2 RK_PA2 4 &pcfg_pull_none>, - /* can0_txm1 */ - <2 RK_PA1 4 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rxm0 */ - <1 RK_PA0 3 &pcfg_pull_none>, - /* can1_txm0 */ - <1 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rxm1 */ - <4 RK_PC2 3 &pcfg_pull_none>, - /* can1_txm1 */ - <4 RK_PC3 3 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rxm0 */ - <4 RK_PB4 3 &pcfg_pull_none>, - /* can2_txm0 */ - <4 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rxm1 */ - <2 RK_PB1 4 &pcfg_pull_none>, - /* can2_txm1 */ - <2 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PC1 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB6 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PD6 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PD7 1 &pcfg_pull_none>, - /* cif_d10 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d11 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d12 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d13 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d14 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d15 */ - <4 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d5 */ - <3 RK_PD3 1 &pcfg_pull_none>, - /* cif_d6 */ - <3 RK_PD4 1 &pcfg_pull_none>, - /* cif_d7 */ - <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_avs */ - <0 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - ebc { - /omit-if-no-ref/ - ebc_extern: ebc-extern { - rockchip,pins = - /* ebc_sdce1 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* ebc_sdce2 */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* ebc_sdce3 */ - <4 RK_PB1 2 &pcfg_pull_none>, - /* ebc_sdshr */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* ebc_vcom */ - <4 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - ebc_pins: ebc-pins { - rockchip,pins = - /* ebc_gdclk */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* ebc_gdoe */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* ebc_gdsp */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* ebc_sdce0 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* ebc_sdclk */ - <4 RK_PC1 2 &pcfg_pull_none>, - /* ebc_sddo0 */ - <3 RK_PC6 2 &pcfg_pull_none>, - /* ebc_sddo1 */ - <3 RK_PC7 2 &pcfg_pull_none>, - /* ebc_sddo2 */ - <3 RK_PD0 2 &pcfg_pull_none>, - /* ebc_sddo3 */ - <3 RK_PD1 2 &pcfg_pull_none>, - /* ebc_sddo4 */ - <3 RK_PD2 2 &pcfg_pull_none>, - /* ebc_sddo5 */ - <3 RK_PD3 2 &pcfg_pull_none>, - /* ebc_sddo6 */ - <3 RK_PD4 2 &pcfg_pull_none>, - /* ebc_sddo7 */ - <3 RK_PD5 2 &pcfg_pull_none>, - /* ebc_sddo8 */ - <3 RK_PD6 2 &pcfg_pull_none>, - /* ebc_sddo9 */ - <3 RK_PD7 2 &pcfg_pull_none>, - /* ebc_sddo10 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* ebc_sddo11 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* ebc_sddo12 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* ebc_sddo13 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* ebc_sddo14 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* ebc_sddo15 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* ebc_sdle */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* ebc_sdoe */ - <4 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - edpdp { - /omit-if-no-ref/ - edpdpm0_pins: edpdpm0-pins { - rockchip,pins = - /* edpdp_hpdinm0 */ - <4 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - edpdpm1_pins: edpdpm1-pins { - rockchip,pins = - /* edpdp_hpdinm1 */ - <0 RK_PC2 2 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_datastrobe: emmc-datastrobe { - rockchip,pins = - /* emmc_datastrobe */ - <1 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko25m */ - <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1m0_pins: eth1m0-pins { - rockchip,pins = - /* eth1_refclko25mm0 */ - <3 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - eth1m1_pins: eth1m1-pins { - rockchip,pins = - /* eth1_refclko25mm1 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - flash { - /omit-if-no-ref/ - flash_pins: flash-pins { - rockchip,pins = - /* flash_ale */ - <1 RK_PD0 2 &pcfg_pull_none>, - /* flash_cle */ - <1 RK_PC6 3 &pcfg_pull_none>, - /* flash_cs0n */ - <1 RK_PD3 2 &pcfg_pull_none>, - /* flash_cs1n */ - <1 RK_PD4 2 &pcfg_pull_none>, - /* flash_d0 */ - <1 RK_PB4 2 &pcfg_pull_none>, - /* flash_d1 */ - <1 RK_PB5 2 &pcfg_pull_none>, - /* flash_d2 */ - <1 RK_PB6 2 &pcfg_pull_none>, - /* flash_d3 */ - <1 RK_PB7 2 &pcfg_pull_none>, - /* flash_d4 */ - <1 RK_PC0 2 &pcfg_pull_none>, - /* flash_d5 */ - <1 RK_PC1 2 &pcfg_pull_none>, - /* flash_d6 */ - <1 RK_PC2 2 &pcfg_pull_none>, - /* flash_d7 */ - <1 RK_PC3 2 &pcfg_pull_none>, - /* flash_dqs */ - <1 RK_PC5 2 &pcfg_pull_none>, - /* flash_rdn */ - <1 RK_PD2 2 &pcfg_pull_none>, - /* flash_rdy */ - <1 RK_PD1 2 &pcfg_pull_none>, - /* flash_volsel */ - <0 RK_PA7 1 &pcfg_pull_none>, - /* flash_wpn */ - <1 RK_PC7 3 &pcfg_pull_none>, - /* flash_wrn */ - <1 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspi_pins: fspi-pins { - rockchip,pins = - /* fspi_clk */ - <1 RK_PD0 1 &pcfg_pull_none>, - /* fspi_cs0n */ - <1 RK_PD3 1 &pcfg_pull_none>, - /* fspi_d0 */ - <1 RK_PD1 1 &pcfg_pull_none>, - /* fspi_d1 */ - <1 RK_PD2 1 &pcfg_pull_none>, - /* fspi_d2 */ - <1 RK_PC7 2 &pcfg_pull_none>, - /* fspi_d3 */ - <1 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - fspi_cs1: fspi-cs1 { - rockchip,pins = - /* fspi_cs1n */ - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <2 RK_PC3 2 &pcfg_pull_none>, - /* gmac0_mdio */ - <2 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <2 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_er: gmac0-rx-er { - rockchip,pins = - /* gmac0_rxer */ - <2 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PB7 2 &pcfg_pull_none>, - /* gmac0_rxdvcrs */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1m0_miim: gmac1m0-miim { - rockchip,pins = - /* gmac1_mdcm0 */ - <3 RK_PC4 3 &pcfg_pull_none>, - /* gmac1_mdiom0 */ - <3 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_clkinout: gmac1m0-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm0 */ - <3 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_er: gmac1m0-rx-er { - rockchip,pins = - /* gmac1_rxerm0 */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_bus2: gmac1m0-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m0 */ - <3 RK_PB1 3 &pcfg_pull_none>, - /* gmac1_rxd1m0 */ - <3 RK_PB2 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm0 */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2: gmac1m0-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_miim: gmac1m1-miim { - rockchip,pins = - /* gmac1_mdcm1 */ - <4 RK_PB6 3 &pcfg_pull_none>, - /* gmac1_mdiom1 */ - <4 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_clkinout: gmac1m1-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm1 */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_er: gmac1m1-rx-er { - rockchip,pins = - /* gmac1_rxerm1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_bus2: gmac1m1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m1 */ - <4 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_rxd1m1 */ - <4 RK_PB0 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm1 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2: gmac1m1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC0 2 &pcfg_pull_none>, - /* gpu_pwren */ - <0 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - hdmitx { - /omit-if-no-ref/ - hdmitxm0_cec: hdmitxm0-cec { - rockchip,pins = - /* hdmitxm0_cec */ - <4 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitxm1_cec: hdmitxm1-cec { - rockchip,pins = - /* hdmitxm1_cec */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_scl: hdmitx-scl { - rockchip,pins = - /* hdmitx_scl */ - <4 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_sda: hdmitx-sda { - rockchip,pins = - /* hdmitx_sda */ - <4 RK_PD0 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0_xfer: i2c0-xfer { - rockchip,pins = - /* i2c0_scl */ - <0 RK_PB1 1 &pcfg_pull_none_smt>, - /* i2c0_sda */ - <0 RK_PB2 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1_xfer: i2c1-xfer { - rockchip,pins = - /* i2c1_scl */ - <0 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c1_sda */ - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_sclm0 */ - <0 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam0 */ - <0 RK_PB6 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_sclm1 */ - <4 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam1 */ - <4 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_sclm0 */ - <1 RK_PA1 1 &pcfg_pull_none_smt>, - /* i2c3_sdam0 */ - <1 RK_PA0 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_sclm1 */ - <3 RK_PB5 4 &pcfg_pull_none_smt>, - /* i2c3_sdam1 */ - <3 RK_PB6 4 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_sclm0 */ - <4 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c4_sdam0 */ - <4 RK_PB2 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_sclm1 */ - <2 RK_PB2 2 &pcfg_pull_none_smt>, - /* i2c4_sdam1 */ - <2 RK_PB1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_sclm0 */ - <3 RK_PB3 4 &pcfg_pull_none_smt>, - /* i2c5_sdam0 */ - <3 RK_PB4 4 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_sclm1 */ - <4 RK_PC7 2 &pcfg_pull_none_smt>, - /* i2c5_sdam1 */ - <4 RK_PD0 2 &pcfg_pull_none_smt>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrckrx: i2s1m0-lrckrx { - rockchip,pins = - /* i2s1m0_lrckrx */ - <1 RK_PA6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_lrcktx: i2s1m0-lrcktx { - rockchip,pins = - /* i2s1m0_lrcktx */ - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclkrx: i2s1m0-sclkrx { - rockchip,pins = - /* i2s1m0_sclkrx */ - <1 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclktx: i2s1m0-sclktx { - rockchip,pins = - /* i2s1m0_sclktx */ - <1 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <1 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <1 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrckrx: i2s1m1-lrckrx { - rockchip,pins = - /* i2s1m1_lrckrx */ - <4 RK_PA7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrcktx: i2s1m1-lrcktx { - rockchip,pins = - /* i2s1m1_lrcktx */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <3 RK_PC6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclkrx: i2s1m1-sclkrx { - rockchip,pins = - /* i2s1m1_sclkrx */ - <4 RK_PA6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclktx: i2s1m1-sclktx { - rockchip,pins = - /* i2s1m1_sclktx */ - <3 RK_PC7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <3 RK_PD2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <3 RK_PD4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <3 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <4 RK_PB0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrckrx: i2s1m2-lrckrx { - rockchip,pins = - /* i2s1m2_lrckrx */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrcktx: i2s1m2-lrcktx { - rockchip,pins = - /* i2s1m2_lrcktx */ - <2 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_mclk: i2s1m2-mclk { - rockchip,pins = - /* i2s1m2_mclk */ - <2 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclkrx: i2s1m2-sclkrx { - rockchip,pins = - /* i2s1m2_sclkrx */ - <3 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclktx: i2s1m2-sclktx { - rockchip,pins = - /* i2s1m2_sclktx */ - <2 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi0: i2s1m2-sdi0 { - rockchip,pins = - /* i2s1m2_sdi0 */ - <2 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi1: i2s1m2-sdi1 { - rockchip,pins = - /* i2s1m2_sdi1 */ - <2 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi2: i2s1m2-sdi2 { - rockchip,pins = - /* i2s1m2_sdi2 */ - <2 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi3: i2s1m2-sdi3 { - rockchip,pins = - /* i2s1m2_sdi3 */ - <2 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo0: i2s1m2-sdo0 { - rockchip,pins = - /* i2s1m2_sdo0 */ - <2 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo1: i2s1m2-sdo1 { - rockchip,pins = - /* i2s1m2_sdo1 */ - <3 RK_PA0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo2: i2s1m2-sdo2 { - rockchip,pins = - /* i2s1m2_sdo2 */ - <3 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo3: i2s1m2-sdo3 { - rockchip,pins = - /* i2s1m2_sdo3 */ - <3 RK_PC2 5 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = - /* i2s2m0_lrckrx */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = - /* i2s2m0_lrcktx */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclkrx: i2s2m0-sclkrx { - rockchip,pins = - /* i2s2m0_sclkrx */ - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclktx: i2s2m0-sclktx { - rockchip,pins = - /* i2s2m0_sclktx */ - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrckrx: i2s2m1-lrckrx { - rockchip,pins = - /* i2s2m1_lrckrx */ - <4 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = - /* i2s2m1_lrcktx */ - <4 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclkrx: i2s2m1-sclkrx { - rockchip,pins = - /* i2s2m1_sclkrx */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclktx: i2s2m1-sclktx { - rockchip,pins = - /* i2s2m1_sclktx */ - <4 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <4 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <4 RK_PB3 5 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3m0_lrck: i2s3m0-lrck { - rockchip,pins = - /* i2s3m0_lrck */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_mclk: i2s3m0-mclk { - rockchip,pins = - /* i2s3m0_mclk */ - <3 RK_PA2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sclk: i2s3m0-sclk { - rockchip,pins = - /* i2s3m0_sclk */ - <3 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdi: i2s3m0-sdi { - rockchip,pins = - /* i2s3m0_sdi */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdo: i2s3m0-sdo { - rockchip,pins = - /* i2s3m0_sdo */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_lrck: i2s3m1-lrck { - rockchip,pins = - /* i2s3m1_lrck */ - <4 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_mclk: i2s3m1-mclk { - rockchip,pins = - /* i2s3m1_mclk */ - <4 RK_PC2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sclk: i2s3m1-sclk { - rockchip,pins = - /* i2s3m1_sclk */ - <4 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdi: i2s3m1-sdi { - rockchip,pins = - /* i2s3m1_sdi */ - <4 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdo: i2s3m1-sdo { - rockchip,pins = - /* i2s3m1_sdo */ - <4 RK_PC5 5 &pcfg_pull_none>; - }; - }; - - isp { - /omit-if-no-ref/ - isp_pins: isp-pins { - rockchip,pins = - /* isp_flashtrigin */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* isp_flashtrigout */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* isp_prelighttrig */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtag_pins: jtag-pins { - rockchip,pins = - /* jtag_tck */ - <1 RK_PD7 2 &pcfg_pull_none>, - /* jtag_tms */ - <2 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - lcdc { - /omit-if-no-ref/ - lcdc_ctl: lcdc-ctl { - rockchip,pins = - /* lcdc_clk */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* lcdc_d0 */ - <2 RK_PD0 1 &pcfg_pull_none>, - /* lcdc_d1 */ - <2 RK_PD1 1 &pcfg_pull_none>, - /* lcdc_d2 */ - <2 RK_PD2 1 &pcfg_pull_none>, - /* lcdc_d3 */ - <2 RK_PD3 1 &pcfg_pull_none>, - /* lcdc_d4 */ - <2 RK_PD4 1 &pcfg_pull_none>, - /* lcdc_d5 */ - <2 RK_PD5 1 &pcfg_pull_none>, - /* lcdc_d6 */ - <2 RK_PD6 1 &pcfg_pull_none>, - /* lcdc_d7 */ - <2 RK_PD7 1 &pcfg_pull_none>, - /* lcdc_d8 */ - <3 RK_PA1 1 &pcfg_pull_none>, - /* lcdc_d9 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PA4 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* lcdc_d16 */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* lcdc_d17 */ - <3 RK_PB2 1 &pcfg_pull_none>, - /* lcdc_d18 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* lcdc_d19 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* lcdc_d20 */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* lcdc_d21 */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* lcdc_d22 */ - <3 RK_PB7 1 &pcfg_pull_none>, - /* lcdc_d23 */ - <3 RK_PC0 1 &pcfg_pull_none>, - /* lcdc_den */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_hsync */ - <3 RK_PC1 1 &pcfg_pull_none>, - /* lcdc_vsync */ - <3 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcu_pins: mcu-pins { - rockchip,pins = - /* mcu_jtagtck */ - <0 RK_PB4 4 &pcfg_pull_none>, - /* mcu_jtagtdi */ - <0 RK_PC1 4 &pcfg_pull_none>, - /* mcu_jtagtdo */ - <0 RK_PB3 4 &pcfg_pull_none>, - /* mcu_jtagtms */ - <0 RK_PC2 4 &pcfg_pull_none>, - /* mcu_jtagtrstn */ - <0 RK_PC3 4 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - pcie20 { - /omit-if-no-ref/ - pcie20m0_pins: pcie20m0-pins { - rockchip,pins = - /* pcie20_clkreqnm0 */ - <0 RK_PA5 3 &pcfg_pull_none>, - /* pcie20_perstnm0 */ - <0 RK_PB6 3 &pcfg_pull_none>, - /* pcie20_wakenm0 */ - <0 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m1_pins: pcie20m1-pins { - rockchip,pins = - /* pcie20_clkreqnm1 */ - <2 RK_PD0 4 &pcfg_pull_none>, - /* pcie20_perstnm1 */ - <3 RK_PC1 4 &pcfg_pull_none>, - /* pcie20_wakenm1 */ - <2 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m2_pins: pcie20m2-pins { - rockchip,pins = - /* pcie20_clkreqnm2 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie20_perstnm2 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie20_wakenm2 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20_buttonrstn: pcie20-buttonrstn { - rockchip,pins = - /* pcie20_buttonrstn */ - <0 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_clkreqnm0 */ - <0 RK_PA4 3 &pcfg_pull_none>, - /* pcie30x1_perstnm0 */ - <0 RK_PC3 3 &pcfg_pull_none>, - /* pcie30x1_wakenm0 */ - <0 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_clkreqnm1 */ - <2 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x1_perstnm1 */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* pcie30x1_wakenm1 */ - <2 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_clkreqnm2 */ - <1 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_perstnm2 */ - <1 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_wakenm2 */ - <1 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_buttonrstn: pcie30x1-buttonrstn { - rockchip,pins = - /* pcie30x1_buttonrstn */ - <0 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqnm0 */ - <0 RK_PA6 2 &pcfg_pull_none>, - /* pcie30x2_perstnm0 */ - <0 RK_PC6 3 &pcfg_pull_none>, - /* pcie30x2_wakenm0 */ - <0 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqnm1 */ - <2 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_perstnm1 */ - <2 RK_PD6 4 &pcfg_pull_none>, - /* pcie30x2_wakenm1 */ - <2 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqnm2 */ - <4 RK_PC2 4 &pcfg_pull_none>, - /* pcie30x2_perstnm2 */ - <4 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x2_wakenm2 */ - <4 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_buttonrstn: pcie30x2-buttonrstn { - rockchip,pins = - /* pcie30x2_buttonrstn */ - <0 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm { - /omit-if-no-ref/ - pdmm0_clk: pdmm0-clk { - rockchip,pins = - /* pdm_clk0m0 */ - <1 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_clk1: pdmm0-clk1 { - rockchip,pins = - /* pdmm0_clk1 */ - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = - /* pdmm0_sdi0 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = - /* pdmm0_sdi1 */ - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = - /* pdmm0_sdi2 */ - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = - /* pdmm0_sdi3 */ - <1 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk: pdmm1-clk { - rockchip,pins = - /* pdm_clk0m1 */ - <3 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk1: pdmm1-clk1 { - rockchip,pins = - /* pdmm1_clk1 */ - <4 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi0: pdmm1-sdi0 { - rockchip,pins = - /* pdmm1_sdi0 */ - <3 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi1: pdmm1-sdi1 { - rockchip,pins = - /* pdmm1_sdi1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi2: pdmm1-sdi2 { - rockchip,pins = - /* pdmm1_sdi2 */ - <4 RK_PA2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi3: pdmm1-sdi3 { - rockchip,pins = - /* pdmm1_sdi3 */ - <4 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_clk1: pdmm2-clk1 { - rockchip,pins = - /* pdmm2_clk1 */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi0: pdmm2-sdi0 { - rockchip,pins = - /* pdmm2_sdi0 */ - <3 RK_PB3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi1: pdmm2-sdi1 { - rockchip,pins = - /* pdmm2_sdi1 */ - <3 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi2: pdmm2-sdi2 { - rockchip,pins = - /* pdmm2_sdi2 */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi3: pdmm2-sdi3 { - rockchip,pins = - /* pdmm2_sdi3 */ - <3 RK_PC0 5 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_sleep */ - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug0 */ - <0 RK_PA5 4 &pcfg_pull_none>, - /* pmu_debug1 */ - <0 RK_PA6 3 &pcfg_pull_none>, - /* pmu_debug2 */ - <0 RK_PC4 4 &pcfg_pull_none>, - /* pmu_debug3 */ - <0 RK_PC5 4 &pcfg_pull_none>, - /* pmu_debug4 */ - <0 RK_PC6 4 &pcfg_pull_none>, - /* pmu_debug5 */ - <0 RK_PC7 4 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <0 RK_PB5 4 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <0 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3_pins: pwm3-pins { - rockchip,pins = - /* pwm3_ir */ - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4_pins: pwm4-pins { - rockchip,pins = - /* pwm4 */ - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5_pins: pwm5-pins { - rockchip,pins = - /* pwm5 */ - <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6_pins: pwm6-pins { - rockchip,pins = - /* pwm6 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7_pins: pwm7-pins { - rockchip,pins = - /* pwm7_ir */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PB1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <1 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <1 RK_PD6 4 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <2 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_irm0 */ - <3 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_irm1 */ - <4 RK_PC0 3 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_irm0 */ - <3 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_irm1 */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_ou */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cpdet */ - <0 RK_PA4 2 &pcfg_pull_none>, - /* sata_cppod */ - <0 RK_PA6 1 &pcfg_pull_none>, - /* sata_mpswitch */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0_pins: sata0-pins { - rockchip,pins = - /* sata0_actled */ - <4 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1_pins: sata1-pins { - rockchip,pins = - /* sata1_actled */ - <4 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2_pins: sata2-pins { - rockchip,pins = - /* sata2_actled */ - <4 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - scr { - /omit-if-no-ref/ - scr_pins: scr-pins { - rockchip,pins = - /* scr_clk */ - <1 RK_PA2 3 &pcfg_pull_none>, - /* scr_det */ - <1 RK_PA7 3 &pcfg_pull_up>, - /* scr_io */ - <1 RK_PA3 3 &pcfg_pull_up>, - /* scr_rst */ - <1 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - sdmmc0 { - /omit-if-no-ref/ - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - /* sdmmc0_d0 */ - <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d1 */ - <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d2 */ - <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d3 */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - /* sdmmc0_clk */ - <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - /* sdmmc0_cmd */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_det: sdmmc0-det { - rockchip,pins = - /* sdmmc0_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc0_pwren: sdmmc0-pwren { - rockchip,pins = - /* sdmmc0_pwren */ - <0 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - sdmmc1 { - /omit-if-no-ref/ - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - /* sdmmc1_d0 */ - <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d1 */ - <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d2 */ - <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d3 */ - <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - /* sdmmc1_clk */ - <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - /* sdmmc1_cmd */ - <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_det: sdmmc1-det { - rockchip,pins = - /* sdmmc1_det */ - <2 RK_PB2 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = - /* sdmmc1_pwren */ - <2 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - sdmmc2 { - /omit-if-no-ref/ - sdmmc2m0_bus4: sdmmc2m0-bus4 { - rockchip,pins = - /* sdmmc2_d0m0 */ - <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m0 */ - <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m0 */ - <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m0 */ - <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_clk: sdmmc2m0-clk { - rockchip,pins = - /* sdmmc2_clkm0 */ - <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_cmd: sdmmc2m0-cmd { - rockchip,pins = - /* sdmmc2_cmdm0 */ - <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_det: sdmmc2m0-det { - rockchip,pins = - /* sdmmc2_detm0 */ - <3 RK_PD4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m0_pwren: sdmmc2m0-pwren { - rockchip,pins = - /* sdmmc2m0_pwren */ - <3 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sdmmc2m1_bus4: sdmmc2m1-bus4 { - rockchip,pins = - /* sdmmc2_d0m1 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m1 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m1 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m1 */ - <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_clk: sdmmc2m1-clk { - rockchip,pins = - /* sdmmc2_clkm1 */ - <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_cmd: sdmmc2m1-cmd { - rockchip,pins = - /* sdmmc2_cmdm1 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_det: sdmmc2m1-det { - rockchip,pins = - /* sdmmc2_detm1 */ - <3 RK_PA7 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m1_pwren: sdmmc2m1-pwren { - rockchip,pins = - /* sdmmc2m1_pwren */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - }; - - spdif { - /omit-if-no-ref/ - spdifm0_tx: spdifm0-tx { - rockchip,pins = - /* spdifm0_tx */ - <1 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm1_tx: spdifm1-tx { - rockchip,pins = - /* spdifm1_tx */ - <3 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm2_tx: spdifm2-tx { - rockchip,pins = - /* spdifm2_tx */ - <4 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_none>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_none>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_none>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_none>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_none>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_none>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_none>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_none>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_none>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_none>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_none>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_none>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_none>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm0_shut: tsadcm0-shut { - rockchip,pins = - /* tsadcm0_shut */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shutorg: tsadc-shutorg { - rockchip,pins = - /* tsadc_shutorg */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0_xfer: uart0-xfer { - rockchip,pins = - /* uart0_rx */ - <0 RK_PC0 3 &pcfg_pull_up>, - /* uart0_tx */ - <0 RK_PC1 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PC7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rxm0 */ - <2 RK_PB3 2 &pcfg_pull_up>, - /* uart1_txm0 */ - <2 RK_PB4 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rxm1 */ - <3 RK_PD7 4 &pcfg_pull_up>, - /* uart1_txm1 */ - <3 RK_PD6 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <4 RK_PC1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <4 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rxm0 */ - <0 RK_PD0 1 &pcfg_pull_up>, - /* uart2_txm0 */ - <0 RK_PD1 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rxm1 */ - <1 RK_PD6 2 &pcfg_pull_up>, - /* uart2_txm1 */ - <1 RK_PD5 2 &pcfg_pull_up>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rxm0 */ - <1 RK_PA0 2 &pcfg_pull_up>, - /* uart3_txm0 */ - <1 RK_PA1 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m0_ctsn: uart3m0-ctsn { - rockchip,pins = - /* uart3m0_ctsn */ - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m0_rtsn: uart3m0-rtsn { - rockchip,pins = - /* uart3m0_rtsn */ - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rxm1 */ - <3 RK_PC0 4 &pcfg_pull_up>, - /* uart3_txm1 */ - <3 RK_PB7 4 &pcfg_pull_up>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rxm0 */ - <1 RK_PA4 2 &pcfg_pull_up>, - /* uart4_txm0 */ - <1 RK_PA6 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m0_ctsn: uart4m0-ctsn { - rockchip,pins = - /* uart4m0_ctsn */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m0_rtsn: uart4m0-rtsn { - rockchip,pins = - /* uart4m0_rtsn */ - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rxm1 */ - <3 RK_PB1 4 &pcfg_pull_up>, - /* uart4_txm1 */ - <3 RK_PB2 4 &pcfg_pull_up>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rxm0 */ - <2 RK_PA1 3 &pcfg_pull_up>, - /* uart5_txm0 */ - <2 RK_PA2 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <1 RK_PD7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <2 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rxm1 */ - <3 RK_PC3 4 &pcfg_pull_up>, - /* uart5_txm1 */ - <3 RK_PC2 4 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rxm0 */ - <2 RK_PA3 3 &pcfg_pull_up>, - /* uart6_txm0 */ - <2 RK_PA4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rxm1 */ - <1 RK_PD6 3 &pcfg_pull_up>, - /* uart6_txm1 */ - <1 RK_PD5 3 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rxm0 */ - <2 RK_PA5 3 &pcfg_pull_up>, - /* uart7_txm0 */ - <2 RK_PA6 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <2 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <2 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rxm1 */ - <3 RK_PC5 4 &pcfg_pull_up>, - /* uart7_txm1 */ - <3 RK_PC4 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rxm2 */ - <4 RK_PA3 4 &pcfg_pull_up>, - /* uart7_txm2 */ - <4 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rxm0 */ - <2 RK_PC6 2 &pcfg_pull_up>, - /* uart8_txm0 */ - <2 RK_PC5 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <2 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <2 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rxm1 */ - <3 RK_PA0 4 &pcfg_pull_up>, - /* uart8_txm1 */ - <2 RK_PD7 4 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rxm0 */ - <2 RK_PA7 3 &pcfg_pull_up>, - /* uart9_txm0 */ - <2 RK_PB0 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <2 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <2 RK_PC3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rxm1 */ - <4 RK_PC6 4 &pcfg_pull_up>, - /* uart9_txm1 */ - <4 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rxm2 */ - <4 RK_PA5 4 &pcfg_pull_up>, - /* uart9_txm2 */ - <4 RK_PA4 4 &pcfg_pull_up>; - }; - }; - - vop { - /omit-if-no-ref/ - vopm0_pins: vopm0-pins { - rockchip,pins = - /* vop_pwmm0 */ - <0 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - vopm1_pins: vopm1-pins { - rockchip,pins = - /* vop_pwmm1 */ - <3 RK_PC4 2 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - spi0-hs { - /omit-if-no-ref/ - spi0m0_pins_hs: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0_hs: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1_hs: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_pins_hs: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0_hs: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1-hs { - /omit-if-no-ref/ - spi1m0_pins_hs: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0_hs: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1_hs: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_pins_hs: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0_hs: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2-hs { - /omit-if-no-ref/ - spi2m0_pins_hs: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0_hs: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1_hs: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins_hs: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0_hs: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1_hs: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3-hs { - /omit-if-no-ref/ - spi3m0_pins_hs: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0_hs: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1_hs: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_pins_hs: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0_hs: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1_hs: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; - }; - }; - - gmac-txd-level3 { - /omit-if-no-ref/ - gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; - }; - }; - - gmac-txc-level2 { - /omit-if-no-ref/ - gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; -}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index 44d4fc9686..25a0c05737 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -3,6 +3,7 @@ /dts-v1/; #include <arm64/rockchip/rk3568-rock-3a.dts> +#include "rk356x.dtsi" / { chosen: chosen { diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi deleted file mode 100644 index 3c458754af..0000000000 --- a/arch/arm/dts/rk3568.dtsi +++ /dev/null @@ -1,1084 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include <dt-bindings/clock/rk3568-cru.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "rockchip,rk3568"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1150000>; - clock-latency-ns = <40000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1150000>; - opp-suspend; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <975000 975000 1150000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1050000 1050000 1150000>; - }; - - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - }; - - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - pinctrl-0 = <&clk32k_out0>; - pinctrl-names = "default"; - #clock-cells = <0>; - }; - - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - usb_host0_xhci: usb@fcc00000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG0>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - usb_host1_xhci: usb@fd000000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "host"; - phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG1>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd100000>; - mbi-ranges = <296 24>; - msi-controller; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb2phy0: usb2-phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&usb2phy0>; - clock-output-names = "usb480m_phy"; - rockchip,usbgrf = <&usb2phy0_grf>; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2-phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - rockchip,usbgrf = <&usb2phy1_grf>; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - combphy0_us: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <24000000>; - resets = <&cru SRST_PIPEPHY0>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - status = "disabled"; - }; - - combphy1_usq: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <24000000>; - resets = <&cru SRST_PIPEPHY1>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - status = "disabled"; - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipegrf", "syscon"; - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - rockchip,grf = <&grf>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - rockchip,grf = <&grf>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, - <&cru PCLK_XPCS>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, - <&cru PCLK_XPCS>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: mmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - dmac0: dmac@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dmac@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@fe600000 { - compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi new file mode 100644 index 0000000000..923e18e7cc --- /dev/null +++ b/arch/arm/dts/rk356x.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + chosen { + barebox,bootsource-mmc0 = &sdhci; + barebox,bootsource-mmc1 = &sdmmc0; + barebox,bootsource-mmc2 = &sdmmc1; + }; + + dmc: memory-controller { + compatible = "rockchip,rk3568-dmc"; + rockchip,pmu = <&pmugrf>; + }; + + otp: nvmem@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x0 0xfe38c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_id: id@a { + reg = <0x0a 0x10>; + }; + }; + + rng: rng@fe388000 { + compatible = "rockchip,rk3568-rng", "rockchip,cryptov2-rng"; + reg = <0x0 0xfe388000 0x0 0x2000>; + clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; + clock-names = "trng_clk", "trng_hclk"; + resets = <&cru SRST_TRNG_NS>; + }; +}; diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts new file mode 100644 index 0000000000..ddff76028e --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/rockchip/rk3588-rock-5b.dts> +#include "rk3588.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + mmc1 = &sdmmc; + }; + + chosen: chosen { + environment-emmc { + compatible = "barebox,environment"; + device-path = &environment_emmc; + status = "disabled"; + }; + + environment-sd { + compatible = "barebox,environment"; + device-path = &environment_sd; + status = "disabled"; + }; + }; +}; + +&sdhci { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_emmc: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; + +&sdmmc { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_sd: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; + +&pcie3x4 { + /* Does not work in barebox (missing phy driver) */ + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie2x1l2 { + /* + * Originally in upstream dts this is: + * ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + * <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + * <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + * + * Overwriting this shouldn't be necessary, but without it PCI doesn't + * work. We have some deficiency in the PCI driver that causes this. + */ + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; +}; + +&pcie2x1l0 { + /* Does not work in barebox */ + status = "disabled"; +}; + +&usb_host0_ehci { + /* Does not work in barebox (missing phy driver) */ + status = "disabled"; +}; + +&usb_host1_ehci { + /* Does not work in barebox (missing phy driver) */ + status = "disabled"; +}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi new file mode 100644 index 0000000000..0aef30eaff --- /dev/null +++ b/arch/arm/dts/rk3588.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/phy/phy.h> +#include "rk3588s.dtsi" + +/ { +}; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi new file mode 100644 index 0000000000..6572588ad6 --- /dev/null +++ b/arch/arm/dts/rk3588s.dtsi @@ -0,0 +1,12 @@ +/ { + dmc: memory-controller { + compatible = "rockchip,rk3588-dmc"; + rockchip,pmu = <&pmu1grf>; + }; +}; + +&scmi_clk { + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, + <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>, <816000000>; +}; diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi index 2301ad135b..658292792f 100644 --- a/arch/arm/dts/sama5d3.dtsi +++ b/arch/arm/dts/sama5d3.dtsi @@ -6,18 +6,5 @@ }; }; -&ebi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - -}; - -&nand_controller { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - -}; +/* Will be automatically read back from HW */ +/delete-node/ &{/memory@20000000}; diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi new file mode 100644 index 0000000000..d7dbba667d --- /dev/null +++ b/arch/arm/dts/sama5d4.dtsi @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/ { + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; +}; + +/delete-node/ &{/memory@20000000}; diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts index 6071dbfb49..fbfdc9a882 100644 --- a/arch/arm/dts/socfpga_arria10_achilles.dts +++ b/arch/arm/dts/socfpga_arria10_achilles.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ /dts-v1/; -#include <arm/socfpga_arria10.dtsi> +#include <arm/intel/socfpga/socfpga_arria10.dtsi> / { model = "Reflex SOCFPGA Arria 10 Achilles"; @@ -108,19 +108,19 @@ }; }; -&{/soc/clkmgr@ffd04000/clocks/osc1} { +&osc1 { clock-frequency = <25000000>; }; -&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} { +&cb_intosc_hs_div2_clk { clock-frequency = <0>; }; -&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} { +&cb_intosc_ls_clk { clock-frequency = <60000000>; }; -&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} { +&f2s_free_clk { clock-frequency = <200000000>; }; diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts index 3f551755cb..84d4534cc6 100644 --- a/arch/arm/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -#include <arm/socfpga_arria10_mercury_aa1.dts> + +/dts-v1/; + +#include <arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi> / { aliases { @@ -17,20 +20,20 @@ }; // provide reset-names until fixed in the upstream dts. Binding prescribes this property. -&{/soc/dwmmc0@ff808000} { +&mmc { reset-names = "reset"; }; // This clock is unused, but fixed-clocks need to have a clock-frequency set -&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} { +&cb_intosc_hs_div2_clk { clock-frequency = <0>; }; -&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} { +&cb_intosc_ls_clk { clock-frequency = <60000000>; }; -&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} { +&f2s_free_clk { clock-frequency = <200000000>; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index c737b091a7..479c81476d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <arm/socfpga_cyclone5_de0_nano_soc.dts> +#include <arm/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts> #include "socfpga.dtsi" / { diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index da6da02381..4a47773a78 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -5,7 +5,7 @@ * Copyright (C) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> */ -#include <arm/socfpga_cyclone5.dtsi> +#include <arm/intel/socfpga/socfpga_cyclone5.dtsi> #include "socfpga.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index f0a6ae98ed..ef1f9af9cf 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <arm/socfpga_cyclone5_socdk.dts> +#include <arm/intel/socfpga/socfpga_cyclone5_socdk.dts> #include "socfpga.dtsi" / { @@ -31,22 +31,6 @@ }; }; -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <0>; - spi-max-frequency = <108000000>; - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; +&flash0 { + compatible = "n25q00"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index 27d2087a33..0c377477f3 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <arm/socfpga_cyclone5_sockit.dts> +#include <arm/intel/socfpga/socfpga_cyclone5_sockit.dts> #include "socfpga.dtsi" / { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e731b55a6c..627a306b8a 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <arm/socfpga_cyclone5_socrates.dts> +#include <arm/intel/socfpga/socfpga_cyclone5_socrates.dts> #include "socfpga.dtsi" / { @@ -34,52 +34,39 @@ }; }; -&qspi { - status = "okay"; +&flash { + compatible = "n25q00"; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <0>; - spi-max-frequency = <100000000>; - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@0 { - label = "prebootloader0"; - reg = <0x00000 0x10000>; - }; + partition@0 { + label = "prebootloader0"; + reg = <0x00000 0x10000>; + }; - partition@1 { - label = "prebootloader1"; - reg = <0x10000 0x10000>; - }; + partition@1 { + label = "prebootloader1"; + reg = <0x10000 0x10000>; + }; - partition@2 { - label = "prebootloader2"; - reg = <0x20000 0x10000>; - }; + partition@2 { + label = "prebootloader2"; + reg = <0x20000 0x10000>; + }; - partition@3 { - label = "prebootloader3"; - reg = <0x30000 0x10000>; - }; + partition@3 { + label = "prebootloader3"; + reg = <0x30000 0x10000>; + }; - partition@4 { - label = "barebox"; - reg = <0x40000 0x80000>; - }; + partition@4 { + label = "barebox"; + reg = <0x40000 0x80000>; + }; - partition@5 { - label = "data"; - reg = <0xc0000 0x1f40000>; - }; + partition@5 { + label = "data"; + reg = <0xc0000 0x1f40000>; }; }; diff --git a/arch/arm/dts/state-example.dtsi b/arch/arm/dts/state-example.dtsi index 490ee7840b..4572168336 100644 --- a/arch/arm/dts/state-example.dtsi +++ b/arch/arm/dts/state-example.dtsi @@ -89,28 +89,29 @@ }; -&ecspi3 { - flash@0 { - backend_state_nor: partition@120000 { - }; - }; +backend_state_nor: &{ecspi3/flash@0/partitions/partition@120000} { }; -&gpmi { - backend_state_nand: partition@500000 { +/* Reduce barebox partition size from 16M to 15M */ +&{gpmi/partitions/partition@0} { + reg = <0x0 0xf00000>; +}; + +&{gpmi/partitions} { + backend_state_nand: partition@f00000 { + label = "barebox-state"; + reg = <0xf00000 0x100000>; }; }; -&i2c1 { - eeprom@50 { - partitions { - compatible = "fixed-partitions"; - #size-cells = <1>; - #address-cells = <1>; - backend_state_eeprom: state@400 { - reg = <0x400 0x400>; - label = "state-eeprom"; - }; +&som_eeprom { /* On I2C1 */ + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + backend_state_eeprom: state@400 { + reg = <0x400 0x400>; + label = "state-eeprom"; }; }; }; @@ -125,4 +126,4 @@ label = "state-sd"; }; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/stm32mp1-scmi-smc.dtsi b/arch/arm/dts/stm32mp1-scmi-smc.dtsi new file mode 100644 index 0000000000..590df657e9 --- /dev/null +++ b/arch/arm/dts/stm32mp1-scmi-smc.dtsi @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ + +/ { + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi0_shm>; + arm,smc-id = <0x82002000>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + soc { + sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi0_shm: scmi_shm@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + + scmi1_shm: scmi_shm@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x80>; + }; + }; + }; +}; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 2ecad85f08..89a7ffcb81 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -12,3 +12,7 @@ reg = <0x5a003000 0x1000>; }; }; + +&iwdg2 { + barebox,restart-warm-bootrom; +}; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index 104886e8af..5f0f52d005 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -1,12 +1,17 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -#include <arm/stm32mp135f-dk.dts> +#include <arm/st/stm32mp135f-dk.dts> #include "stm32mp131.dtsi" / { - model = "STM32MP153F-DK"; + model = "STM32MP135F-DK"; chosen { stdout-path = "serial0:115200n8"; + + environment { + compatible = "barebox,environment"; + device-path = &sdmmc1, "partname:barebox-environment"; + }; }; }; diff --git a/arch/arm/dts/stm32mp151-prtt1l.dtsi b/arch/arm/dts/stm32mp151-prtt1l.dtsi index 80ae72dee2..fffa64841b 100644 --- a/arch/arm/dts/stm32mp151-prtt1l.dtsi +++ b/arch/arm/dts/stm32mp151-prtt1l.dtsi @@ -4,9 +4,9 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <arm/stm32mp151.dtsi> -#include <arm/stm32mp15-pinctrl.dtsi> -#include <arm/stm32mp15xxad-pinctrl.dtsi> +#include <arm/st/stm32mp151.dtsi> +#include <arm/st/stm32mp15-pinctrl.dtsi> +#include <arm/st/stm32mp15xxad-pinctrl.dtsi> #include "stm32mp151.dtsi" @@ -56,6 +56,7 @@ phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; + g-tx-fifo-size = <128 128 128 16>; }; &usbphyc { diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 7b07aaf7cf..d3e924dc00 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -31,22 +31,24 @@ compatible = "st,stm32mp1-ddr"; reg = <0x5a003000 0x1000>; }; - - tamp@5c00a000 { - compatible = "simple-bus", "syscon", "simple-mfd"; - reg = <0x5c00a000 0x400>; - - reboot_mode_tamp: reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x150>; /* reg20 */ - mask = <0xff>; - mode-normal = <0>; - mode-loader = <0xBB>; - mode-recovery = <0xBC>; - }; - }; }; &bsec { barebox,provide-mac-address = <ðernet0 0x39>; }; + +&iwdg2 { + barebox,restart-warm-bootrom; +}; + +&tamp { + reboot_mode_tamp: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x150>; /* reg20 */ + mask = <0xffff>; + mode-normal = <0>; + mode-loader = <0xBB>; + mode-recovery = <0xBC>; + barebox,mode-serial = <0xFF>; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 0000000000..7092b3af9f --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +#include <arm/st/stm32mp157a-dk1-scmi.dts> +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 7a907cc314..d3395b0d95 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -4,5 +4,5 @@ * Author: Alexandre Torgue <alexandre.torgue@st.com>. */ -#include <arm/stm32mp157a-dk1.dts> +#include <arm/st/stm32mp157a-dk1.dts> #include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 0000000000..7f01531986 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +#include <arm/st/stm32mp157c-dk2-scmi.dts> +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 98525abd71..e3840153ac 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -4,5 +4,5 @@ * Author: Alexandre Torgue <alexandre.torgue@st.com>. */ -#include <arm/stm32mp157c-dk2.dts> +#include <arm/st/stm32mp157c-dk2.dts> #include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 0000000000..7cd279da4c --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) + +#include <arm/st/stm32mp157c-ev1-scmi.dts> +#include "stm32mp151.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &sdmmc1, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &sdmmc2, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 742eca7a33..f1ca0cf997 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR X11) -#include <arm/stm32mp157c-ev1.dts> +#include <arm/st/stm32mp157c-ev1.dts> #include "stm32mp151.dtsi" / { diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts b/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts new file mode 100644 index 0000000000..a7674cf0b3 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +#include "stm32mp157c-lxa-mc1.dts" +#include "stm32mp1-scmi-smc.dtsi" + +/ { + model = "Linux Automation MC-1 SCMI board"; + compatible = "lxa,stm32mp157c-mc1-scmi", "lxa,stm32mp157c-mc1", + "oct,stm32mp15xx-osd32", "st,stm32mp157"; + +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/dts/stm32mp157c-lxa-mc1.dts index f89c085280..1220a77c1b 100644 --- a/arch/arm/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/dts/stm32mp157c-lxa-mc1.dts @@ -3,7 +3,7 @@ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix */ -#include <arm/stm32mp157c-lxa-mc1.dts> +#include <arm/st/stm32mp157c-lxa-mc1.dts> #include "stm32mp151.dtsi" / { diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi deleted file mode 100644 index 1e5bd8bccb..0000000000 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. - */ - -/dts-v1/; - -#include <arm/stm32mp157.dtsi> -#include <arm/stm32mp15xc.dtsi> -#include <arm/stm32mp15-pinctrl.dtsi> -#include <arm/stm32mp15xxac-pinctrl.dtsi> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - model = "Seeed Studio Odyssey-STM32MP157C SOM"; - compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; - }; - - led { - compatible = "gpio-leds"; - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gpu { - contiguous-area = <&gpu_reserved>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO1 0>; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO2 0>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = <IT_CURLIM_LDO4 0>; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO6 0>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc2_d47_pins_a { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - }; -}; - -&sdmmc2_d47_sleep_pins_a { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ - }; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e395bdec9..9c9fd34ccd 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -3,7 +3,7 @@ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix */ -#include "stm32mp157c-odyssey.dtsi" +#include <arm/st/stm32mp157c-odyssey.dts> #include "stm32mp151.dtsi" / { @@ -21,7 +21,3 @@ }; }; }; - -&phy0 { - reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dtsi b/arch/arm/dts/stm32mp157c-odyssey.dtsi deleted file mode 100644 index 85a4f313ae..0000000000 --- a/arch/arm/dts/stm32mp157c-odyssey.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. - */ - -/dts-v1/; - -#include "stm32mp157c-odyssey-som.dtsi" - -/ { - model = "Seeed Studio Odyssey-STM32MP157C Board"; - compatible = "seeed,stm32mp157c-odyssey", - "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { /* KSZ9031RN */ - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts index 0818f8d9ad..6ad978f453 100644 --- a/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts +++ b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts @@ -6,12 +6,8 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <arm/stm32mp157.dtsi> -#include <arm/stm32mp15xc.dtsi> -#include <arm/stm32mp15-pinctrl.dtsi> -#include <arm/stm32mp15xxac-pinctrl.dtsi> -#include "stm32mp157c-phycore-stm32mp15-som.dtsi" +#include <arm/st/stm32mp157c-phycore-stm32mp1-3.dts> +#include "stm32mp151.dtsi" / { model = "PHYTEC phyCORE-STM32MP1-3 SoM"; @@ -32,10 +28,18 @@ }; }; -&sdmmc1 { - status = "okay"; -}; - -&sdmmc2 { - status = "okay"; +ðernet0_rgmii_pins_d { + /* + * Kernel uses ETH_RGMII_CLK125 instead of ETH_RGMII_GTX_CLK. Drop this + * once it is fixed upstream. + */ + pins1 { + pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + }; }; diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp157c-phycore-stm32mp15-pinctrl.dtsi deleted file mode 100644 index 011d73ec3f..0000000000 --- a/arch/arm/dts/stm32mp157c-phycore-stm32mp15-pinctrl.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD <dom.vovard@linrt.com>. - */ -#include <arm/stm32mp15-pinctrl.dtsi> - -ðernet0_rgmii_pins_a { - pins1 { - pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; -}; - -&pinctrl { - sdmmc1_dir_pins_b: sdmmc1-dir-1 { - pins1 { - pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; -}; - -&sdmmc1_b4_pins_a { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; -}; - -&sdmmc2_d47_pins_a { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; -}; - -&uart4_pins_a { - pins1 { - pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; -}; diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/dts/stm32mp157c-phycore-stm32mp15-som.dtsi deleted file mode 100644 index a40e59ae2e..0000000000 --- a/arch/arm/dts/stm32mp157c-phycore-stm32mp15-som.dtsi +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD <dom.vovard@linrt.com>. - */ - -#include "stm32mp157c-phycore-stm32mp15-pinctrl.dtsi" -#include <dt-bindings/net/ti-dp83867.h> -#include "stm32mp151.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - pwr_irq: pwr@50001020 { - compatible = "st,stm32mp1-pwr"; - reg = <0x50001020 0x100>; - }; -}; - -&bsec { - board_id: board_id@ec { - reg = <0xec 0x4>; - st,non-secure-otp; - }; -}; - -&clk_hse { - st,digbypass; -}; - -&cpu0 { - cpu-supply = <&vddcore>; -}; - -&cpu1 { - cpu-supply = <&vddcore>; -}; - -ðernet0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - max-speed = <1000>; - st,eth-clk-sel; - status = "okay"; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_eth_2v5: ldo2 { - regulator-name = "vdd_eth_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - }; - - vdd_eth_1v0: ldo6 { - regulator-name = "vdd_eth_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - regulator-active-discharge = <1>; - }; - }; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&sdmmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - status = "disabled"; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb-role-switch; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 027c2e5905..186985545b 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -1,4 +1,4 @@ -#include <arm/tegra124-jetson-tk1.dts> +#include <arm/nvidia/tegra124-jetson-tk1.dts> #include "tegra124.dtsi" / { diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ce618db78c..abfa5f47ba 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -2,41 +2,41 @@ / { aliases { - mmc0 = "/sdhci@700b0000/"; - mmc1 = "/sdhci@700b0200/"; - mmc2 = "/sdhci@700b0400/"; - mmc3 = "/sdhci@700b0600/"; + mmc0 = &{/mmc@700b0000}; + mmc1 = &{/mmc@700b0200}; + mmc2 = &{/mmc@700b0400}; + mmc3 = &{/mmc@700b0600}; }; +}; - pcie-controller@01003000 { - phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; - phy-names = "pcie"; - }; +&{/pcie@1003000} { + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; +}; - padctl@7009f000 { - pinctrl-0 = <&padctl_default>; - pinctrl-names = "default"; - #phy-cells = <1>; +&padctl { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + #phy-cells = <1>; - padctl_default: pinmux { - usb3 { - nvidia,lanes = "pcie-0", "pcie-1"; - nvidia,function = "usb3"; - nvidia,iddq = <0>; - }; + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; - pcie { - nvidia,lanes = "pcie-2", "pcie-3", - "pcie-4"; - nvidia,function = "pcie"; - nvidia,iddq = <0>; - }; + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; - sata { - nvidia,lanes = "sata-0"; - nvidia,function = "sata"; - nvidia,iddq = <0>; - }; + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; }; }; }; diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts index da5ef7a7e7..e8bd8feb31 100644 --- a/arch/arm/dts/tegra20-colibri-iris.dts +++ b/arch/arm/dts/tegra20-colibri-iris.dts @@ -9,72 +9,70 @@ chosen { stdout-path = &uarta; }; +}; - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - hdint { - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - i2cddc { - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdio4 { - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uarta { - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; +&{/host1x@50000000/hdmi@54280000} { + status = "okay"; +}; - uartd { - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - }; +&pinmux { + hdint { + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; - serial@70006000 { - status = "okay"; + i2cddc { + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; - serial@70006300 { - status = "okay"; + sdio4 { + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; - i2c_ddc: i2c@7000c400 { - status = "okay"; + uarta { + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; - usb@c5000000 { - status = "okay"; + uartd { + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; +}; - usb-phy@c5000000 { - status = "okay"; - }; +&uarta { + status = "okay"; +}; - usb@c5008000 { - status = "okay"; - }; +&uartd { + status = "okay"; +}; - usb-phy@c5008000 { - status = "okay"; - }; +i2c_ddc: &i2c2 { + status = "okay"; +}; - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vcc_sd_reg>; - vqmmc-supply = <&vcc_sd_reg>; - }; +&{/usb@c5000000} { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&{/usb@c5008000} { + status = "okay"; +}; + +&phy3 { + status = "okay"; +}; +&{/mmc@c8000600} { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vcc_sd_reg>; + vqmmc-supply = <&vcc_sd_reg>; +}; + +/ { regulator_usb_host_vbus { compatible = "regulator-fixed"; regulator-name = "usb_host_vbus"; diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi index 4f6dc9daf2..a9c2ad8bab 100644 --- a/arch/arm/dts/tegra20-colibri.dtsi +++ b/arch/arm/dts/tegra20-colibri.dtsi @@ -1,2 +1,2 @@ -#include <arm/tegra20-colibri.dtsi> +#include <arm/nvidia/tegra20-colibri.dtsi> #include "tegra20.dtsi" diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index f3a3759ebd..a9019d1959 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -1,2 +1,2 @@ -#include <arm/tegra20-paz00.dts> +#include <arm/nvidia/tegra20-paz00.dts> #include "tegra20.dtsi" diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 995eee4a6e..02425874f6 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,8 +1,8 @@ / { aliases { - mmc0 = "/sdhci@c8000000/"; - mmc1 = "/sdhci@c8000200/"; - mmc2 = "/sdhci@c8000400/"; - mmc3 = "/sdhci@c8000600/"; + mmc0 = &{/mmc@c8000000}; + mmc1 = &{/mmc@c8000200}; + mmc2 = &{/mmc@c8000400}; + mmc3 = &{/mmc@c8000600}; }; }; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 7a9ced6cef..d6aa0e4d13 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include <arm/tegra30.dtsi> +#include <arm/nvidia/tegra30.dtsi> #include "tegra30.dtsi" / { @@ -8,8 +8,8 @@ compatible = "nvidia,beaver", "nvidia,tegra30"; aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; + rtc0 = &pmic; + rtc1 = &{/rtc@7000e000}; serial0 = &uarta; }; @@ -21,766 +21,764 @@ device-path = &emmc, "partname:boot1"; }; }; +}; + +&{/pcie@3000} { + status = "okay"; + pex-clk-supply = <&sys_3v3_pexs_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; - pcie-controller@00003000 { + pci@1,0 { status = "okay"; - pex-clk-supply = <&sys_3v3_pexs_reg>; - vdd-supply = <&ldo1_reg>; - avdd-supply = <&ldo2_reg>; + nvidia,num-lanes = <2>; + }; - pci@1,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; + pci@2,0 { + nvidia,num-lanes = <2>; + }; - pci@2,0 { - nvidia,num-lanes = <2>; - }; + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; +}; + +&{/host1x@50000000/hdmi@54280000} { + status = "okay"; + + vdd-supply = <&sys_3v3_reg>; + pll-supply = <&vio_reg>; + + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmiddc>; +}; + +&pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <2>; + state_default: pinmux { + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_gpio { + nvidia,pins = "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_rst { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + dap { + nvidia,pins = "clk1_req_pee2", + "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dev3 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap1 { + nvidia,pins = "dap1_fs_pn0", "dap1_dout_pn2", + "dap1_din_pn1", "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap3 { + nvidia,pins = "dap3_fs_pp0", "dap3_dout_pp2", + "dap3_din_pp1", "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap4 { + nvidia,pins = "dap4_fs_pp4", "dap4_dout_pp6", + "dap4_din_pp5", "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pex_in { + nvidia,pins = "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7", + "pex_l2_clkreq_n_pcc7", + "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_out { + nvidia,pins = "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5", + "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; + sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; + gpv { + nvidia,pins = "drive_gpv"; + nvidia,pull-up-strength = <16>; + }; + uarta { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,tristate = <0>; + }; + pu { + nvidia,pins = "pu0", "pu1", "pu2", "pu3", + "pu4", "pu5", "pu6"; + nvidia,function = "rsvd4"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + uartb { + nvidia,pins = "uart2_txd_pc2", + "uart2_rxd_pc3", + "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uartc { + nvidia,pins = "uart3_txd_pw6", + "uart3_rxd_pw7", + "uart3_cts_n_pa1", + "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uartd { + nvidia,pins = "ulpi_clk_py0", "ulpi_dir_py1", + "ulpi_nxt_py2", "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + i2c1 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + i2c2 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + i2c3 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + i2c4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + i2cpwr { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + spi1 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_up { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + spi4 { + nvidia,pins = "gmi_a16_pj7", "gmi_a17_pb0", + "gmi_a18_pb1", "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spdif { + nvidia,pins = "spdif_out_pk5", "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + hdmi_int { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ddr { + nvidia,pins = "vi_d10_pt2", "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + }; + ddr_up { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi { + nvidia,pins = "vi_d4_pl2", "vi_mclk_pt1", + "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "pv2", "pu0", "owr"; + nvidia,function = "owr"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + lcd { + nvidia,pins = "lcd_pwr1_pc1", "lcd_pwr2_pc6", + "lcd_sdin_pz2", "lcd_sdout_pn5", + "lcd_wr_n_pz3", "lcd_cs0_n_pn4", + "lcd_dc0_pn6", "lcd_sck_pz4", + "lcd_pwr0_pb2", "lcd_pclk_pb3", + "lcd_de_pj1", "lcd_hsync_pj3", + "lcd_vsync_pj4", "lcd_d0_pe0", + "lcd_d1_pe1", "lcd_d2_pe2", + "lcd_d3_pe3", "lcd_d4_pe4", + "lcd_d5_pe5", "lcd_d6_pe6", + "lcd_d7_pe7", "lcd_d8_pf0", + "lcd_d9_pf1", "lcd_d10_pf2", + "lcd_d11_pf3", "lcd_d12_pf4", + "lcd_d13_pf5", "lcd_d14_pf6", + "lcd_d15_pf7", "lcd_d16_pm0", + "lcd_d17_pm1", "lcd_d18_pm2", + "lcd_d19_pm3", "lcd_d20_pm4", + "lcd_d21_pm5", "lcd_d22_pm6", + "lcd_d23_pm7", "lcd_cs1_n_pw0", + "lcd_m1_pw1", "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kbc { + nvidia,pins = "kb_row0_pr0", "kb_row1_pr1", + "kb_row2_pr2", "kb_row3_pr3", + "kb_row4_pr4", "kb_row5_pr5", + "kb_row6_pr6", "kb_row7_pr7", + "kb_row9_ps1", "kb_row8_ps0", + "kb_row10_ps2", "kb_row11_ps3", + "kb_row12_ps4", "kb_row13_ps5", + "kb_row14_ps6", "kb_row15_ps7", + "kb_col0_pq0", "kb_col1_pq1", + "kb_col2_pq2", "kb_col3_pq3", + "kb_col4_pq4", "kb_col5_pq5", + "kb_col6_pq6", "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_vi { + nvidia,pins = "vi_d1_pd5", "vi_d2_pl0", + "vi_d3_pl1", "vi_d5_pl3", + "vi_d7_pl5", "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pbb0 { + nvidia,pins = "pbb0", "pbb7", "pcc1", "pcc2"; + nvidia,function = "i2s4"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_pu1 { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "rsvd1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + gpio_pv0 { + nvidia,pins = "pv0", "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + gpio_pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + gpio_gmi { + nvidia,pins = "spi2_sck_px2", "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + gpio_gmi_ad { + nvidia,pins = "gmi_ad10_ph2", "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + gpio_gmi_ad_up { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + gpio_gmi_iordy_up { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + pwm0 { + nvidia,pins = "gmi_ad8_ph0", "pu3"; + nvidia,function = "pwm0"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwm1 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwm2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwm3 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + extperiph1 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + extperiph2 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + extperiph3 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + jtag { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sysclk { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + vi_pclk { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,io-reset = <TEGRA_PIN_DISABLE>; + }; + unused { + nvidia,pins = "gmi_adv_n_pk0", "gmi_clk_pk1", + "gmi_cs3_n_pk4", "gmi_ad0_pg0", + "gmi_ad1_pg1", "gmi_ad2_pg2", + "gmi_ad3_pg3", "gmi_ad4_pg4", + "gmi_ad5_pg5", "gmi_ad6_pg6", + "gmi_ad7_pg7", "gmi_ad9_ph1", + "gmi_ad11_ph3", "gmi_wr_n_pi0", + "gmi_oe_n_pi1", "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + unused_pu { + nvidia,pins = "gmi_wait_pi7", "gmi_cs7_n_pi6", + "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; }; +}; - host1x@50000000 { - hdmi@54280000 { - status = "okay"; +&uarta { + status = "okay"; +}; - vdd-supply = <&sys_3v3_reg>; - pll-supply = <&vio_reg>; +&{/i2c@7000c000} { + status = "okay"; + clock-frequency = <100000>; +}; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; +&{/i2c@7000c400} { + status = "okay"; + clock-frequency = <100000>; +}; + +&{/i2c@7000c500} { + status = "okay"; + clock-frequency = <100000>; +}; + +hdmiddc: &{/i2c@7000c700} { + status = "okay" ; + clock-frequency = <100000>; +}; + +&{/i2c@7000d000} { + status = "okay"; + clock-frequency = <100000>; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; }; - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sdmmc3_gpio { - nvidia,pins = "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sdmmc4_rst { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - crt { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - dap { - nvidia,pins = "clk1_req_pee2", - "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - dev3 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - dap1 { - nvidia,pins = "dap1_fs_pn0", "dap1_dout_pn2", - "dap1_din_pn1", "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - dap3 { - nvidia,pins = "dap3_fs_pp0", "dap3_dout_pp2", - "dap3_din_pp1", "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - dap4 { - nvidia,pins = "dap4_fs_pp4", "dap4_dout_pp6", - "dap4_din_pp5", "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - pex_in { - nvidia,pins = "pex_l0_prsnt_n_pdd0", - "pex_l0_clkreq_n_pdd2", - "pex_l2_prsnt_n_pdd7", - "pex_l2_clkreq_n_pcc7", - "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pex_out { - nvidia,pins = "pex_l0_rst_n_pdd1", - "pex_l1_rst_n_pdd5", - "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4", - "pex_l1_clkreq_n_pdd6"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - }; - sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; - gpv { - nvidia,pins = "drive_gpv"; - nvidia,pull-up-strength = <16>; - }; - uarta { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,tristate = <0>; - }; - pu { - nvidia,pins = "pu0", "pu1", "pu2", "pu3", - "pu4", "pu5", "pu6"; - nvidia,function = "rsvd4"; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - uartb { - nvidia,pins = "uart2_txd_pc2", - "uart2_rxd_pc3", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - uartc { - nvidia,pins = "uart3_txd_pw6", - "uart3_rxd_pw7", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - uartd { - nvidia,pins = "ulpi_clk_py0", "ulpi_dir_py1", - "ulpi_nxt_py2", "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - i2c1 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - i2c2 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - i2c3 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - i2c4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - i2cpwr { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - spi1 { - nvidia,pins = "spi1_mosi_px4", - "spi1_sck_px5", - "spi1_cs0_n_px6", - "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - spi2_up { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - }; - spi4 { - nvidia,pins = "gmi_a16_pj7", "gmi_a17_pb0", - "gmi_a18_pb1", "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - spdif { - nvidia,pins = "spdif_out_pk5", "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - hdmi_int { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - hdmi_cec { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - ddr { - nvidia,pins = "vi_d10_pt2", "vi_vsync_pd6", - "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; - }; - ddr_up { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - vi { - nvidia,pins = "vi_d4_pl2", "vi_mclk_pt1", - "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - owr { - nvidia,pins = "pv2", "pu0", "owr"; - nvidia,function = "owr"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - lcd { - nvidia,pins = "lcd_pwr1_pc1", "lcd_pwr2_pc6", - "lcd_sdin_pz2", "lcd_sdout_pn5", - "lcd_wr_n_pz3", "lcd_cs0_n_pn4", - "lcd_dc0_pn6", "lcd_sck_pz4", - "lcd_pwr0_pb2", "lcd_pclk_pb3", - "lcd_de_pj1", "lcd_hsync_pj3", - "lcd_vsync_pj4", "lcd_d0_pe0", - "lcd_d1_pe1", "lcd_d2_pe2", - "lcd_d3_pe3", "lcd_d4_pe4", - "lcd_d5_pe5", "lcd_d6_pe6", - "lcd_d7_pe7", "lcd_d8_pf0", - "lcd_d9_pf1", "lcd_d10_pf2", - "lcd_d11_pf3", "lcd_d12_pf4", - "lcd_d13_pf5", "lcd_d14_pf6", - "lcd_d15_pf7", "lcd_d16_pm0", - "lcd_d17_pm1", "lcd_d18_pm2", - "lcd_d19_pm3", "lcd_d20_pm4", - "lcd_d21_pm5", "lcd_d22_pm6", - "lcd_d23_pm7", "lcd_cs1_n_pw0", - "lcd_m1_pw1", "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kbc { - nvidia,pins = "kb_row0_pr0", "kb_row1_pr1", - "kb_row2_pr2", "kb_row3_pr3", - "kb_row4_pr4", "kb_row5_pr5", - "kb_row6_pr6", "kb_row7_pr7", - "kb_row9_ps1", "kb_row8_ps0", - "kb_row10_ps2", "kb_row11_ps3", - "kb_row12_ps4", "kb_row13_ps5", - "kb_row14_ps6", "kb_row15_ps7", - "kb_col0_pq0", "kb_col1_pq1", - "kb_col2_pq2", "kb_col3_pq3", - "kb_col4_pq4", "kb_col5_pq5", - "kb_col6_pq6", "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_vi { - nvidia,pins = "vi_d1_pd5", "vi_d2_pl0", - "vi_d3_pl1", "vi_d5_pl3", - "vi_d7_pl5", "vi_d8_pl6", - "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pbb0 { - nvidia,pins = "pbb0", "pbb7", "pcc1", "pcc2"; - nvidia,function = "i2s4"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_pu1 { - nvidia,pins = "pu1", "pu2"; - nvidia,function = "rsvd1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - gpio_pv0 { - nvidia,pins = "pv0", "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - }; - gpio_pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - gpio_gmi { - nvidia,pins = "spi2_sck_px2", "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - gpio_gmi_ad { - nvidia,pins = "gmi_ad10_ph2", "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - gpio_gmi_ad_up { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - }; - gpio_gmi_iordy_up { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - }; - pwm0 { - nvidia,pins = "gmi_ad8_ph0", "pu3"; - nvidia,function = "pwm0"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - pwm1 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - pwm2 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - pwm3 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - extperiph1 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - extperiph2 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - extperiph3 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - jtag { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - blink { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - sysclk { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - cam_mclk { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v_in_reg>; + vcc2-supply = <&vdd_5v_in_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v_in_reg>; + vcc5-supply = <&vdd_5v_in_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v_in_reg>; + vccio-supply = <&vdd_5v_in_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; }; - vi_pclk { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,io-reset = <TEGRA_PIN_DISABLE>; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; }; - unused { - nvidia,pins = "gmi_adv_n_pk0", "gmi_clk_pk1", - "gmi_cs3_n_pk4", "gmi_ad0_pg0", - "gmi_ad1_pg1", "gmi_ad2_pg2", - "gmi_ad3_pg3", "gmi_ad4_pg4", - "gmi_ad5_pg5", "gmi_ad6_pg6", - "gmi_ad7_pg7", "gmi_ad9_ph1", - "gmi_ad11_ph3", "gmi_wr_n_pi0", - "gmi_oe_n_pi1", "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,tristate = <TEGRA_PIN_ENABLE>; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; }; - unused_pu { - nvidia,pins = "gmi_wait_pi7", "gmi_cs7_n_pi6", - "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; - }; - }; - serial@70006000 { - status = "okay"; - }; + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; + /* LDO3 is not connected to anything */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; - hdmiddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v_in_reg>; - vcc2-supply = <&vdd_5v_in_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v_in_reg>; - vcc5-supply = <&vdd_5v_in_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v_in_reg>; - vccio-supply = <&vdd_5v_in_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; - }; - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; }; }; - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32"; - reg = <1>; - spi-max-frequency = <20000000>; - }; + tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; }; +}; - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; +&{/spi@7000da00} { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@1 { + compatible = "winbond,w25q32"; + reg = <1>; + spi-max-frequency = <20000000>; }; +}; - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; +&tegra_pmc { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; +}; - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; +&tegra_i2s1 { + status = "okay"; +}; - emmc: sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; +&{/mmc@78000000} { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; +}; - usb@7d004000 { - status = "okay"; - }; +emmc: &{/mmc@78000600} { + status = "okay"; + bus-width = <8>; + non-removable; +}; - phy2: usb-phy@7d004000 { - vbus-supply = <&sys_3v3_reg>; - status = "okay"; - }; +&{/usb@7d004000} { + status = "okay"; +}; - usb@7d008000 { - status = "okay"; - }; +&phy2 { + vbus-supply = <&sys_3v3_reg>; + status = "okay"; +}; - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; +&{/usb@7d008000} { + status = "okay"; +}; +&phy3 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; +}; + +/ { clocks { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 90bd08ba63..2724714f60 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,8 +1,8 @@ / { aliases { - mmc0 = "/sdhci@78000000/"; - mmc1 = "/sdhci@78000200/"; - mmc2 = "/sdhci@78000400/"; - mmc3 = "/sdhci@78000600/"; + mmc0 = &{/mmc@78000000}; + mmc1 = &{/mmc@78000200}; + mmc2 = &{/mmc@78000400}; + mmc3 = &{/mmc@78000600}; }; }; diff --git a/arch/arm/dts/tny_a9260.dts b/arch/arm/dts/tny_a9260.dts new file mode 100644 index 0000000000..2c4df66f7a --- /dev/null +++ b/arch/arm/dts/tny_a9260.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arm/microchip/tny_a9260.dts> +#include "at91sam9260.dtsi" +#include "calao_nand.dtsi" diff --git a/arch/arm/dts/tny_a9g20.dts b/arch/arm/dts/tny_a9g20.dts new file mode 100644 index 0000000000..654a988c44 --- /dev/null +++ b/arch/arm/dts/tny_a9g20.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arm/microchip/tny_a9g20.dts> +#include "at91sam9g20.dtsi" +#include "calao_nand.dtsi" diff --git a/arch/arm/dts/tqma6ul-common.dtsi b/arch/arm/dts/tqma6ul-common.dtsi deleted file mode 100644 index 92b295891c..0000000000 --- a/arch/arm/dts/tqma6ul-common.dtsi +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018 TQ Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -&cpu0 { - arm-supply = <®_arm>; - soc-supply = <®_soc>; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pfuze3000: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - reg_sw1a: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-ramp-delay = <6250>; - /* not used */ - }; - - reg_sw1b_core: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - reg_sw2: sw2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - reg_sw3_ddr: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_swbst: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - /* not used */ - }; - - reg_snvs_3v0: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vccsd: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - }; - - reg_v33_3v3: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vldo1_3v3: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* not used */ - }; - - reg_vldo2: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - /* not used */ - }; - - reg_vldo3: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* not used */ - }; - - reg_vldo4: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-fixed; - regulator-always-on; - }; - }; - }; - - jc42_1a: eeprom-temperature-sensor@1a { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x1a>; - status = "okay"; - }; - - m24c64_50: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - status = "okay"; - }; - - m24c02_52: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - status = "okay"; - }; - - rtc1: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - status = "okay"; - }; -}; - -&iomuxc { - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 - >; - }; - - /* - * currently not used, potentially dangerous if used on - * baseboard - */ - pinctrl_pmic: pmic { - fsl,pins = < - /* PMIC irq */ - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 - >; - }; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: spinor@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <33000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -&snvs_rtc { - status = "disabled"; -}; - -/* eMMC */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz" , "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - - bus-width = <8>; - disable-wp; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; diff --git a/arch/arm/dts/tqma6ulx-common.dtsi b/arch/arm/dts/tqma6ulx-common.dtsi deleted file mode 100644 index 3e398d25ad..0000000000 --- a/arch/arm/dts/tqma6ulx-common.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018 TQ Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -&iomuxc { - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; -}; - -®_sw2 { - regulator-always-on; -}; - -/* eMMC */ -&usdhc2 { - vmmc-supply = <®_sw2>; - vqmmc-supply = <®_vldo4>; -}; diff --git a/arch/arm/dts/usb_a9260.dts b/arch/arm/dts/usb_a9260.dts new file mode 100644 index 0000000000..9eb2db3ff8 --- /dev/null +++ b/arch/arm/dts/usb_a9260.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arm/microchip/usb_a9260.dts> +#include "at91sam9260.dtsi" +#include "calao_nand.dtsi" diff --git a/arch/arm/dts/usb_a9g20.dts b/arch/arm/dts/usb_a9g20.dts new file mode 100644 index 0000000000..a8ed22b7c4 --- /dev/null +++ b/arch/arm/dts/usb_a9g20.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arm/microchip/usb_a9g20.dts> +#include "at91sam9g20.dtsi" +#include "calao_nand.dtsi" diff --git a/arch/arm/dts/versatile-pb.dts b/arch/arm/dts/versatile-pb.dts index d374f54291..d81b7d2715 100644 --- a/arch/arm/dts/versatile-pb.dts +++ b/arch/arm/dts/versatile-pb.dts @@ -1,10 +1,36 @@ -#include <arm/versatile-ab.dts> +#include <arm/arm/versatile-ab.dts> / { model = "ARM Versatile PB"; compatible = "arm,versatile-pb"; + + chosen { + environment-nor { + compatible = "barebox,environment"; + device-path = &env_nor; + }; + }; }; &{/memory} { reg = <0x0 0x04000000>; }; + +&{/flash@34000000} { + partitions { + compatible = "fixed-partitions"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + env_nor: partition@400000 { + label = "bareboxenv"; + reg = <0x400000 0x400000>; + }; + }; +}; diff --git a/arch/arm/dts/vexpress-v2p-ca15.dts b/arch/arm/dts/vexpress-v2p-ca15.dts index 78d0025909..acf4e023d5 100644 --- a/arch/arm/dts/vexpress-v2p-ca15.dts +++ b/arch/arm/dts/vexpress-v2p-ca15.dts @@ -1,4 +1,4 @@ -#include <arm/vexpress-v2p-ca15_a7.dts> +#include <arm/arm/vexpress-v2p-ca15_a7.dts> / { barebox_environment { @@ -28,3 +28,11 @@ }; }; }; + +&{/leds} { + status = "disabled"; +}; + +&{/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/compact-flash@1a0000/} { + status = "disabled"; +}; diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts index a43628e7ce..d1484ff4b0 100644 --- a/arch/arm/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/dts/vexpress-v2p-ca9.dts @@ -1,4 +1,4 @@ -#include <arm/vexpress-v2p-ca9.dts> +#include <arm/arm/vexpress-v2p-ca9.dts> / { barebox_environment { @@ -91,3 +91,15 @@ }; }; }; + +&{/timer@1e000600} { + status = "disabled"; +}; + +&{/bus@40000000/motherboard-bus@40000000/leds/} { + status = "disabled"; +}; + +&{/bus@40000000/motherboard-bus@40000000/iofpga@7,00000000/compact-flash@1a000/} { + status = "disabled"; +}; diff --git a/arch/arm/dts/vf610-ddrmc.dtsi b/arch/arm/dts/vf610-ddrmc.dtsi index 772131ec28..44d933b3e9 100644 --- a/arch/arm/dts/vf610-ddrmc.dtsi +++ b/arch/arm/dts/vf610-ddrmc.dtsi @@ -1,10 +1,12 @@ /* * Include file to switch board DTS form using hardcoded memory node - * to dynamic memory size detection based on DDR controller settings + * (if specified) to dynamic memory size detection based on DDR + * controller settings */ / { /delete-node/ memory; + /delete-node/ memory@80000000; }; &aips1 { diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts index ac2774979e..14d9e74274 100644 --- a/arch/arm/dts/vf610-twr.dts +++ b/arch/arm/dts/vf610-twr.dts @@ -7,7 +7,7 @@ * (at your option) any later version. */ -#include <arm/vf610-twr.dts> +#include <arm/nxp/vf/vf610-twr.dts> #include "vf610.dtsi" #include "vf610-ddrmc.dtsi" diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts index 9226930612..fd06147c8e 100644 --- a/arch/arm/dts/vf610-zii-cfu1.dts +++ b/arch/arm/dts/vf610-zii-cfu1.dts @@ -4,7 +4,7 @@ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations */ -#include <arm/vf610-zii-cfu1.dts> +#include <arm/nxp/vf/vf610-zii-cfu1.dts> #include "vf610-zii-dev.dtsi" @@ -18,12 +18,6 @@ switch-eeprom = &switch0; fiber-eeprom0 = &fiber_eeprom0; }; - - gpio-leds { - led-status { - linux,default-trigger = "heartbeat"; - }; - }; }; &{/gpio-leds/led-status} { diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts index 2949042bc3..ec71b1e43a 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts @@ -4,11 +4,11 @@ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations */ -#include <arm/vf610-zii-dev-rev-b.dts> +#include <arm/nxp/vf/vf610-zii-dev-rev-b.dts> #include "vf610-zii-dev.dtsi" -&{/spi0/flash@0} { +&{/spi-0/flash@0} { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts index c1b3bc86dc..d61b291509 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts @@ -4,7 +4,7 @@ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations */ -#include <arm/vf610-zii-dev-rev-c.dts> +#include <arm/nxp/vf/vf610-zii-dev-rev-c.dts> #include "vf610-zii-dev.dtsi" diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts index 43a13e243d..a6f585ae37 100644 --- a/arch/arm/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/dts/vf610-zii-scu4-aib.dts @@ -2,7 +2,7 @@ // // Copyright (C) 2016-2018 Zodiac Inflight Innovations -#include <arm/vf610-zii-scu4-aib.dts> +#include <arm/nxp/vf/vf610-zii-scu4-aib.dts> #include "vf610-zii-dev.dtsi" diff --git a/arch/arm/dts/vf610-zii-spb4.dtsi b/arch/arm/dts/vf610-zii-spb4.dtsi index f618ca45ee..b8e80be0e9 100644 --- a/arch/arm/dts/vf610-zii-spb4.dtsi +++ b/arch/arm/dts/vf610-zii-spb4.dtsi @@ -14,7 +14,7 @@ */ /dts-v1/; -#include <arm/vf610.dtsi> +#include <arm/nxp/vf/vf610.dtsi> / { model = "ZII VF610 SPB4 Board"; diff --git a/arch/arm/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/dts/vf610-zii-ssmb-dtu.dts index 6ffb7aa62d..7952b09e84 100644 --- a/arch/arm/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/dts/vf610-zii-ssmb-dtu.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -#include <arm/vf610-zii-ssmb-dtu.dts> +#include <arm/nxp/vf/vf610-zii-ssmb-dtu.dts> #include "vf610-zii-dev.dtsi" diff --git a/arch/arm/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/dts/vf610-zii-ssmb-spu3.dts index 5b2460cafa..d6c436b204 100644 --- a/arch/arm/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/dts/vf610-zii-ssmb-spu3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -#include <arm/vf610-zii-ssmb-spu3.dts> +#include <arm/nxp/vf/vf610-zii-ssmb-spu3.dts> #include "vf610-zii-dev.dtsi" diff --git a/arch/arm/dts/vf610.dtsi b/arch/arm/dts/vf610.dtsi index 3060031b8a..d1297e952c 100644 --- a/arch/arm/dts/vf610.dtsi +++ b/arch/arm/dts/vf610.dtsi @@ -9,4 +9,4 @@ mmc0 = &esdhc0; mmc1 = &esdhc1; }; -}; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 3791f743a4..f7a0d70bab 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -8,7 +8,7 @@ clocks = <&clkc 10>, <&clkc 43>; clock-names = "ref_clk", "pclk"; status = "disabled"; - + #address-cells = <1>; #size-cells = <0>; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index a6b1da854b..465758ebf6 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -1,4 +1,4 @@ -#include <arm/zynq-zed.dts> +#include <arm/xilinx/zynq-zed.dts> #include "zynq-7000.dtsi" / { diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts new file mode 100644 index 0000000000..8f5410d5e6 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <arm64/xilinx/zynqmp-zcu102-revA.dts> + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &sdhci1, "partname:0"; + file-path = "barebox.env"; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts new file mode 100644 index 0000000000..3f772f465a --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <arm64/xilinx/zynqmp-zcu102-revB.dts> + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &sdhci1, "partname:0"; + file-path = "barebox.env"; + }; + }; +}; |