diff options
Diffstat (limited to 'arch/arm/mach-at91/include')
53 files changed, 0 insertions, 6468 deletions
diff --git a/arch/arm/mach-at91/include/mach/aic.h b/arch/arm/mach-at91/include/mach/aic.h deleted file mode 100644 index c1f026b60c..0000000000 --- a/arch/arm/mach-at91/include/mach/aic.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause */ -#ifndef __AT91_AIC_H_ -#define __AT91_AIC_H_ - -#include <linux/compiler.h> - -void at91_aic_redir(void __iomem *sfr, u32 key); - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h deleted file mode 100644 index f79175c5e9..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * arch/arm/mach-at91/include/mach/at91_dbgu.h - * - * Debug Unit (DBGU) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B. - */ - -#ifndef AT91_DBGU_H -#define AT91_DBGU_H - -#define AT91_DBGU_CR (0x00) /* Control Register */ -#define AT91_DBGU_RSTRX (1 << 2) /* Reset Receiver */ -#define AT91_DBGU_RSTTX (1 << 3) /* Reset Transmitter */ -#define AT91_DBGU_RXEN (1 << 4) /* Receiver Enable */ -#define AT91_DBGU_RXDIS (1 << 5) /* Receiver Disable */ -#define AT91_DBGU_TXEN (1 << 6) /* Transmitter Enable */ -#define AT91_DBGU_TXDIS (1 << 7) /* Transmitter Disable */ -#define AT91_DBGU_RSTSTA (1 << 8) /* Reset Status Bits */ -#define AT91_DBGU_MR (0x04) /* Mode Register */ -#define AT91_DBGU_NBSTOP_1BIT (0 << 12) /* 1 stop bit */ -#define AT91_DBGU_NBSTOP_1_5BIT (1 << 12) /* 1.5 stop bits */ -#define AT91_DBGU_NBSTOP_2BIT (2 << 12) /* 2 stop bits */ - -#define AT91_DBGU_CHRL_5BIT (0 << 6) /* 5 bit character length */ -#define AT91_DBGU_CHRL_6BIT (1 << 6) /* 6 bit character length */ -#define AT91_DBGU_CHRL_7BIT (2 << 6) /* 7 bit character length */ -#define AT91_DBGU_CHRL_8BIT (3 << 6) /* 8 bit character length */ - -#define AT91_DBGU_PAR_EVEN (0 << 9) /* Even Parity */ -#define AT91_DBGU_PAR_ODD (1 << 9) /* Odd Parity */ -#define AT91_DBGU_PAR_SPACE (2 << 9) /* Space: Force Parity to 0 */ -#define AT91_DBGU_PAR_MARK (3 << 9) /* Mark: Force Parity to 1 */ -#define AT91_DBGU_PAR_NONE (4 << 9) /* No Parity */ - -#define AT91_DBGU_CHMODE_NORMAL (0 << 14) /* Normal mode */ -#define AT91_DBGU_CHMODE_AUTO (1 << 14) /* Automatic Echo */ -#define AT91_DBGU_CHMODE_LOCAL (2 << 14) /* Local Loopback */ -#define AT91_DBGU_CHMODE_REMOTE (3 << 14) /* Remote Loopback */ -#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ -#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (0x14) /* Status Register */ -#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ - -#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - - -/* - * Some AT91 parts that don't have full DEBUG units still support the ID - * and extensions register. - */ -#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ -#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ -#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ -#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ -#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ -#define AT91_CIDR_SRAMSIZ_1K (1 << 16) -#define AT91_CIDR_SRAMSIZ_2K (2 << 16) -#define AT91_CIDR_SRAMSIZ_112K (4 << 16) -#define AT91_CIDR_SRAMSIZ_4K (5 << 16) -#define AT91_CIDR_SRAMSIZ_80K (6 << 16) -#define AT91_CIDR_SRAMSIZ_160K (7 << 16) -#define AT91_CIDR_SRAMSIZ_8K (8 << 16) -#define AT91_CIDR_SRAMSIZ_16K (9 << 16) -#define AT91_CIDR_SRAMSIZ_32K (10 << 16) -#define AT91_CIDR_SRAMSIZ_64K (11 << 16) -#define AT91_CIDR_SRAMSIZ_128K (12 << 16) -#define AT91_CIDR_SRAMSIZ_256K (13 << 16) -#define AT91_CIDR_SRAMSIZ_96K (14 << 16) -#define AT91_CIDR_SRAMSIZ_512K (15 << 16) -#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ -#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ -#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ - -#ifndef __ASSEMBLY__ - -#include <asm/io.h> -static inline void at91_dbgu_setup_ll(void __iomem *dbgu_base, - unsigned mck, - unsigned baudrate) -{ - u32 brgr = mck / (baudrate * 16); - - if ((mck / (baudrate * 16)) % 10 >= 5) - brgr++; - - writel(~0, dbgu_base + AT91_DBGU_IDR); - - writel(AT91_DBGU_RSTRX - | AT91_DBGU_RSTTX - | AT91_DBGU_RXDIS - | AT91_DBGU_TXDIS, - dbgu_base + AT91_DBGU_CR); - - writel(brgr, dbgu_base + AT91_DBGU_BRGR); - - writel(AT91_DBGU_PAR_NONE - | AT91_DBGU_CHMODE_NORMAL - | AT91_DBGU_CHRL_8BIT - | AT91_DBGU_NBSTOP_1BIT, - dbgu_base + AT91_DBGU_MR); - - writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR); -} - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h deleted file mode 100644 index 7d70fe4cb4..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h +++ /dev/null @@ -1,373 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause */ -/* - * Copyright (c) 2006, Atmel Corporation - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - */ -#ifndef __AT91_DDRSDRC_H__ -#define __AT91_DDRSDRC_H__ - -/**** Register offset in AT91S_HDDRSDRC2 structure ***/ -#define AT91_HDDRSDRC2_MR 0x00 /* Mode Register */ -#define AT91_HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */ -#define AT91_HDDRSDRC2_CR 0x08 /* Configuration Register */ -#define AT91_HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */ -#define AT91_HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */ -#define AT91_HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */ -#define AT91_HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */ -#define AT91_HDDRSDRC2_LPR 0x1C /* Low-power Register */ -#define AT91_HDDRSDRC2_MDR 0x20 /* Memory Device Register */ -#define AT91_HDDRSDRC2_DLL 0x24 /* DLL Information Register */ -#define AT91_HDDRSDRC2_HS 0x2C /* High Speed Register */ - -/* below items defined for sama5d3x */ -#define AT91_MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */ -#define AT91_MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */ -#define AT91_MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */ -#define AT91_MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */ -#define AT91_MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */ -#define AT91_MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */ -#define AT91_MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */ -#define AT91_MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */ -/* 0x54 ~ 0x70 Reserved */ -#define AT91_MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */ -#define AT91_MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */ -#define AT91_MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */ -#define AT91_MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */ -#define AT91_MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */ - -#define AT91_MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */ - -/* 0x94 ~ 0xE0 Reserved */ -#define AT91_HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */ -#define AT91_HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */ - -/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/ -#define AT91_DDRC2_MODE (0x7UL << 0) -#define AT91_DDRC2_MODE_NORMAL_CMD (0x0UL) -#define AT91_DDRC2_MODE_NOP_CMD (0x1UL) -#define AT91_DDRC2_MODE_PRCGALL_CMD (0x2UL) -#define AT91_DDRC2_MODE_LMR_CMD (0x3UL) -#define AT91_DDRC2_MODE_RFSH_CMD (0x4UL) -#define AT91_DDRC2_MODE_EXT_LMR_CMD (0x5UL) -#define AT91_DDRC2_MODE_DEEP_CMD (0x6UL) -#define AT91_DDRC2_MODE_LPDDR2_CMD (0x7UL) -#define AT91_DDRC2_MRS(value) (value << 8) - -/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */ -#define AT91_DDRC2_COUNT (0xFFFUL << 0) -#define AT91_DDRC2_ADJ_REF (0x1UL << 16) -#define AT91_DDRC2_DISABLE_ADJ_REF (0x0UL << 16) -#define AT91_DDRC2_ENABLE_ADJ_REF (0x1UL << 16) - -/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/ -#define AT91_DDRC2_NC (0x3UL << 0) -#define AT91_DDRC2_NC_DDR9_SDR8 (0x0UL) -#define AT91_DDRC2_NC_DDR10_SDR9 (0x1UL) -#define AT91_DDRC2_NC_DDR11_SDR10 (0x2UL) -#define AT91_DDRC2_NC_DDR12_SDR11 (0x3UL) -#define AT91_DDRC2_NR (0x3UL << 2) -#define AT91_DDRC2_NR_11 (0x0UL << 2) -#define AT91_DDRC2_NR_12 (0x1UL << 2) -#define AT91_DDRC2_NR_13 (0x2UL << 2) -#define AT91_DDRC2_NR_14 (0x3UL << 2) -#define AT91_DDRC2_CAS (0x7UL << 4) -#define AT91_DDRC2_CAS_2 (0x2UL << 4) -#define AT91_DDRC2_CAS_3 (0x3UL << 4) -#define AT91_DDRC2_CAS_4 (0x4UL << 4) -#define AT91_DDRC2_CAS_5 (0x5UL << 4) -#define AT91_DDRC2_CAS_6 (0x6UL << 4) -#define AT91_DDRC2_RESET_DLL (0x1UL << 7) -#define AT91_DDRC2_DISABLE_RESET_DLL (0x0UL << 7) -#define AT91_DDRC2_ENABLE_RESET_DLL (0x1UL << 7) -#define AT91_DDRC2_DIC_DS (0x1UL << 8) -#define AT91_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8) -#define AT91_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8) -#define AT91_DDRC2_DLL (0x1UL << 9) -#define AT91_DDRC2_ENABLE_DLL (0x0UL << 9) -#define AT91_DDRC2_DISABLE_DLL (0x1UL << 9) -#define AT91_DDRC2_ZQ (0x03 << 10) -#define AT91_DDRC2_ZQ_INIT (0x0 << 10) -#define AT91_DDRC2_ZQ_LONG (0x1 << 10) -#define AT91_DDRC2_ZQ_SHORT (0x2 << 10) -#define AT91_DDRC2_ZQ_RESET (0x3 << 10) -#define AT91_DDRC2_OCD (0x7UL << 12) -#define AT91_DDRC2_OCD_EXIT (0x0UL << 12) -#define AT91_DDRC2_OCD_DEFAULT (0x7UL << 12) -#define AT91_DDRC2_EBISHARE (0x1UL << 16) -#define AT91_DDRC2_DQMS (0x1UL << 16) -#define AT91_DDRC2_DQMS_NOT_SHARED (0x0UL << 16) -#define AT91_DDRC2_DQMS_SHARED (0x1UL << 16) -#define AT91_DDRC2_ENRDM (0x1UL << 17) -#define AT91_DDRC2_ENRDM_DISABLE (0x0UL << 17) -#define AT91_DDRC2_ENRDM_ENABLE (0x1UL << 17) -#define AT91_DDRC2_ACTBST (0x1UL << 18) -#define AT91_DDRC2_NB_BANKS (0x1UL << 20) -#define AT91_DDRC2_NB_BANKS_4 (0x0UL << 20) -#define AT91_DDRC2_NB_BANKS_8 (0x1UL << 20) -#define AT91_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */ -#define AT91_DDRC2_NDQS_ENABLED (0x0UL << 21) -#define AT91_DDRC2_NDQS_DISABLED (0x1UL << 21) -#define AT91_DDRC2_DECOD (0x1UL << 22) -#define AT91_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22) -#define AT91_DDRC2_DECOD_INTERLEAVED (0x1UL << 22) -#define AT91_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */ -#define AT91_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23) -#define AT91_DDRC2_UNAL_SUPPORTED (0x1UL << 23) - -/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/ -#define AT91_DDRC2_TRAS (0xFUL << 0) -#define AT91_DDRC2_TRAS_(x) (x & 0x0f) -#define AT91_DDRC2_TRCD (0xFUL << 4) -#define AT91_DDRC2_TRCD_(x) ((x & 0x0f) << 4) -#define AT91_DDRC2_TWR (0xFUL << 8) -#define AT91_DDRC2_TWR_(x) ((x & 0x0f) << 8) -#define AT91_DDRC2_TRC (0xFUL << 12) -#define AT91_DDRC2_TRC_(x) ((x & 0x0f) << 12) -#define AT91_DDRC2_TRP (0xFUL << 16) -#define AT91_DDRC2_TRP_(x) ((x & 0x0f) << 16) -#define AT91_DDRC2_TRRD (0xFUL << 20) -#define AT91_DDRC2_TRRD_(x) ((x & 0x0f) << 20) -#define AT91_DDRC2_TWTR (0xFUL << 24) -#define AT91_DDRC2_TWTR_(x) ((x & 0x0f) << 24) -#define AT91_DDRC2_TMRD (0xFUL << 28) -#define AT91_DDRC2_TMRD_(x) ((x & 0x0f) << 28) - -/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */ -#define AT91_DDRC2_TRFC (0x7FUL << 0) -#define AT91_DDRC2_TRFC_(x) (x & 0x7f) -#define AT91_DDRC2_TXSNR (0xFFUL << 8) -#define AT91_DDRC2_TXSNR_(x) ((x & 0xff) << 8) -#define AT91_DDRC2_TXSRD (0xFFUL << 16) -#define AT91_DDRC2_TXSRD_(x) ((x & 0xff) << 16) -#define AT91_DDRC2_TXP (0xFUL << 24) -#define AT91_DDRC2_TXP_(x) ((x & 0x0f) << 24) - -/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/ -#define AT91_DDRC2_TXARD (0xFUL << 0) -#define AT91_DDRC2_TXARD_(x) (x & 0x0f) -#define AT91_DDRC2_TXARDS (0xFUL << 4) -#define AT91_DDRC2_TXARDS_(x) ((x & 0x0f) << 4) -#define AT91_DDRC2_TRPA (0xFUL << 8) -#define AT91_DDRC2_TRPA_(x) ((x & 0x0f) << 8) -#define AT91_DDRC2_TRT (0xFUL << 12) -#define AT91_DDRC2_TRTP_(x) ((x & 0x0f) << 12) -#define AT91_DDRC2_TFA (0xFUL << 16) -#define AT91_DDRC2_TFAW_(x) ((x & 0x0f) << 16) - -/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/ -#define AT91_DDRC2_LPCB (0x3UL << 0) -#define AT91_DDRC2_LPCB_DISABLED (0x0UL) -#define AT91_DDRC2_LPCB_SELFREFRESH (0x1UL) -#define AT91_DDRC2_LPCB_POWERDOWN (0x2UL) -#define AT91_DDRC2_LPCB_DEEP_PWD (0x3UL) -#define AT91_DDRC2_CLK_FR (0x1UL << 2) -#define AT91_DDRC2_PASR (0x7UL << 4) -#define AT91_DDRC2_PASR_(x) ((x & 0x7) << 4) -#define AT91_DDRC2_DS (0x7UL << 8) -#define AT91_DDRC2_DS_(x) ((x & 0x7) << 8) -#define AT91_DDRC2_TIMEOUT (0x3UL << 12) -#define AT91_DDRC2_TIMEOUT_0 (0x0UL << 12) -#define AT91_DDRC2_TIMEOUT_64 (0x1UL << 12) -#define AT91_DDRC2_TIMEOUT_128 (0x2UL << 12) -#define AT91_DDRC2_TIMEOUT_Reserved (0x3UL << 12) -#define AT91_DDRC2_ADPE (0x1UL << 16) -#define AT91_DDRC2_ADPE_FAST (0x0UL << 16) -#define AT91_DDRC2_ADPE_SLOW (0x1UL << 16) -#define AT91_DDRC2_UPD_MR (0x3UL << 20) -#define AT91_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20) -#define AT91_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20) -#define AT91_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20) -#define AT91_DDRC2_SELF_DONE (0x1UL << 25) - -/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */ -#define AT91_DDRC2_MD (0x7UL << 0) -#define AT91_DDRC2_MD_SDR_SDRAM (0x0UL) -#define AT91_DDRC2_MD_LP_SDR_SDRAM (0x1UL) -#define AT91_DDRC2_MD_DDR_SDRAM (0x2UL) -#define AT91_DDRC2_MD_LP_DDR_SDRAM (0x3UL) -#define AT91_DDRC2_MD_DDR3_SDRAM (0x4UL) -#define AT91_DDRC2_MD_LPDDR3_SDRAM (0x5UL) -#define AT91_DDRC2_MD_DDR2_SDRAM (0x6UL) -#define AT91_DDRC2_MD_LPDDR2_SDRAM (0x7UL) -#define AT91_DDRC2_DBW (0x1UL << 4) -#define AT91_DDRC2_DBW_32_BITS (0x0UL << 4) -#define AT91_DDRC2_DBW_16_BITS (0x1UL << 4) - -/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/ -#define AT91_DDRC2_MDINC (0x1UL << 0) -#define AT91_DDRC2_MDDEC (0x1UL << 1) -#define AT91_DDRC2_MDOVF (0x1UL << 2) -#define AT91_DDRC2_MDVAL (0xFFUL << 8) - -/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */ -#define AT91_LPDDRC2_BK_MASK_PASR(value) (value << 0) -#define AT91_LPDDRC2_SEG_MASK(value) (value << 8) -#define AT91_LPDDRC2_DS(value) (value << 24) - -/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/ -#define AT91_DDRC2_NO_ANT (0x1UL << 2) - -/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/ -#define AT91_DDRC2_COUNT_CAL_MASK (0xFFFFUL) -#define AT91_DDRC2_COUNT_CAL(value) (((value) & AT91_DDRC2_COUNT_CAL_MASK) << 0) -#define AT91_DDRC2_MR4R(value) (((value) & 0xFFFFUL) << 16) - -/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */ -#define AT91_DDRC2_ZQCS(value) (value << 0) - -/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/ -#define AT91_MPDDRC_RDIV (0x7UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0) - -#define AT91_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0) -#define AT91_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0) -#define AT91_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0) -#define AT91_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0) - -#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0) -#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0) - -#define AT91_MPDDRC_ENABLE_CALIB (0x01 << 4) -#define AT91_MPDDRC_DISABLE_CALIB (0x00 << 4) -#define AT91_MPDDRC_EN_CALIB (0x01 << 4) - -#define AT91_MPDDRC_TZQIO (0x7FUL << 8) -#define AT91_MPDDRC_TZQIO_(x) ((x) << 8) -#define AT91_MPDDRC_TZQIO_0 (0x0UL << 8) -#define AT91_MPDDRC_TZQIO_1 (0x1UL << 8) -#define AT91_MPDDRC_TZQIO_3 (0x3UL << 8) -#define AT91_MPDDRC_TZQIO_4 (0x4UL << 8) -#define AT91_MPDDRC_TZQIO_5 (0x5UL << 8) -#define AT91_MPDDRC_TZQIO_31 (0x1FUL << 8) - -#define AT91_MPDDRC_CALCODEP (0xFUL << 16) -#define AT91_MPDDRC_CALCODEP_(x) ((x) << 16) - -#define AT91_MPDDRC_CALCODEN (0xFUL << 20) -#define AT91_MPDDRC_CALCODEN_(x) ((x) << 20) - -/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */ -#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0) -#define AT91_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0) -#define AT91_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0) -#define AT91_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0) -#define AT91_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0) - -/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/ -#define AT91_MPDDRC_MOFF(value) (value << 0) -#define AT91_MPDDRC_MOFF_1 (0x1UL << 0) -#define AT91_MPDDRC_MOFF_7 (0x7UL << 0) -#define AT91_MPDDRC_CLK90OFF(value) (value << 8) -#define AT91_MPDDRC_CLK90OFF_1 (0x1UL << 8) -#define AT91_MPDDRC_CLK90OFF_31 (0x1FUL << 8) -#define AT91_MPDDRC_SELOFF (0x1UL << 16) -#define AT91_MPDDRC_SELOFF_DISABLED (0x0UL << 16) -#define AT91_MPDDRC_SELOFF_ENABLED (0x1UL << 16) -#define AT91_MPDDRC_KEY (0xC5UL << 24) - -/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/ -#define AT91_MPDDRC_S0OFF_1 (0x1UL << 0) -#define AT91_MPDDRC_S1OFF_1 (0x1UL << 8) -#define AT91_MPDDRC_S2OFF_1 (0x1UL << 16) -#define AT91_MPDDRC_S3OFF_1 (0x1UL << 24) - -#define AT91_MPDDRC_S0OFF(value) (value << 0) -#define AT91_MPDDRC_S1OFF(value) (value << 8) -#define AT91_MPDDRC_S2OFF(value) (value << 16) -#define AT91_MPDDRC_S3OFF(value) (value << 24) - -/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/ -#define AT91_DDRC2_WPEN (0x1UL << 0) -#define AT91_DDRC2_WPKEY (0xFFFFFFUL << 8) - -/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/ -#define AT91_DDRC2_WPVS (0x1UL << 0) -#define AT91_DDRC2_WPSRC (0xFFFFUL << 8) - -#ifndef __ASSEMBLY__ -#include <common.h> -#include <io.h> -#include <mach/hardware.h> - -static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb) -{ - u32 cr; - u32 mdr; - u32 size; - bool is_sdram; - - cr = readl(base + AT91_HDDRSDRC2_CR); - mdr = readl(base + AT91_HDDRSDRC2_MDR); - - /* will always be false for sama5d2, sama5d3 or sama5d4 */ - is_sdram = (mdr & AT91_DDRC2_MD) <= AT91_DDRC2_MD_LP_SDR_SDRAM; - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91_DDRC2_NC) + 8; - if (!is_sdram) - size ++; - /* ROW */ - size += ((cr & AT91_DDRC2_NR) >> 2) + 11; - /* BANK */ - if (is_nb) - size = ((cr & AT91_DDRC2_NB_BANKS) ? 8 : 4) << size; - else - size = 4 << size; - - /* bandwidth */ - if (!(mdr & AT91_DDRC2_DBW)) - size <<= 1; - - return size; -} - -static inline u32 at91sam9g45_get_ddram_size(int bank) -{ - switch (bank) { - case 0: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); - case 1: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); - default: - return 0; - } -} - -static inline u32 at91sam9x5_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); -} - -static inline u32 at91sam9n12_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); -} - -static inline u32 at91sama5d3_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true); -} - -static inline u32 at91sama5d4_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true); -} - - -#endif /* __ASSEMBLY__ */ - -#endif /* #ifndef __AT91_DDRSDRC_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h deleted file mode 100644 index 61cff83c73..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ -/* SPDX-FileCopyrightText: 2015 Atmel */ -/* SPDX-FileCopyrightText: 2015 Ludovic Desroches <ludovic.desroches@atmel.com> */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - -#include <linux/bitops.h> - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */ -#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */ -#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */ -#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */ -#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ -#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */ -#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */ -#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ -#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */ -#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */ -#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */ -#define PIO_ESR 0xc0 /* Edge Select Register */ -#define PIO_LSR 0xc4 /* Level Select Register */ -#define PIO_ELSR 0xc8 /* Edge/Level Status Register */ -#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */ -#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */ -#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */ -#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */ - -#define ABCDSR_PERIPH_A 0x0 -#define ABCDSR_PERIPH_B 0x1 -#define ABCDSR_PERIPH_C 0x2 -#define ABCDSR_PERIPH_D 0x3 - -#define PIO4_MSKR 0x0000 /* Mask Register */ -#define PIO4_CFGR 0x0004 /* Configuration Register */ -#define PIO4_CFGR_FUNC_MASK GENMASK(2, 0) -#define PIO4_DIR_MASK BIT(8) -#define PIO4_PUEN_MASK BIT(9) -#define PIO4_PDEN_MASK BIT(10) -#define PIO4_IFEN_MASK BIT(12) -#define PIO4_IFSCEN_MASK BIT(13) -#define PIO4_OPD_MASK BIT(14) -#define PIO4_SCHMITT_MASK BIT(15) -#define PIO4_DRVSTR_MASK GENMASK(17, 16) -#define PIO4_DRVSTR_OFFSET 16 -#define PIO4_CFGR_EVTSEL_MASK GENMASK(26, 24) -#define PIO4_CFGR_EVTSEL_FALLING (0 << 24) -#define PIO4_CFGR_EVTSEL_RISING (1 << 24) -#define PIO4_CFGR_EVTSEL_BOTH (2 << 24) -#define PIO4_CFGR_EVTSEL_LOW (3 << 24) -#define PIO4_CFGR_EVTSEL_HIGH (4 << 24) -#define PIO4_PDSR 0x0008 /* Data Status Register */ -#define PIO4_LOCKSR 0x000C /* Lock Status Register */ -#define PIO4_SODR 0x0010 /* Set Output Data Register */ -#define PIO4_CODR 0x0014 /* Clear Output Data Register */ -#define PIO4_ODSR 0x0018 /* Output Data Status Register */ -#define PIO4_IER 0x0020 /* Interrupt Enable Register */ -#define PIO4_IDR 0x0024 /* Interrupt Disable Register */ -#define PIO4_IMR 0x0028 /* Interrupt Mask Register */ -#define PIO4_ISR 0x002C /* Interrupt Status Register */ -#define PIO4_IOFR 0x003C /* I/O Freeze Configuration Register */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h deleted file mode 100644 index 4cdeeb4871..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pit.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Andrew Victor */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -#define AT91_PIT_MR 0x00 /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR 0x04 /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h deleted file mode 100644 index 2860ea4854..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ -#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ - -#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_UPLLCOUNT_DEFAULT (0x1UL << 20) -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ - -#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ -#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_PMC_OSCOUNT_(x) ((x) << 8) -#define AT91_PMC_KEY_MASK (0xff << 16) /* MOR Writing Key */ -#define AT91_PMC_KEY (0x37 << 16) -#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ - -#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Frequency Measure Ready */ -#define AT91_PMC_RCMEAS (1 << 20) /* RC Oscillator Frequency Measure (write-only) */ -#define AT91_PMC_CCSS (1 << 24) /* Counter Clock Source Selection */ -#define AT91_PMC_CCSS_RC_OSC (0 << 24) /* MAINF counter clock is the RC oscillator. */ -#define AT91_PMC_CCSS_XTAL_OSC (1 << 24) /* MAINF counter clock is the crystal oscillator. */ -#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ -#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_OUT_0 (0 << 14) -#define AT91_PMC_OUT_1 (1 << 14) -#define AT91_PMC_OUT_2 (2 << 14) -#define AT91_PMC_OUT_3 (3 << 14) -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL) -#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/ -#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL) -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define PMC_PRES_OFFSET 2 -#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) -#define PMC_ALT_PRES_OFFSET 4 -#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ -#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_H32MXDIV (1 << 24) /* AHB 32-bit Matrix Divisor [some SAMA5 only] */ - -#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ - -#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ -#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ -#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ -#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) - -#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ -#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) - -#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ -#define AT91_PMC_MOSCXTS (1 << 0) /* Oscillator Startup Time */ -#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ -#define AT91_PMC_SR 0x68 /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ -#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ -#define AT91_PMC_GCKRDY (1 << 24) -#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ -#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ -#define AT91_PMC_ICPPLLA (0xf << 0) -#define AT91_PMC_ICPPLLA_0 (0 << 0) -#define AT91_PMC_ICPPLLA_1 (1 << 0) -#define AT91_PMC_REALLOCK (0x1 << 7) -#define AT91_PMC_IPLLA (0xf << 8) -#define AT91_PMC_IPLLA_0 (0 << 8) -#define AT91_PMC_IPLLA_1 (1 << 8) -#define AT91_PMC_IPLLA_2 (2 << 8) -#define AT91_PMC_IPLLA_3 (3 << 8) - - -#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ -#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ -#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ -#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ - -#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ -#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ -#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ - -#define AT91_PMC_VER 0xfc /* PMC Module Version [AT91CAP9 only] */ - -#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ -#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ -#define AT91_PMC_GCKCSS (0x7 << 8) -#define AT91_PMC_GCKCSS_SLOW_CLK (0x0 << 8) -#define AT91_PMC_GCKCSS_MAIN_CLK (0x1 << 8) -#define AT91_PMC_GCKCSS_PLLA_CLK (0x2 << 8) -#define AT91_PMC_GCKCSS_UPLL_CLK (0x3 << 8) -#define AT91_PMC_GCKCSS_MCK_CLK (0x4 << 8) -#define AT91_PMC_GCKCSS_AUDIO_CLK (0x5 << 8) -#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ -#define AT91_PMC_PCR_DIV_MASK (0x3 << 16) -#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ -#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ -#define AT91_PMC_GCKDIV (0xff << 20) -#define AT91_PMC_GCKDIV_MSK 0xff -#define AT91_PMC_GCKDIV_OFFSET 20 -#define AT91_PMC_GCKDIV_(x) (((x) & AT91_PMC_GCKDIV_MSK) << AT91_PMC_GCKDIV_OFFSET) -#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ -#define AT91_PMC_GCK_EN (0x1 << 29) - -#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 */ -#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Disable Register 1 */ -#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Status Register 1 */ -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h deleted file mode 100644 index 85896a01d5..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Copyright (c) 2006, Atmel Corporation - */ - -#ifndef AT91_PMC_LL_H -#define AT91_PMC_LL_H - -#include <errno.h> -#include <asm/io.h> -#include <mach/at91_pmc.h> - -#define AT91_PMC_LL_FLAG_SAM9X5_PMC (1 << 0) -#define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1) -#define AT91_PMC_LL_FLAG_DISABLE_RC (1 << 2) -#define AT91_PMC_LL_FLAG_H32MXDIV (1 << 3) -#define AT91_PMC_LL_FLAG_PMC_UTMI (1 << 4) -#define AT91_PMC_LL_FLAG_GCSR (1 << 5) -#define AT91_PMC_LL_FLAG_MCK_BYPASS (1 << 6) - -#define AT91_PMC_LL_AT91RM9200 (0) -#define AT91_PMC_LL_AT91SAM9260 (0) -#define AT91_PMC_LL_AT91SAM9261 (0) -#define AT91_PMC_LL_AT91SAM9263 (0) -#define AT91_PMC_LL_AT91SAM9G45 (AT91_PMC_LL_FLAG_PMC_UTMI) -#define AT91_PMC_LL_AT91SAM9X5 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC | \ - AT91_PMC_LL_FLAG_PMC_UTMI) -#define AT91_PMC_LL_AT91SAM9N12 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) -#define AT91_PMC_LL_SAMA5D2 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_MEASURE_XTAL | \ - AT91_PMC_LL_FLAG_PMC_UTMI) -/* This assumes a crystal on both XIN and XOUT. If your board - * instead has an extenal oscillator on XIN only, - * AT91_PMC_LL_FLAG_MCK_BYPASS needs to be OR`ed in as well - */ -#define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC | \ - AT91_PMC_LL_FLAG_PMC_UTMI) -#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_H32MXDIV | \ - AT91_PMC_LL_FLAG_PMC_UTMI) - -void at91_pmc_init(void __iomem *pmc_base, unsigned int flags); -void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags); -void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags); - -int at91_pmc_enable_generic_clock(void __iomem *pmc_base, void __iomem *sfr_base, - unsigned int periph_id, - unsigned int clk_source, unsigned int div, - unsigned int flags); - -static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr) -{ - writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR); -} - -static inline void at91_pmc_enable_system_clock(void __iomem *pmc_base, - unsigned clock_id) -{ - writel(clock_id, pmc_base + AT91_PMC_SCER); -} - -static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base, - unsigned periph_id) -{ - u32 mask = 0x01 << (periph_id % 32); - - if ((periph_id / 32) == 1) - writel(mask, pmc_base + AT91_PMC_PCER1); - else if ((periph_id / 32) == 0) - writel(mask, pmc_base + AT91_PMC_PCER); - else - return -EINVAL; - - return 0; -} - -static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base, - unsigned periph_id) -{ - u32 pcr = periph_id; - - if (periph_id >= 0x80) /* 7 bits only */ - return -EINVAL; - - writel(pcr, pmc_base + AT91_PMC_PCR); - pcr |= readl(pmc_base + AT91_PMC_PCR) & AT91_PMC_PCR_DIV_MASK; - pcr |= AT91_PMC_PCR_CMD | AT91_PMC_PCR_EN; - writel(pcr, pmc_base + AT91_PMC_PCR); - - return 0; -} - -static inline bool at91_pmc_check_mck_h32mxdiv(void __iomem *pmc_base, - unsigned flags) -{ - if (flags & AT91_PMC_LL_FLAG_H32MXDIV) - return readl(pmc_base + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV; - - return false; -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h deleted file mode 100644 index 1dc665b877..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Andrew Victor */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_RSTC_CR (0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_RSTC_SR (0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h deleted file mode 100644 index b4197665dd..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_rtt.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Andrew Victor */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * arch/arm/mach-at91/include/mach/at91_rtt.h - * - * Real-time Timer (RTT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#include <io.h> - -#define AT91_RTT_MR 0x00 /* Real-time Mode Register */ -#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ -#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ -#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ -#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ - -#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ -#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ - -#define AT91_RTT_VR 0x08 /* Real-time Value Register */ -#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ - -#define AT91_RTT_SR 0x0c /* Real-time Status Register */ -#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ -#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ - - -/* - * As the RTT is powered by the backup power so if the interrupt - * is still on when the kernel start, the kernel will end up with - * dead lock interrupt that it can not clear. Because the interrupt line is - * shared with the basic timer (PIT) on AT91_ID_SYS. - */ -static inline void at91_rtt_irq_fixup(void *base) -{ - void __iomem *reg = base + AT91_RTT_MR; - u32 mr = readl(reg); - - writel(mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN), reg); -} -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h deleted file mode 100644 index 04924742a5..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR 0x08 /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#ifndef __ASSEMBLY__ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Copyright (c) 2006, Atmel Corporation - */ - -#include <asm/io.h> - -static inline void at91_wdt_disable(void __iomem *wdt_base) -{ - u32 reg = readl(wdt_base + AT91_WDT_MR); - reg |= AT91_WDT_WDDIS; - writel(reg, wdt_base + AT91_WDT_MR); -} - -#endif /* __ASSEMBLY__ */ -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h deleted file mode 100644 index 4d6c8939ef..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91rm9200.h] - * - * Common definitions. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91RM9200_ID_US0 6 /* USART 0 */ -#define AT91RM9200_ID_US1 7 /* USART 1 */ -#define AT91RM9200_ID_US2 8 /* USART 2 */ -#define AT91RM9200_ID_US3 9 /* USART 3 */ -#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91RM9200_ID_UDP 11 /* USB Device Port */ -#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ -#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ -#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ -#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ -#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ -#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ -#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ -#define AT91RM9200_ID_UHP 23 /* USB Host port */ -#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ -#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ - - -/* - * Peripheral physical base addresses. - */ -#define AT91RM9200_BASE_TCB0 0xfffa0000 -#define AT91RM9200_BASE_TC0 0xfffa0000 -#define AT91RM9200_BASE_TC1 0xfffa0040 -#define AT91RM9200_BASE_TC2 0xfffa0080 -#define AT91RM9200_BASE_TCB1 0xfffa4000 -#define AT91RM9200_BASE_TC3 0xfffa4000 -#define AT91RM9200_BASE_TC4 0xfffa4040 -#define AT91RM9200_BASE_TC5 0xfffa4080 -#define AT91RM9200_BASE_UDP 0xfffb0000 -#define AT91RM9200_BASE_MCI 0xfffb4000 -#define AT91RM9200_BASE_TWI 0xfffb8000 -#define AT91RM9200_BASE_EMAC 0xfffbc000 -#define AT91RM9200_BASE_US0 0xfffc0000 -#define AT91RM9200_BASE_US1 0xfffc4000 -#define AT91RM9200_BASE_US2 0xfffc8000 -#define AT91RM9200_BASE_US3 0xfffcc000 -#define AT91RM9200_BASE_SSC0 0xfffd0000 -#define AT91RM9200_BASE_SSC1 0xfffd4000 -#define AT91RM9200_BASE_SSC2 0xfffd8000 -#define AT91RM9200_BASE_SPI 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ -#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ -#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ -#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ -#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ -#define AT91RM9200_BASE_PMC 0xfffffc00 -#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ -#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ -#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ - -/* - * Internal Memory. - */ -#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - -#define AT91_VA_BASE_EMAC AT91RM9200_BASE_EMAC - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h deleted file mode 100644 index 5de0349433..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * [origin: arch/arm/mach-at91/include/mach/at91rm9200_emac.h] - * - * Ethernet MAC registers. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91RM9200_EMAC_H -#define AT91RM9200_EMAC_H - -#define AT91_EMAC_CTL 0x00 /* Control Register */ -#define AT91_EMAC_LB (1 << 0) /* Loopback */ -#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ -#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ -#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ -#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ -#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ -#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ -#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ -#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ - -#define AT91_EMAC_CFG 0x04 /* Configuration Register */ -#define AT91_EMAC_SPD (1 << 0) /* Speed */ -#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ -#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ -#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ -#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ -#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ -#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ -#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ -#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ -#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ -#define AT91_EMAC_CLK_DIV8 (0 << 10) -#define AT91_EMAC_CLK_DIV16 (1 << 10) -#define AT91_EMAC_CLK_DIV32 (2 << 10) -#define AT91_EMAC_CLK_DIV64 (3 << 10) -#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ -#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ - -#define AT91_EMAC_SR 0x08 /* Status Register */ -#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ -#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ -#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ - -#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ - -#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ -#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ -#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ - -#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ -#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ -#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ -#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ -#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ -#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ -#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ - -#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ - -#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ -#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ -#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ -#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ - -#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ -#define AT91_EMAC_DONE (1 << 0) /* Management Done */ -#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ -#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ -#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ -#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ -#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ -#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ -#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ -#define AT91_EMAC_LINK (1 << 9) /* Link */ -#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ -#define AT91_EMAC_ABT (1 << 11) /* Abort */ - -#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ -#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ -#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ - -#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ -#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ -#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ -#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ -#define AT91_EMAC_RW_W (1 << 28) -#define AT91_EMAC_RW_R (2 << 28) -#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ - -/* - * Statistics Registers. - */ -#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ -#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ -#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ -#define AT91_EMAC_OK 0x4c /* Frames Received OK */ -#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ -#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ -#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ -#define AT91_EMAC_LCOL 0x5c /* Late Collision */ -#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ -#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ -#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ -#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ -#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ -#define AT91_EMAC_CDE 0x74 /* Code Error */ -#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ -#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ -#define AT91_EMAC_USF 0x80 /* Undersize Frame */ -#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ - -/* - * Address Registers. - */ -#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ -#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ -#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ -#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ -#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ -#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ -#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ -#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ -#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ -#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h deleted file mode 100644 index 41ee1caba7..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * arch/arm/mach-at91/include/mach/at91rm9200_mc.h - * - * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91RM9200_MC_H -#define AT91RM9200_MC_H - -/* Memory Controller */ -#define AT91RM9200_MC_RCR (0x00) /* MC Remap Control Register */ -#define AT91RM9200_MC_RCB (1 << 0) /* Remap Command Bit */ - -#define AT91RM9200_MC_ASR (0x04) /* MC Abort Status Register */ -#define AT91RM9200_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ -#define AT91RM9200_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ -#define AT91RM9200_MC_ABTSZ (3 << 8) /* Abort Size Status */ -#define AT91RM9200_MC_ABTSZ_BYTE (0 << 8) -#define AT91RM9200_MC_ABTSZ_HALFWORD (1 << 8) -#define AT91RM9200_MC_ABTSZ_WORD (2 << 8) -#define AT91RM9200_MC_ABTTYP (3 << 10) /* Abort Type Status */ -#define AT91RM9200_MC_ABTTYP_DATAREAD (0 << 10) -#define AT91RM9200_MC_ABTTYP_DATAWRITE (1 << 10) -#define AT91RM9200_MC_ABTTYP_FETCH (2 << 10) -#define AT91RM9200_MC_MST0 (1 << 16) /* ARM920T Abort Source */ -#define AT91RM9200_MC_MST1 (1 << 17) /* PDC Abort Source */ -#define AT91RM9200_MC_MST2 (1 << 18) /* UHP Abort Source */ -#define AT91RM9200_MC_MST3 (1 << 19) /* EMAC Abort Source */ -#define AT91RM9200_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ -#define AT91RM9200_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ -#define AT91RM9200_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ -#define AT91RM9200_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ - -#define AT91RM9200_MC_AASR (0x08) /* MC Abort Address Status Register */ - -#define AT91RM9200_MC_MPR (0x0c) /* MC Master Priority Register */ -#define AT91RM9200_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ -#define AT91RM9200_MPR_MSTP1 (7 << 4) /* PDC Priority */ -#define AT91RM9200_MPR_MSTP2 (7 << 8) /* UHP Priority */ -#define AT91RM9200_MPR_MSTP3 (7 << 12) /* EMAC Priority */ - -/* External Bus Interface (EBI) registers */ -#define AT91RM9200_EBI_CSA (0x60) /* Chip Select Assignment Register */ -#define AT91RM9200_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ -#define AT91RM9200_EBI_CS0A_SMC (0 << 0) -#define AT91RM9200_EBI_CS0A_BFC (1 << 0) -#define AT91RM9200_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91RM9200_EBI_CS1A_SMC (0 << 1) -#define AT91RM9200_EBI_CS1A_SDRAMC (1 << 1) -#define AT91RM9200_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ -#define AT91RM9200_EBI_CS3A_SMC (0 << 3) -#define AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91RM9200_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ -#define AT91RM9200_EBI_CS4A_SMC (0 << 4) -#define AT91RM9200_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) -#define AT91RM9200_EBI_CFGR (0x64) /* Configuration Register */ -#define AT91RM9200_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ - -/* Static Memory Controller (SMC) registers */ -#define AT91RM9200_SMC_CSR(n) (0x70 + ((n) * 4))/* SMC Chip Select Register */ -#define AT91RM9200_SMC_NWS (0x7f << 0) /* Number of Wait States */ -#define AT91RM9200_SMC_NWS_(x) ((x) << 0) -#define AT91RM9200_SMC_WSEN (1 << 7) /* Wait State Enable */ -#define AT91RM9200_SMC_TDF (0xf << 8) /* Data Float Time */ -#define AT91RM9200_SMC_TDF_(x) ((x) << 8) -#define AT91RM9200_SMC_BAT (1 << 12) /* Byte Access Type */ -#define AT91RM9200_SMC_DBW (3 << 13) /* Data Bus Width */ -#define AT91RM9200_SMC_DBW_16 (1 << 13) -#define AT91RM9200_SMC_DBW_8 (2 << 13) -#define AT91RM9200_SMC_DPR (1 << 15) /* Data Read Protocol */ -#define AT91RM9200_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ -#define AT91RM9200_SMC_ACSS_STD (0 << 16) -#define AT91RM9200_SMC_ACSS_1 (1 << 16) -#define AT91RM9200_SMC_ACSS_2 (2 << 16) -#define AT91RM9200_SMC_ACSS_3 (3 << 16) -#define AT91RM9200_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ -#define AT91RM9200_SMC_RWSETUP_(x) ((x) << 24) -#define AT91RM9200_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ -#define AT91RM9200_SMC_RWHOLD_(x) ((x) << 28) - -/* SDRAM Controller registers */ -#define AT91RM9200_SDRAMC_MR (0x90) /* Mode Register */ -#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0) -#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0) -#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0) -#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0) -#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0) -#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */ -#define AT91RM9200_SDRAMC_DBW_32 (0 << 4) -#define AT91RM9200_SDRAMC_DBW_16 (1 << 4) - -#define AT91RM9200_SDRAMC_TR (0x94) /* Refresh Timer Register */ -#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ - -#define AT91RM9200_SDRAMC_CR (0x98) /* Configuration Register */ -#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91RM9200_SDRAMC_NC_8 (0 << 0) -#define AT91RM9200_SDRAMC_NC_9 (1 << 0) -#define AT91RM9200_SDRAMC_NC_10 (2 << 0) -#define AT91RM9200_SDRAMC_NC_11 (3 << 0) -#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91RM9200_SDRAMC_NR_11 (0 << 2) -#define AT91RM9200_SDRAMC_NR_12 (1 << 2) -#define AT91RM9200_SDRAMC_NR_13 (2 << 2) -#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91RM9200_SDRAMC_NB_2 (0 << 4) -#define AT91RM9200_SDRAMC_NB_4 (1 << 4) -#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91RM9200_SDRAMC_CAS_2 (2 << 5) -#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ -#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ -#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ -#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ -#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ -#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ - -#define AT91RM9200_SDRAMC_SRR (0x9c) /* Self Refresh Register */ -#define AT91RM9200_SDRAMC_LPR (0xa0) /* Low Power Register */ -#define AT91RM9200_SDRAMC_IER (0xa4) /* Interrupt Enable Register */ -#define AT91RM9200_SDRAMC_IDR (0xa8) /* Interrupt Disable Register */ -#define AT91RM9200_SDRAMC_IMR (0xac) /* Interrupt Mask Register */ -#define AT91RM9200_SDRAMC_ISR (0xb0) /* Interrupt Status Register */ - -/* Burst Flash Controller register */ -#define AT91RM9200_BFC_MR (0xc0) /* Mode Register */ -#define AT91RM9200_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ -#define AT91RM9200_BFC_BFCOM_DISABLED (0 << 0) -#define AT91RM9200_BFC_BFCOM_ASYNC (1 << 0) -#define AT91RM9200_BFC_BFCOM_BURST (2 << 0) -#define AT91RM9200_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ -#define AT91RM9200_BFC_BFCC_MCK (1 << 2) -#define AT91RM9200_BFC_BFCC_DIV2 (2 << 2) -#define AT91RM9200_BFC_BFCC_DIV4 (3 << 2) -#define AT91RM9200_BFC_AVL (0xf << 4) /* Address Valid Latency */ -#define AT91RM9200_BFC_PAGES (7 << 8) /* Page Size */ -#define AT91RM9200_BFC_PAGES_NO_PAGE (0 << 8) -#define AT91RM9200_BFC_PAGES_16 (1 << 8) -#define AT91RM9200_BFC_PAGES_32 (2 << 8) -#define AT91RM9200_BFC_PAGES_64 (3 << 8) -#define AT91RM9200_BFC_PAGES_128 (4 << 8) -#define AT91RM9200_BFC_PAGES_256 (5 << 8) -#define AT91RM9200_BFC_PAGES_512 (6 << 8) -#define AT91RM9200_BFC_PAGES_1024 (7 << 8) -#define AT91RM9200_BFC_OEL (3 << 12) /* Output Enable Latency */ -#define AT91RM9200_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ -#define AT91RM9200_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ -#define AT91RM9200_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ -#define AT91RM9200_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ - -#ifndef __ASSEMBLY__ -#include <io.h> -#include <mach/at91rm9200.h> -static inline u32 at91rm9200_get_sdram_size(void) -{ - u32 cr, mr; - u32 size; - - cr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_CR); - mr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_MR); - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91RM9200_SDRAMC_NC) + 8; - /* ROW */ - size += ((cr & AT91RM9200_SDRAMC_NR) >> 2) + 11; - /* BANK */ - size = ((cr & AT91RM9200_SDRAMC_NB) ? 4 : 2) << size; - /* bandwidth */ - if (!(mr & AT91RM9200_SDRAMC_DBW)) - size <<= 1; - - return size; -} -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_st.h b/arch/arm/mach-at91/include/mach/at91rm9200_st.h deleted file mode 100644 index 67bcfaa13b..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_st.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * arch/arm/mach-at91/include/mach/at91_st.h - * - * System Timer (ST) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - */ - -#ifndef AT91RM9200_ST_H -#define AT91RM9200_ST_H - -#define AT91RM9200_ST_CR (0x00) /* Control Register */ -#define AT91RM9200_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ - -#define AT91RM9200_ST_PIMR (0x04) /* Period Interval Mode Register */ -#define AT91RM9200_ST_PIV (0xffff << 0) /* Period Interval Value */ - -#define AT91RM9200_ST_WDMR (0x08) /* Watchdog Mode Register */ -#define AT91RM9200_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ -#define AT91RM9200_ST_RSTEN (1 << 16) /* Reset Enable */ -#define AT91RM9200_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ - -#define AT91RM9200_ST_RTMR (0x0c) /* Real-time Mode Register */ -#define AT91RM9200_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ - -#define AT91RM9200_ST_SR (0x10) /* Status Register */ -#define AT91RM9200_ST_PITS (1 << 0) /* Period Interval Timer Status */ -#define AT91RM9200_ST_WDOVF (1 << 1) /* Watchdog Overflow */ -#define AT91RM9200_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ -#define AT91RM9200_ST_ALMS (1 << 3) /* Alarm Status */ - -#define AT91RM9200_ST_IER (0x14) /* Interrupt Enable Register */ -#define AT91RM9200_ST_IDR (0x18) /* Interrupt Disable Register */ -#define AT91RM9200_ST_IMR (0x1c) /* Interrupt Mask Register */ - -#define AT91RM9200_ST_RTAR (0x20) /* Real-time Alarm Register */ -#define AT91RM9200_ST_ALMV (0xfffff << 0) /* Alarm Value */ - -#define AT91RM9200_ST_CRTR (0x24) /* Current Real-time Register */ -#define AT91RM9200_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h deleted file mode 100644 index 1375872ce2..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2006 Andrew Victor */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91SAM9260_BASE_ECC 0xffffe800 -#define AT91SAM9260_BASE_SDRAMC 0xffffea00 -#define AT91SAM9260_BASE_SMC 0xffffec00 -#define AT91SAM9260_BASE_MATRIX 0xffffee00 -#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9260_BASE_PIOA 0xfffff400 -#define AT91SAM9260_BASE_PIOB 0xfffff600 -#define AT91SAM9260_BASE_PIOC 0xfffff800 -#define AT91SAM9260_BASE_RSTC 0xfffffd00 -#define AT91SAM9260_BASE_SHDWC 0xfffffd10 -#define AT91SAM9260_BASE_RTT 0xfffffd20 -#define AT91SAM9260_BASE_PIT 0xfffffd30 -#define AT91SAM9260_BASE_WDT 0xfffffd40 -#define AT91SAM9260_BASE_GPBR 0xfffffd50 - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ -#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */ -#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ -#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */ -#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h deleted file mode 100644 index fb5e76bb51..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91SAM9260_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9260_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9260_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9260_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9260_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9260_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9260_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9260_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9260_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9260_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9260_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9260_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91SAM9260_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9260_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9260_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9260_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9260_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9260_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9260_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91SAM9260_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91SAM9260_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91SAM9260_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91SAM9260_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9260_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9260_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9260_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9260_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9260_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9260_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9260_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9260_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9260_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9260_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91SAM9260_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9260_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9260_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91SAM9260_MATRIX_EBICSA (0x11C) /* EBI Chip Select Assignment Register */ -#define AT91SAM9260_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9260_MATRIX_CS1A_SMC (0 << 1) -#define AT91SAM9260_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91SAM9260_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9260_MATRIX_CS3A_SMC (0 << 3) -#define AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9260_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9260_MATRIX_CS4A_SMC (0 << 4) -#define AT91SAM9260_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9260_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9260_MATRIX_CS5A_SMC (0 << 5) -#define AT91SAM9260_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9260_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9260_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9260_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9260_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h deleted file mode 100644 index fa42907473..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: SAN People */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 - - -/* - * System Peripherals - */ -#define AT91SAM9261_BASE_SMC 0xffffec00 -#define AT91SAM9261_BASE_MATRIX 0xffffee00 -#define AT91SAM9261_BASE_SDRAMC 0xffffea00 -#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9261_BASE_PIOA 0xfffff400 -#define AT91SAM9261_BASE_PIOB 0xfffff600 -#define AT91SAM9261_BASE_PIOC 0xfffff800 -#define AT91SAM9261_BASE_RSTC 0xfffffd00 -#define AT91SAM9261_BASE_SHDWC 0xfffffd10 -#define AT91SAM9261_BASE_RTT 0xfffffd20 -#define AT91SAM9261_BASE_PIT 0xfffffd30 -#define AT91SAM9261_BASE_WDT 0xfffffd40 -#define AT91SAM9261_BASE_GPBR 0xfffffd50 - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ -#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h deleted file mode 100644 index dda9cef945..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#define AT91SAM9261_MATRIX_MCFG (0x00) /* Master Configuration Register */ -#define AT91SAM9261_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9261_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91SAM9261_MATRIX_SCFG0 (0x04) /* Slave Configuration Register 0 */ -#define AT91SAM9261_MATRIX_SCFG1 (0x08) /* Slave Configuration Register 1 */ -#define AT91SAM9261_MATRIX_SCFG2 (0x0C) /* Slave Configuration Register 2 */ -#define AT91SAM9261_MATRIX_SCFG3 (0x10) /* Slave Configuration Register 3 */ -#define AT91SAM9261_MATRIX_SCFG4 (0x14) /* Slave Configuration Register 4 */ -#define AT91SAM9261_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9261_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9261_MATRIX_TCR (0x24) /* TCM Configuration Register */ -#define AT91SAM9261_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9261_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9261_MATRIX_ITCM_16 (5 << 0) -#define AT91SAM9261_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9261_MATRIX_ITCM_64 (7 << 0) -#define AT91SAM9261_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9261_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9261_MATRIX_DTCM_16 (5 << 4) -#define AT91SAM9261_MATRIX_DTCM_32 (6 << 4) -#define AT91SAM9261_MATRIX_DTCM_64 (7 << 4) - -#define AT91SAM9261_MATRIX_EBICSA (0x30) /* EBI Chip Select Assignment Register */ -#define AT91SAM9261_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9261_MATRIX_CS1A_SMC (0 << 1) -#define AT91SAM9261_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91SAM9261_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9261_MATRIX_CS3A_SMC (0 << 3) -#define AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9261_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9261_MATRIX_CS4A_SMC (0 << 4) -#define AT91SAM9261_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9261_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9261_MATRIX_CS5A_SMC (0 << 5) -#define AT91SAM9261_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9261_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ - -#define AT91SAM9261_MATRIX_USBPUCR (0x34) /* USB Pad Pull-Up Control Register */ -#define AT91SAM9261_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h deleted file mode 100644 index 2ea9aadafa..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 - - -/* - * System Peripherals - */ -#define AT91SAM9263_BASE_ECC0 0xffffe000 -#define AT91SAM9263_BASE_SDRAMC0 0xffffe200 -#define AT91SAM9263_BASE_SMC0 0xffffe400 -#define AT91SAM9263_BASE_ECC1 0xffffe600 -#define AT91SAM9263_BASE_SDRAMC1 0xffffe800 -#define AT91SAM9263_BASE_SMC1 0xffffea00 -#define AT91SAM9263_BASE_MATRIX 0xffffec00 -#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9263_BASE_PIOA 0xfffff200 -#define AT91SAM9263_BASE_PIOB 0xfffff400 -#define AT91SAM9263_BASE_PIOC 0xfffff600 -#define AT91SAM9263_BASE_PIOD 0xfffff800 -#define AT91SAM9263_BASE_PIOE 0xfffffa00 -#define AT91SAM9263_BASE_RSTC 0xfffffd00 -#define AT91SAM9263_BASE_SHDWC 0xfffffd10 -#define AT91SAM9263_BASE_RTT0 0xfffffd20 -#define AT91SAM9263_BASE_PIT 0xfffffd30 -#define AT91SAM9263_BASE_WDT 0xfffffd40 -#define AT91SAM9263_BASE_RTT1 0xfffffd50 -#define AT91SAM9263_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h deleted file mode 100644 index 2f10ce096e..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2006 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#define AT91SAM9263_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9263_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9263_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9263_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9263_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9263_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9263_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9263_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9263_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9263_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9263_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9263_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9263_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9263_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91SAM9263_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9263_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9263_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9263_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9263_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9263_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9263_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9263_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9263_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9263_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9263_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9263_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9263_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9263_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ - -#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9263_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9263_MATRIX_RCB2 (1 << 2) -#define AT91SAM9263_MATRIX_RCB3 (1 << 3) -#define AT91SAM9263_MATRIX_RCB4 (1 << 4) -#define AT91SAM9263_MATRIX_RCB5 (1 << 5) -#define AT91SAM9263_MATRIX_RCB6 (1 << 6) -#define AT91SAM9263_MATRIX_RCB7 (1 << 7) -#define AT91SAM9263_MATRIX_RCB8 (1 << 8) - -#define AT91SAM9263_MATRIX_TCMR (0x114) /* TCM Configuration Register */ -#define AT91SAM9263_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9263_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9263_MATRIX_ITCM_16 (5 << 0) -#define AT91SAM9263_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9263_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9263_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9263_MATRIX_DTCM_16 (5 << 4) -#define AT91SAM9263_MATRIX_DTCM_32 (6 << 4) - -#define AT91SAM9263_MATRIX_EBI0CSA (0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91SAM9263_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91SAM9263_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9263_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9263_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9263_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) - -#define AT91SAM9263_MATRIX_EBI1CSA (0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91SAM9263_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9263_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91SAM9263_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91SAM9263_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9263_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h deleted file mode 100644 index 8ef83010d2..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam926x.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_AT91SAM926X_H -#define __MACH_AT91SAM926X_H - -#define AT91SAM926X_BASE_PMC 0xfffffc00 -#define AT91SAM926X_BASE_RSTC 0xfffffd00 -#define AT91SAM926X_BASE_WDT 0xfffffd40 - -#endif /* __MACH_AT91SAM926X_H */ diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h deleted file mode 100644 index 3dab64b71a..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h +++ /dev/null @@ -1,204 +0,0 @@ -#ifndef __AT91SAM926X_BOARD_INIT_H__ -#define __AT91SAM926X_BOARD_INIT_H__ -/* - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#include <common.h> -#include <init.h> - -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9_smc.h> -#include <mach/at91_rstc.h> -#include <mach/at91_pio.h> -#include <mach/at91_pmc.h> -#include <mach/at91_wdt.h> -#include <mach/hardware.h> -#include <mach/gpio.h> -#include <mach/at91sam926x.h> - -struct at91sam926x_board_cfg { - /* SoC specific */ - void __iomem *pio; - void __iomem *sdramc; - u32 ebi_pio_is_peripha; - void __iomem *matrix_csa; - - /* board specific */ - u32 wdt_mr; - u32 ebi_pio_pdr; - u32 ebi_pio_ppudr; - u32 ebi_csa; - u32 smc_cs; - u32 smc_mode; - u32 smc_cycle; - u32 smc_pulse; - u32 smc_setup; - u32 pmc_mor; - u32 pmc_pllar; - u32 pmc_mckr1; - u32 pmc_mckr2; - u32 sdrc_cr; - u32 sdrc_tr1; - u32 sdrc_mdr; - u32 sdrc_tr2; - u32 rstc_rmr; -}; - - -static void __always_inline access_sdram(void) -{ - writel(0x00000000, AT91_CHIPSELECT_1); -} - -static void __always_inline pmc_check_mckrdy(void) -{ - u32 r; - - do { - r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR); - } while (!(r & AT91_PMC_MCKRDY)); -} - -static int __always_inline running_in_sram(void) -{ - u32 addr = get_pc(); - - addr >>= 28; - return addr == 0; -} - -static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg *cfg) -{ - u32 r; - int i; - int in_sram = running_in_sram(); - - /* SDRAMC Check if Refresh Timer Counter is already initialized */ - r = readl(cfg->sdramc + AT91_SDRAMC_TR); - if (r && !in_sram) - return; - - /* SDRAMC_MR : Normal Mode */ - writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); - - /* SDRAMC_TR - Refresh Timer register */ - writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR); - - /* SDRAMC_CR - Configuration register*/ - writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR); - - /* Memory Device Type */ - writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR); - - /* SDRAMC_MR : Precharge All */ - writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_MR : refresh */ - writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR); - - /* access SDRAM 8 times */ - for (i = 0; i < 8; i++) - access_sdram(); - - /* SDRAMC_MR : Load Mode Register */ - writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_MR : Normal Mode */ - writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_TR : Refresh Timer Counter */ - writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR); - access_sdram(); -} - -static void __always_inline at91sam926x_board_init(void __iomem *smcbase, - struct at91sam926x_board_cfg *cfg) -{ - u32 r; - void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC); - - if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT)) - return; - - writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR); - - /* configure PIOx as EBI0 D[16-31] */ - at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr); - at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true); - if (cfg->ebi_pio_is_peripha) - at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr); - - writel(cfg->ebi_csa, cfg->matrix_csa); - - /* flash */ - writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE); - writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE); - writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE); - writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP); - - /* PMC Check if the PLL is already initialized */ - r = readl(pmc + AT91_PMC_MCKR); - if ((r & AT91_PMC_CSS) && !running_in_sram()) - return; - - /* Enable the Main Oscillator */ - writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR); - do { - r = readl(pmc + AT91_PMC_SR); - } while (!(r & AT91_PMC_MOSCS)); - - /* PLLAR: x MHz for PCK */ - writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR); - do { - r = readl(pmc + AT91_PMC_SR); - } while (!(r & AT91_PMC_LOCKA)); - - /* PCK/x = MCK Master Clock from SLOW */ - writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR); - pmc_check_mckrdy(); - - /* PCK/x = MCK Master Clock from PLLA */ - writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR); - pmc_check_mckrdy(); - - /* Init SDRAM */ - at91sam926x_sdramc_init(cfg); - - /* User reset enable*/ - writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR); - - /* - * When boot from external boot - * we need to enable mck and ohter clock - * so enable all of them - * We will shutdown what we don't need later - */ - writel(0xffffffff, pmc + AT91_PMC_PCER); -} - -#include <mach/at91sam9260.h> -static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg); -} - -#include <mach/at91sam9261.h> -static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg); -} - -#include <mach/at91sam9263.h> -static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg); -} - -#endif /* __AT91SAM926X_BOARD_INIT_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h deleted file mode 100644 index 80effe2148..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ -/* SPDX-FileCopyrightText: 2007 Andrew Victor */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * SDRAM Controllers (SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91SAM9_SDRAMC_H -#define AT91SAM9_SDRAMC_H - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - -#ifndef __ASSEMBLY__ -#include <io.h> -static inline u32 at91_get_sdram_size(void *base) -{ - u32 val; - u32 size; - - val = readl(base + AT91_SDRAMC_CR); - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (val & AT91_SDRAMC_NC) + 8; - /* ROW */ - size += ((val & AT91_SDRAMC_NR) >> 2) + 11; - /* BANK */ - size = ((val & AT91_SDRAMC_NB) ? 4 : 2) << size; - /* bandwidth */ - if (!(val & AT91_SDRAMC_DBW)) - size <<= 1; - - return size; -} - - -static inline bool at91_is_low_power_sdram(void *base) -{ - return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM; -} - -#ifdef CONFIG_SOC_AT91SAM9260 -#include <mach/at91sam9260.h> -static inline u32 at91sam9260_get_sdram_size(void) -{ - return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)); -} - -static inline bool at91sam9260_is_low_power_sdram(void) -{ - return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC)); -} -#else -static inline u32 at91sam9260_get_sdram_size(void) -{ - return 0; -} - -static inline bool at91sam9260_is_low_power_sdram(void) -{ - return false; -} -#endif - -#ifdef CONFIG_SOC_AT91SAM9261 -#include <mach/at91sam9261.h> -static inline u32 at91sam9261_get_sdram_size(void) -{ - return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC)); -} - -static inline bool at91sam9261_is_low_power_sdram(void) -{ - return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC)); -} -#else -static inline u32 at91sam9261_get_sdram_size(void) -{ - return 0; -} - -static inline bool at91sam9261_is_low_power_sdram(void) -{ - return false; -} -#endif - -#ifdef CONFIG_SOC_AT91SAM9263 -#include <mach/at91sam9263.h> -static inline u32 at91sam9263_get_sdram_size(int bank) -{ - switch (bank) { - case 0: - return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0)); - case 1: - return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC1)); - default: - return 0; - } -} - -static inline bool at91sam9263_is_low_power_sdram(int bank) -{ - switch (bank) { - case 0: - return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC0)); - case 1: - return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC1)); - default: - return false; - } -} -#else -static inline u32 at91sam9263_get_sdram_size(int bank) -{ - return 0; -} - -static inline bool at91sam9263_is_low_power_sdram(void) -{ - return false; -} -#endif - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h deleted file mode 100644 index d23ea52bce..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2007 Andrew Victor */ -/* SPDX-FileCopyrightText: 2007 Atmel Corporation */ - -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - */ - -#ifndef AT91SAM9_SMC_H -#define AT91SAM9_SMC_H - -#ifndef __ASSEMBLY__ -struct sam9_smc_config { - /* Setup register */ - u8 ncs_read_setup; - u8 nrd_setup; - u8 ncs_write_setup; - u8 nwe_setup; - - /* Pulse register */ - u8 ncs_read_pulse; - u8 nrd_pulse; - u8 ncs_write_pulse; - u8 nwe_pulse; - - /* Cycle register */ - u16 read_cycle; - u16 write_cycle; - - /* Mode register */ - u32 mode; - u8 tdf_cycles:4; - - /* Timings register */ - u8 tclr; - u8 tadl; - u8 tar; - u8 ocms; - u8 trr; - u8 twb; - u8 rbnsel; - u8 nfsel; -}; - -extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); - -extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config); -#endif - -#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SAMA5_SMC_TIMINGS 0x0c /* Timings register for CS n */ -#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */ -#define AT91_SMC_TCLR_(x) ((x) << 0) -#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */ -#define AT91_SMC_TADL_(x) ((x) << 4) -#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */ -#define AT91_SMC_TAR_(x) ((x) << 8) -#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */ -#define AT91_SMC_OCMS_(x) ((x) << 12) -#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */ -#define AT91_SMC_TRR_(x) ((x) << 16) -#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */ -#define AT91_SMC_TWB_(x) ((x) << 24) -#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */ -#define AT91_SMC_RBNSEL_(x) ((x) << 28) -#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */ -#define AT91_SMC_NFSEL_(x) ((x) << 31) - -#define AT91_SAM9_SMC_MODE 0xc -#define AT91_SAMA5_SMC_MODE 0x10 -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h deleted file mode 100644 index d7596930d2..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2008-2009 Atmel Corporation */ - -/* - * Chip-specific header file for the AT91SAM9G45 family - * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TCB0 0xfff7c000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TCB1 0xfffd4000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 - -/* - * System Peripherals - */ -#define AT91SAM9G45_BASE_ECC 0xffffe200 -#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 -#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 -#define AT91SAM9G45_BASE_DMA 0xffffec00 -#define AT91SAM9G45_BASE_SMC 0xffffe800 -#define AT91SAM9G45_BASE_MATRIX 0xffffea00 -#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9G45_BASE_PIOA 0xfffff200 -#define AT91SAM9G45_BASE_PIOB 0xfffff400 -#define AT91SAM9G45_BASE_PIOC 0xfffff600 -#define AT91SAM9G45_BASE_PIOD 0xfffff800 -#define AT91SAM9G45_BASE_PIOE 0xfffffa00 -#define AT91SAM9G45_BASE_RSTC 0xfffffd00 -#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 -#define AT91SAM9G45_BASE_RTT 0xfffffd20 -#define AT91SAM9G45_BASE_PIT 0xfffffd30 -#define AT91SAM9G45_BASE_WDT 0xfffffd40 -#define AT91SAM9G45_BASE_RTC 0xfffffdb0 -#define AT91SAM9G45_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h deleted file mode 100644 index 239e11df3d..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2008-2009 Atmel Corporation */ - -/* - * Matrix-centric header file for the AT91SAM9G45 family - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9G45 preliminary datasheet. - */ - -#ifndef AT91SAM9G45_MATRIX_H -#define AT91SAM9G45_MATRIX_H - -#define AT91SAM9G45_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9G45_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9G45_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9G45_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9G45_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9G45_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9G45_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9G45_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9G45_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9G45_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */ -#define AT91SAM9G45_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */ -#define AT91SAM9G45_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */ -#define AT91SAM9G45_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9G45_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9G45_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9G45_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9G45_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9G45_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9G45_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9G45_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9G45_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9G45_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9G45_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9G45_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9G45_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9G45_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9G45_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9G45_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9G45_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9G45_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9G45_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9G45_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9G45_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9G45_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9G45_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9G45_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9G45_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9G45_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9G45_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9G45_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9G45_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9G45_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9G45_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9G45_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9G45_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9G45_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9G45_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9G45_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9G45_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9G45_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9G45_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9G45_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9G45_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91SAM9G45_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9G45_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9G45_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9G45_MATRIX_RCB2 (1 << 2) -#define AT91SAM9G45_MATRIX_RCB3 (1 << 3) -#define AT91SAM9G45_MATRIX_RCB4 (1 << 4) -#define AT91SAM9G45_MATRIX_RCB5 (1 << 5) -#define AT91SAM9G45_MATRIX_RCB6 (1 << 6) -#define AT91SAM9G45_MATRIX_RCB7 (1 << 7) -#define AT91SAM9G45_MATRIX_RCB8 (1 << 8) -#define AT91SAM9G45_MATRIX_RCB9 (1 << 9) -#define AT91SAM9G45_MATRIX_RCB10 (1 << 10) -#define AT91SAM9G45_MATRIX_RCB11 (1 << 11) - -#define AT91SAM9G45_MATRIX_TCMR (0x110) /* TCM Configuration Register */ -#define AT91SAM9G45_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9G45_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9G45_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9G45_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9G45_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9G45_MATRIX_DTCM_32 (6 << 4) -#define AT91SAM9G45_MATRIX_DTCM_64 (7 << 4) -#define AT91SAM9G45_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91SAM9G45_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91SAM9G45_MATRIX_TCM_ONE_WS (0x1 << 11) - -#define AT91SAM9G45_MATRIX_VIDEO (0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) - -#define AT91SAM9G45_MATRIX_EBICSA (0x128) /* EBI Chip Select Assignment Register */ -#define AT91SAM9G45_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9G45_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9G45_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9G45_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91SAM9G45_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91SAM9G45_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9G45_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9G45_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) - -#define AT91SAM9G45_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9G45_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9G45_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9G45_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9G45_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9G45_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9G45_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9G45_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9G45_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9G45_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h deleted file mode 100644 index b68a529b05..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2011 Atmel Corporation */ - -/* - * Chip-specific header file for the AT91SAM9N12 SoC - * - * Common definitions. - * Based on AT91SAM9N12 preliminary datasheet - */ - -#ifndef __MACH_AT91SAM9N12_H_ -#define __MACH_AT91SAM9N12_H_ - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -/* Reserved 4 */ -#define AT91SAM9N12_ID_USART0 5 /* USART 0 */ -#define AT91SAM9N12_ID_USART1 6 /* USART 1 */ -#define AT91SAM9N12_ID_USART2 7 /* USART 2 */ -#define AT91SAM9N12_ID_USART3 8 /* USART 3 */ -#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ -/* Reserved 11 */ -#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9N12_ID_UART0 15 /* UART 0 */ -#define AT91SAM9N12_ID_UART1 16 /* UART 1 */ -#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9N12_ID_DMA 20 /* DMA Controller 0 */ -/* Reserved 21 */ -#define AT91SAM9N12_ID_UHPFS 22 /* USB Host Full Speed */ -#define AT91SAM9N12_ID_UDPFS 23 /* USB Device Full Speed */ -/* Reserved 24 */ -#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ -/* Reserved 26 */ -/* Reserved 27 */ -#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ -/* Reserved 29 */ -#define AT91SAM9N12_ID_TRNG 30 /* True Random Number Generator */ -#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9N12_BASE_SPI0 0xf0000000 -#define AT91SAM9N12_BASE_SPI1 0xf0004000 -#define AT91SAM9N12_BASE_MCI 0xf0008000 -#define AT91SAM9N12_BASE_SSC 0xf0010000 -#define AT91SAM9N12_BASE_TCB0 0xf8008000 -#define AT91SAM9N12_BASE_TC0 0xf8008000 -#define AT91SAM9N12_BASE_TC1 0xf8008040 -#define AT91SAM9N12_BASE_TC2 0xf8008080 -#define AT91SAM9N12_BASE_TCB1 0xf800c000 -#define AT91SAM9N12_BASE_TC3 0xf800c000 -#define AT91SAM9N12_BASE_TC4 0xf800c040 -#define AT91SAM9N12_BASE_TC5 0xf800c080 -#define AT91SAM9N12_BASE_TWI0 0xf8010000 -#define AT91SAM9N12_BASE_TWI1 0xf8014000 -#define AT91SAM9N12_BASE_USART0 0xf801c000 -#define AT91SAM9N12_BASE_USART1 0xf8020000 -#define AT91SAM9N12_BASE_USART2 0xf8024000 -#define AT91SAM9N12_BASE_USART3 0xf8028000 -#define AT91SAM9N12_BASE_PWMC 0xf8034000 -#define AT91SAM9N12_BASE_LCDC 0xf8038000 -#define AT91SAM9N12_BASE_UDPFS 0xf803c000 -#define AT91SAM9N12_BASE_UART0 0xf8040000 -#define AT91SAM9N12_BASE_UART1 0xf8044000 -#define AT91SAM9N12_BASE_TRNG 0xf8048000 -#define AT91SAM9N12_BASE_ADC 0xf804c000 - -/* - * System Peripherals - */ -#define AT91SAM9N12_BASE_FUSE 0xffffdc00 -#define AT91SAM9N12_BASE_MATRIX 0xffffde00 -#define AT91SAM9N12_BASE_PMECC 0xffffe000 -#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600 -#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800 -#define AT91SAM9N12_BASE_SMC 0xffffea00 -#define AT91SAM9N12_BASE_DMA 0xffffec00 -#define AT91SAM9N12_BASE_AIC 0xfffff000 -#define AT91SAM9N12_BASE_DBGU 0xfffff200 -#define AT91SAM9N12_BASE_PIOA 0xfffff400 -#define AT91SAM9N12_BASE_PIOB 0xfffff600 -#define AT91SAM9N12_BASE_PIOC 0xfffff800 -#define AT91SAM9N12_BASE_PIOD 0xfffffa00 -#define AT91SAM9N12_BASE_PMC 0xfffffc00 -#define AT91SAM9N12_BASE_RSTC 0xfffffe00 -#define AT91SAM9N12_BASE_SHDWC 0xfffffe10 -#define AT91SAM9N12_BASE_PIT 0xfffffe30 -#define AT91SAM9N12_BASE_WDT 0xfffffe40 -#define AT91SAM9N12_BASE_GPBR 0xfffffe60 -#define AT91SAM9N12_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9N12_ROM_SIZE SZ_1M /* Internal ROM size (1Mb) */ - -#define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */ -#define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h deleted file mode 100644 index 43f255808f..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2011 Atmel Corporation */ - -/* - * Matrix-Centric header file for the AT91SAM9N12 SoC - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9N12 preliminary datasheet. - */ - -#ifndef _AT91SAM9N12_MATRIX_H_ -#define _AT91SAM9N12_MATRIX_H_ - -#define AT91SAM9N12_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9N12_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9N12_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9N12_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9N12_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9N12_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9N12_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9N12_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9N12_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9N12_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9N12_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9N12_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9N12_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9N12_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9N12_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9N12_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9N12_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9N12_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9N12_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9N12_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9N12_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9N12_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9N12_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9N12_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9N12_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9N12_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9N12_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9N12_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9N12_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9N12_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91SAM9N12_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9N12_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9N12_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9N12_MATRIX_RCB2 (1 << 2) -#define AT91SAM9N12_MATRIX_RCB3 (1 << 3) -#define AT91SAM9N12_MATRIX_RCB4 (1 << 4) -#define AT91SAM9N12_MATRIX_RCB5 (1 << 5) - -#define AT91SAM9N12_MATRIX_EBICSA (0x118) /* EBI Chip Select Assignment Register */ -#define AT91SAM9N12_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9N12_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9N12_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9N12_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91SAM9N12_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9N12_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9N12_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9N12_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */ -#define AT91SAM9N12_MATRIX_EBI_DBPD_ON (0 << 9) -#define AT91SAM9N12_MATRIX_EBI_DBPD_OFF (1 << 9) -#define AT91SAM9N12_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */ -#define AT91SAM9N12_MATRIX_EBI_LOW_DRIVE (0 << 17) -#define AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE (1 << 17) -#define AT91SAM9N12_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91SAM9N12_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91SAM9N12_MATRIX_NFD0_ON_D16 (1 << 24) - -#define AT91SAM9N12_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9N12_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9N12_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9N12_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9N12_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9N12_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9N12_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9N12_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9N12_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9N12_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h deleted file mode 100644 index 00bef3456a..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2009-2010 Atmel Corporation */ - -/* - * Chip-specific header file for the AT91SAM9x5 family - * - * Common definitions. - * Based on AT91SAM9x5 preliminary datasheet. - */ - -#ifndef AT91SAM9X5_H -#define AT91SAM9X5_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ -#define AT91SAM9X5_ID_USART0 5 /* USART 0 */ -#define AT91SAM9X5_ID_USART1 6 /* USART 1 */ -#define AT91SAM9X5_ID_USART2 7 /* USART 2 */ -#define AT91SAM9X5_ID_USART3 8 /* USART 3 */ -#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ -#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9X5_ID_UART0 15 /* UART 0 */ -#define AT91SAM9X5_ID_UART1 16 /* UART 1 */ -#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ -#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ -#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ -#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ -#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ -#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ -#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ -#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9X5_BASE_SPI0 0xf0000000 -#define AT91SAM9X5_BASE_SPI1 0xf0004000 -#define AT91SAM9X5_BASE_MCI0 0xf0008000 -#define AT91SAM9X5_BASE_MCI1 0xf000c000 -#define AT91SAM9X5_BASE_SSC 0xf0010000 -#define AT91SAM9X5_BASE_CAN0 0xf8000000 -#define AT91SAM9X5_BASE_CAN1 0xf8004000 -#define AT91SAM9X5_BASE_TCB0 0xf8008000 -#define AT91SAM9X5_BASE_TC0 0xf8008000 -#define AT91SAM9X5_BASE_TC1 0xf8008040 -#define AT91SAM9X5_BASE_TC2 0xf8008080 -#define AT91SAM9X5_BASE_TCB1 0xf800c000 -#define AT91SAM9X5_BASE_TC3 0xf800c000 -#define AT91SAM9X5_BASE_TC4 0xf800c040 -#define AT91SAM9X5_BASE_TC5 0xf800c080 -#define AT91SAM9X5_BASE_TWI0 0xf8010000 -#define AT91SAM9X5_BASE_TWI1 0xf8014000 -#define AT91SAM9X5_BASE_TWI2 0xf8018000 -#define AT91SAM9X5_BASE_USART0 0xf801c000 -#define AT91SAM9X5_BASE_USART1 0xf8020000 -#define AT91SAM9X5_BASE_USART2 0xf8024000 -#define AT91SAM9X5_BASE_USART3 0xf8028000 -#define AT91SAM9X5_BASE_EMAC0 0xf802c000 -#define AT91SAM9X5_BASE_EMAC1 0xf8030000 -#define AT91SAM9X5_BASE_PWMC 0xf8034000 -#define AT91SAM9X5_BASE_LCDC 0xf8038000 -#define AT91SAM9X5_BASE_UDPHS 0xf803c000 -#define AT91SAM9X5_BASE_UART0 0xf8040000 -#define AT91SAM9X5_BASE_UART1 0xf8044000 -#define AT91SAM9X5_BASE_ISI 0xf8048000 -#define AT91SAM9X5_BASE_ADC 0xf804c000 - -/* - * System Peripherals - */ -#define AT91SAM9X5_BASE_MATRIX 0xffffde00 -#define AT91SAM9X5_BASE_PMECC 0xffffe000 -#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600 -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 -#define AT91SAM9X5_BASE_SMC 0xffffea00 -#define AT91SAM9X5_BASE_DMA0 0xffffec00 -#define AT91SAM9X5_BASE_DMA1 0xffffee00 -#define AT91SAM9X5_BASE_AIC 0xfffff000 -#define AT91SAM9X5_BASE_DBGU 0xfffff200 -#define AT91SAM9X5_BASE_PIOA 0xfffff400 -#define AT91SAM9X5_BASE_PIOB 0xfffff600 -#define AT91SAM9X5_BASE_PIOC 0xfffff800 -#define AT91SAM9X5_BASE_PIOD 0xfffffa00 -#define AT91SAM9X5_BASE_PMC 0xfffffc00 -#define AT91SAM9X5_BASE_RSTC 0xfffffe00 -#define AT91SAM9X5_BASE_SHDWC 0xfffffe10 -#define AT91SAM9X5_BASE_PIT 0xfffffe30 -#define AT91SAM9X5_BASE_WDT 0xfffffe40 -#define AT91SAM9X5_BASE_GPBR 0xfffffe60 -#define AT91SAM9X5_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9X5_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9X5_SMD_BASE 0x00400000 /* SMD Controller */ -#define AT91SAM9X5_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ -#define AT91SAM9X5_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ -#define AT91SAM9X5_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h deleted file mode 100644 index 2ab211c012..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2009-2010 Atmel Corporation */ - -/* - * Matrix-centric header file for the AT91SAM9x5 family - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9x5 preliminary datasheet. - */ - -#ifndef AT91SAM9X5_MATRIX_H -#define AT91SAM9X5_MATRIX_H - -#define AT91SAM9X5_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9X5_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9X5_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9X5_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9X5_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9X5_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9X5_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9X5_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9X5_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9X5_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */ -#define AT91SAM9X5_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */ -#define AT91SAM9X5_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */ -#define AT91SAM9X5_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9X5_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9X5_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9X5_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9X5_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9X5_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9X5_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9X5_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9X5_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9X5_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9X5_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9X5_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9X5_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9X5_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9X5_MATRIX_SCFG8 (0x60) /* Slave Configuration Register 8 */ -#define AT91SAM9X5_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9X5_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9X5_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9X5_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9X5_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9X5_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9X5_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9X5_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9X5_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9X5_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9X5_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9X5_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9X5_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9X5_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9X5_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9X5_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9X5_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9X5_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9X5_MATRIX_PRAS8 (0xC0) /* Priority Register A for Slave 8 */ -#define AT91SAM9X5_MATRIX_PRBS8 (0xC4) /* Priority Register B for Slave 8 */ -#define AT91SAM9X5_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9X5_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9X5_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9X5_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9X5_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9X5_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9X5_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9X5_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9X5_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91SAM9X5_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9X5_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9X5_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9X5_MATRIX_RCB2 (1 << 2) -#define AT91SAM9X5_MATRIX_RCB3 (1 << 3) -#define AT91SAM9X5_MATRIX_RCB4 (1 << 4) -#define AT91SAM9X5_MATRIX_RCB5 (1 << 5) -#define AT91SAM9X5_MATRIX_RCB6 (1 << 6) -#define AT91SAM9X5_MATRIX_RCB7 (1 << 7) -#define AT91SAM9X5_MATRIX_RCB8 (1 << 8) -#define AT91SAM9X5_MATRIX_RCB9 (1 << 9) -#define AT91SAM9X5_MATRIX_RCB10 (1 << 10) -#define AT91SAM9X5_MATRIX_RCB11 (1 << 11) - -#define AT91SAM9X5_MATRIX_EBICSA (0x120) /* EBI Chip Select Assignment Register */ -#define AT91SAM9X5_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9X5_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9X5_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9X5_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91SAM9X5_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9X5_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9X5_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) -#define AT91SAM9X5_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91SAM9X5_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91SAM9X5_MATRIX_NFD0_ON_D16 (1 << 24) -#define AT91SAM9X5_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ -#define AT91SAM9X5_MATRIX_MP_OFF (0 << 25) -#define AT91SAM9X5_MATRIX_MP_ON (1 << 25) - -#define AT91SAM9X5_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9X5_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9X5_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9X5_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9X5_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9X5_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9X5_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9X5_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9X5_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9X5_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h deleted file mode 100644 index a44160431e..0000000000 --- a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h +++ /dev/null @@ -1,748 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2010 Atmel Corporation */ - -/* - * Header file for AT91 High end LCD Controller - * - * Data structure and register user interface - */ - -#ifndef __MACH_ATMEL_HLCD_H__ -#define __MACH_ATMEL_HLCD_H__ - -/* Lcdc hardware registers */ -#define ATMEL_LCDC_LCDCFG0 0x0000 -#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) -#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) -#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) -#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) -#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) -#define LCDC_LCDCFG0_CGDISOVR2 (0x1 << 10) -#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) -#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) -#define LCDC_LCDCFG0_CGDISPP (0x1 << 13) -#define LCDC_LCDCFG0_CLKDIV_OFFSET 16 -#define LCDC_LCDCFG0_CLKDIV (0xff << LCDC_LCDCFG0_CLKDIV_OFFSET) - -#define ATMEL_LCDC_LCDCFG1 0x0004 -#define LCDC_LCDCFG1_HSPW_OFFSET 0 -#define LCDC_LCDCFG1_HSPW (0x3f << LCDC_LCDCFG1_HSPW_OFFSET) -#define LCDC_LCDCFG1_VSPW_OFFSET 16 -#define LCDC_LCDCFG1_VSPW (0x3f << LCDC_LCDCFG1_VSPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG2 0x0008 -#define LCDC_LCDCFG2_VFPW_OFFSET 0 -#define LCDC_LCDCFG2_VFPW (0x3f << LCDC_LCDCFG2_VFPW_OFFSET) -#define LCDC_LCDCFG2_VBPW_OFFSET 16 -#define LCDC_LCDCFG2_VBPW (0x3f << LCDC_LCDCFG2_VBPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG3 0x000C -#define LCDC_LCDCFG3_HFPW_OFFSET 0 -#define LCDC_LCDCFG3_HFPW (0xff << LCDC_LCDCFG3_HFPW_OFFSET) -#define LCDC2_LCDCFG3_HFPW (0x1ff << LCDC_LCDCFG3_HFPW_OFFSET) -#define LCDC_LCDCFG3_HBPW_OFFSET 16 -#define LCDC_LCDCFG3_HBPW (0xff << LCDC_LCDCFG3_HBPW_OFFSET) -#define LCDC2_LCDCFG3_HBPW (0x1ff << LCDC_LCDCFG3_HBPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG4 0x0010 -#define LCDC_LCDCFG4_PPL_OFFSET 0 -#define LCDC_LCDCFG4_PPL (0x7ff << LCDC_LCDCFG4_PPL_OFFSET) -#define LCDC_LCDCFG4_RPF_OFFSET 16 -#define LCDC_LCDCFG4_RPF (0x7ff << LCDC_LCDCFG4_RPF_OFFSET) - -#define ATMEL_LCDC_LCDCFG5 0x0014 -#define LCDC_LCDCFG5_HSPOL (0x1 << 0) -#define LCDC_LCDCFG5_VSPOL (0x1 << 1) -#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) -#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) -#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) -#define LCDC_LCDCFG5_SERIAL (0x1 << 5) -#define LCDC_LCDCFG5_DITHER (0x1 << 6) -#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) -#define LCDC_LCDCFG5_MODE_OFFSET 8 -#define LCDC_LCDCFG5_MODE (0x3 << LCDC_LCDCFG5_MODE_OFFSET) -#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) -#define LCDC_LCDCFG5_PP (0x1 << 10) -#define LCDC_LCDCFG5_VSPSU (0x1 << 12) -#define LCDC_LCDCFG5_VSPHO (0x1 << 13) -#define LCDC_LCDCFG5_GUARDTIME_OFFSET 16 -#define LCDC_LCDCFG5_GUARDTIME (0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET) - -#define ATMEL_LCDC_LCDCFG6 0x0018 -#define LCDC_LCDCFG6_PWMPS_OFFSET 0 -#define LCDC_LCDCFG6_PWMPS (0x7 << LCDC_LCDCFG6_PWMPS_OFFSET) -#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) -#define LCDC_LCDCFG6_PWMCVAL_OFFSET 8 -#define LCDC_LCDCFG6_PWMCVAL (0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET) - -#define ATMEL_LCDC_LCDEN 0x0020 -#define LCDC_LCDEN_CLKEN (0x1 << 0) -#define LCDC_LCDEN_SYNCEN (0x1 << 1) -#define LCDC_LCDEN_DISPEN (0x1 << 2) -#define LCDC_LCDEN_PWMEN (0x1 << 3) - -#define ATMEL_LCDC_LCDDIS 0x0024 -#define LCDC_LCDDIS_CLKDIS (0x1 << 0) -#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) -#define LCDC_LCDDIS_DISPDIS (0x1 << 2) -#define LCDC_LCDDIS_PWMDIS (0x1 << 3) -#define LCDC_LCDDIS_CLKRST (0x1 << 8) -#define LCDC_LCDDIS_SYNCRST (0x1 << 9) -#define LCDC_LCDDIS_DISPRST (0x1 << 10) -#define LCDC_LCDDIS_PWMRST (0x1 << 11) - -#define ATMEL_LCDC_LCDSR 0x0028 -#define LCDC_LCDSR_CLKSTS (0x1 << 0) -#define LCDC_LCDSR_LCDSTS (0x1 << 1) -#define LCDC_LCDSR_DISPSTS (0x1 << 2) -#define LCDC_LCDSR_PWMSTS (0x1 << 3) -#define LCDC_LCDSR_SIPSTS (0x1 << 4) - -#define ATMEL_LCDC_LCDIER 0x002C -#define LCDC_LCDIER_SOFIE (0x1 << 0) -#define LCDC_LCDIER_DISIE (0x1 << 1) -#define LCDC_LCDIER_DISPIE (0x1 << 2) -#define LCDC_LCDIER_FIFOERRIE (0x1 << 4) -#define LCDC_LCDIER_BASEIE (0x1 << 8) -#define LCDC_LCDIER_OVR1IE (0x1 << 9) -#define LCDC_LCDIER_OVR2IE (0x1 << 10) -#define LCDC_LCDIER_HEOIE (0x1 << 11) -#define LCDC_LCDIER_HCRIE (0x1 << 12) -#define LCDC_LCDIER_PPIE (0x1 << 13) - -#define ATMEL_LCDC_LCDIDR 0x0030 -#define LCDC_LCDIDR_SOFID (0x1 << 0) -#define LCDC_LCDIDR_DISID (0x1 << 1) -#define LCDC_LCDIDR_DISPID (0x1 << 2) -#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) -#define LCDC_LCDIDR_BASEID (0x1 << 8) -#define LCDC_LCDIDR_OVR1ID (0x1 << 9) -#define LCDC_LCDIDR_OVR2ID (0x1 << 10) -#define LCDC_LCDIDR_HEOID (0x1 << 11) -#define LCDC_LCDIDR_HCRID (0x1 << 12) -#define LCDC_LCDIDR_PPID (0x1 << 13) - -#define ATMEL_LCDC_LCDIMR 0x0034 -#define LCDC_LCDIMR_SOFIM (0x1 << 0) -#define LCDC_LCDIMR_DISIM (0x1 << 1) -#define LCDC_LCDIMR_DISPIM (0x1 << 2) -#define LCDC_LCDIMR_FIFOERRIM (0x1 << 4) -#define LCDC_LCDIMR_BASEIM (0x1 << 8) -#define LCDC_LCDIMR_OVR1IM (0x1 << 9) -#define LCDC_LCDIMR_OVR2IM (0x1 << 10) -#define LCDC_LCDIMR_HEOIM (0x1 << 11) -#define LCDC_LCDIMR_HCRIM (0x1 << 12) -#define LCDC_LCDIMR_PPIM (0x1 << 13) - -#define ATMEL_LCDC_LCDISR 0x0038 -#define LCDC_LCDISR_SOF (0x1 << 0) -#define LCDC_LCDISR_DIS (0x1 << 1) -#define LCDC_LCDISR_DISP (0x1 << 2) -#define LCDC_LCDISR_FIFOERR (0x1 << 4) -#define LCDC_LCDISR_BASE (0x1 << 8) -#define LCDC_LCDISR_OVR1 (0x1 << 9) -#define LCDC_LCDISR_OVR2 (0x1 << 10) -#define LCDC_LCDISR_HEO (0x1 << 11) -#define LCDC_LCDISR_HCR (0x1 << 12) -#define LCDC_LCDISR_PP (0x1 << 13) - -#define ATMEL_LCDC_BASECHER 0x0040 -#define LCDC_BASECHER_CHEN (0x1 << 0) -#define LCDC_BASECHER_UPDATEEN (0x1 << 1) -#define LCDC_BASECHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_BASECHDR 0x0044 -#define LCDC_BASECHDR_CHDIS (0x1 << 0) -#define LCDC_BASECHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_BASECHSR 0x0048 -#define LCDC_BASECHSR_CHSR (0x1 << 0) -#define LCDC_BASECHSR_UPDATESR (0x1 << 1) -#define LCDC_BASECHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_BASEIER 0x004C -#define LCDC_BASEIER_DMA (0x1 << 2) -#define LCDC_BASEIER_DSCR (0x1 << 3) -#define LCDC_BASEIER_ADD (0x1 << 4) -#define LCDC_BASEIER_DONE (0x1 << 5) -#define LCDC_BASEIER_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEIDR 0x0050 -#define LCDC_BASEIDR_DMA (0x1 << 2) -#define LCDC_BASEIDR_DSCR (0x1 << 3) -#define LCDC_BASEIDR_ADD (0x1 << 4) -#define LCDC_BASEIDR_DONE (0x1 << 5) -#define LCDC_BASEIDR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEIMR 0x0054 -#define LCDC_BASEIMR_DMA (0x1 << 2) -#define LCDC_BASEIMR_DSCR (0x1 << 3) -#define LCDC_BASEIMR_ADD (0x1 << 4) -#define LCDC_BASEIMR_DONE (0x1 << 5) -#define LCDC_BASEIMR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEISR 0x0058 -#define LCDC_BASEISR_DMA (0x1 << 2) -#define LCDC_BASEISR_DSCR (0x1 << 3) -#define LCDC_BASEISR_ADD (0x1 << 4) -#define LCDC_BASEISR_DONE (0x1 << 5) -#define LCDC_BASEISR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEHEAD 0x005C - -#define ATMEL_LCDC_BASEADDR 0x0060 - -#define ATMEL_LCDC_BASECTRL 0x0064 -#define LCDC_BASECTRL_DFETCH (0x1 << 0) -#define LCDC_BASECTRL_LFETCH (0x1 << 1) -#define LCDC_BASECTRL_DMAIEN (0x1 << 2) -#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) -#define LCDC_BASECTRL_ADDIEN (0x1 << 4) -#define LCDC_BASECTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_BASENEXT 0x0068 - -#define ATMEL_LCDC_BASECFG0 0x006C -#define LCDC_BASECFG0_SIF (0x1 << 0) -#define LCDC_BASECFG0_BLEN_OFFSET 4 -#define LCDC_BASECFG0_BLEN (0x3 << LCDC_BASECFG0_BLEN_OFFSET) -#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_BASECFG0_DLBO (0x1 << 8) - -#define ATMEL_LCDC_BASECFG1 0x0070 -#define LCDC_BASECFG1_CLUTEN (0x1 << 0) -#define LCDC_BASECFG1_RGBMODE_OFFSET 4 -#define LCDC_BASECFG1_RGBMODE (0xf << LCDC_BASECFG1_RGBMODE_OFFSET) -#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_BASECFG1_CLUTMODE_OFFSET 8 -#define LCDC_BASECFG1_CLUTMODE (0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET) -#define LCDC_BASECFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_BASECFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_BASECFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_BASECFG1_CLUTMODE_8BPP (0x3 << 8) - -#define ATMEL_LCDC_BASECFG2 0x0074 - -#define ATMEL_LCDC_BASECFG3 0x0078 -#define LCDC_BASECFG3_BDEF_OFFSET 0 -#define LCDC_BASECFG3_BDEF (0xff << LCDC_BASECFG3_BDEF_OFFSET) -#define LCDC_BASECFG3_GDEF_OFFSET 8 -#define LCDC_BASECFG3_GDEF (0xff << LCDC_BASECFG3_GDEF_OFFSET) -#define LCDC_BASECFG3_RDEF_OFFSET 16 -#define LCDC_BASECFG3_RDEF (0xff << LCDC_BASECFG3_RDEF_OFFSET) - -#define ATMEL_LCDC_BASECFG4 0x007C -#define LCDC_BASECFG4_DMA (0x1 << 8) -#define LCDC_BASECFG4_REP (0x1 << 9) -#define LCDC_BASECFG4_DISCEN (0x1 << 11) - -#define ATMEL_LCDC_BASECFG5 0x0080 -#define LCDC_BASECFG5_DISCXPOS_OFFSET 0 -#define LCDC_BASECFG5_DISCXPOS (0x7ff << LCDC_BASECFG5_DISCXPOS_OFFSET) -#define LCDC_BASECFG5_DISCYPOS_OFFSET 16 -#define LCDC_BASECFG5_DISCYPOS (0x7ff << LCDC_BASECFG5_DISCYPOS_OFFSET) - -#define ATMEL_LCDC_BASECFG6 0x0084 -#define LCDC_BASECFG6_DISCXSIZE_OFFSET 0 -#define LCDC_BASECFG6_DISCXSIZE (0x7ff << LCDC_BASECFG6_DISCXSIZE_OFFSET) -#define LCDC_BASECFG6_DISCYSIZE_OFFSET 16 -#define LCDC_BASECFG6_DISCYSIZE (0x7ff << LCDC_BASECFG6_DISCYSIZE_OFFSET) - -#define ATMEL_LCDC_HEOCHER 0x0280 -#define ATMEL_LCDC2_HEOCHER 0x0340 -#define LCDC_HEOCHER_CHEN (0x1 << 0) -#define LCDC_HEOCHER_UPDATEEN (0x1 << 1) -#define LCDC_HEOCHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_HEOCHDR 0x0284 -#define LCDC_HEOCHDR_CHDIS (0x1 << 0) -#define LCDC_HEOCHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_HEOCHSR 0x0288 -#define LCDC_HEOCHSR_CHSR (0x1 << 0) -#define LCDC_HEOCHSR_UPDATESR (0x1 << 1) -#define LCDC_HEOCHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_HEOIER 0x028C -#define LCDC_HEOIER_DMA (0x1 << 2) -#define LCDC_HEOIER_DSCR (0x1 << 3) -#define LCDC_HEOIER_ADD (0x1 << 4) -#define LCDC_HEOIER_DONE (0x1 << 5) -#define LCDC_HEOIER_OVR (0x1 << 6) -#define LCDC_HEOIER_UDMA (0x1 << 10) -#define LCDC_HEOIER_UDSCR (0x1 << 11) -#define LCDC_HEOIER_UADD (0x1 << 12) -#define LCDC_HEOIER_UDONE (0x1 << 13) -#define LCDC_HEOIER_UOVR (0x1 << 14) -#define LCDC_HEOIER_VDMA (0x1 << 18) -#define LCDC_HEOIER_VDSCR (0x1 << 19) -#define LCDC_HEOIER_VADD (0x1 << 20) -#define LCDC_HEOIER_VDONE (0x1 << 21) -#define LCDC_HEOIER_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOIDR 0x0290 -#define LCDC_HEOIDR_DMA (0x1 << 2) -#define LCDC_HEOIDR_DSCR (0x1 << 3) -#define LCDC_HEOIDR_ADD (0x1 << 4) -#define LCDC_HEOIDR_DONE (0x1 << 5) -#define LCDC_HEOIDR_OVR (0x1 << 6) -#define LCDC_HEOIDR_UDMA (0x1 << 10) -#define LCDC_HEOIDR_UDSCR (0x1 << 11) -#define LCDC_HEOIDR_UADD (0x1 << 12) -#define LCDC_HEOIDR_UDONE (0x1 << 13) -#define LCDC_HEOIDR_UOVR (0x1 << 14) -#define LCDC_HEOIDR_VDMA (0x1 << 18) -#define LCDC_HEOIDR_VDSCR (0x1 << 19) -#define LCDC_HEOIDR_VADD (0x1 << 20) -#define LCDC_HEOIDR_VDONE (0x1 << 21) -#define LCDC_HEOIDR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOIMR 0x0294 -#define LCDC_HEOIMR_DMA (0x1 << 2) -#define LCDC_HEOIMR_DSCR (0x1 << 3) -#define LCDC_HEOIMR_ADD (0x1 << 4) -#define LCDC_HEOIMR_DONE (0x1 << 5) -#define LCDC_HEOIMR_OVR (0x1 << 6) -#define LCDC_HEOIMR_UDMA (0x1 << 10) -#define LCDC_HEOIMR_UDSCR (0x1 << 11) -#define LCDC_HEOIMR_UADD (0x1 << 12) -#define LCDC_HEOIMR_UDONE (0x1 << 13) -#define LCDC_HEOIMR_UOVR (0x1 << 14) -#define LCDC_HEOIMR_VDMA (0x1 << 18) -#define LCDC_HEOIMR_VDSCR (0x1 << 19) -#define LCDC_HEOIMR_VADD (0x1 << 20) -#define LCDC_HEOIMR_VDONE (0x1 << 21) -#define LCDC_HEOIMR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOISR 0x0298 -#define LCDC_HEOISR_DMA (0x1 << 2) -#define LCDC_HEOISR_DSCR (0x1 << 3) -#define LCDC_HEOISR_ADD (0x1 << 4) -#define LCDC_HEOISR_DONE (0x1 << 5) -#define LCDC_HEOISR_OVR (0x1 << 6) -#define LCDC_HEOISR_UDMA (0x1 << 10) -#define LCDC_HEOISR_UDSCR (0x1 << 11) -#define LCDC_HEOISR_UADD (0x1 << 12) -#define LCDC_HEOISR_UDONE (0x1 << 13) -#define LCDC_HEOISR_UOVR (0x1 << 14) -#define LCDC_HEOISR_VDMA (0x1 << 18) -#define LCDC_HEOISR_VDSCR (0x1 << 19) -#define LCDC_HEOISR_VADD (0x1 << 20) -#define LCDC_HEOISR_VDONE (0x1 << 21) -#define LCDC_HEOISR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOHEAD 0x029C - -#define ATMEL_LCDC_HEOADDR 0x02A0 - -#define ATMEL_LCDC_HEOCTRL 0x02A4 -#define LCDC_HEOCTRL_DFETCH (0x1 << 0) -#define LCDC_HEOCTRL_LFETCH (0x1 << 1) -#define LCDC_HEOCTRL_DMAIEN (0x1 << 2) -#define LCDC_HEOCTRL_DSCRIEN (0x1 << 3) -#define LCDC_HEOCTRL_ADDIEN (0x1 << 4) -#define LCDC_HEOCTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEONEXT 0x02A8 - -#define ATMEL_LCDC_HEOUHEAD 0x02AC - -#define ATMEL_LCDC_HEOUADDR 0x02B0 - -#define ATMEL_LCDC_HEOUCTRL 0x02B4 -#define LCDC_HEOUCTRL_UDFETCH (0x1 << 0) -#define LCDC_HEOUCTRL_UDMAIEN (0x1 << 2) -#define LCDC_HEOUCTRL_UDSCRIEN (0x1 << 3) -#define LCDC_HEOUCTRL_UADDIEN (0x1 << 4) -#define LCDC_HEOUCTRL_UDONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEOUNEXT 0x02B8 - -#define ATMEL_LCDC_HEOVHEAD 0x02BC - -#define ATMEL_LCDC_HEOVADDR 0x02C0 - -#define ATMEL_LCDC_HEOVCTRL 0x02C4 -#define LCDC_HEOVCTRL_VDFETCH (0x1 << 0) -#define LCDC_HEOVCTRL_VDMAIEN (0x1 << 2) -#define LCDC_HEOVCTRL_VDSCRIEN (0x1 << 3) -#define LCDC_HEOVCTRL_VADDIEN (0x1 << 4) -#define LCDC_HEOVCTRL_VDONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEOVNEXT 0x02C8 - -#define ATMEL_LCDC_HEOCFG0 0x02CC -#define LCDC_HEOCFG0_BLEN_OFFSET 4 -#define LCDC_HEOCFG0_BLEN (0x3 << LCDC_HEOCFG0_BLEN_OFFSET) -#define LCDC_HEOCFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_HEOCFG0_BLENUV_OFFSET 6 -#define LCDC_HEOCFG0_BLENUV (0x3 << LCDC_HEOCFG0_BLENUV_OFFSET) -#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3 << 6) -#define LCDC_HEOCFG0_DLBO (0x1 << 8) -#define LCDC_HEOCFG0_ROTDIS (0x1 << 12) -#define LCDC_HEOCFG0_LOCKDIS (0x1 << 13) - -#define ATMEL_LCDC_HEOCFG1 0x02D0 -#define LCDC_HEOCFG1_CLUTEN (0x1 << 0) -#define LCDC_HEOCFG1_YUVEN (0x1 << 1) -#define LCDC_HEOCFG1_RGBMODE_OFFSET 4 -#define LCDC_HEOCFG1_RGBMODE (0xf << LCDC_HEOCFG1_RGBMODE_OFFSET) -#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_HEOCFG1_CLUTMODE_OFFSET 8 -#define LCDC_HEOCFG1_CLUTMODE (0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET) -#define LCDC_HEOCFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_HEOCFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_HEOCFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_HEOCFG1_CLUTMODE_8BPP (0x3 << 8) -#define LCDC_HEOCFG1_YUVMODE_OFFSET 12 -#define LCDC_HEOCFG1_YUVMODE (0xf << LCDC_HEOCFG1_YUVMODE_OFFSET) -#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6 << 12) -#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7 << 12) -#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8 << 12) -#define LCDC_HEOCFG1_YUV422ROT (0x1 << 16) -#define LCDC_HEOCFG1_YUV422SWP (0x1 << 17) - -#define ATMEL_LCDC_HEOCFG2 0x02D4 -#define LCDC_HEOCFG2_XOFFSET_OFFSET 0 -#define LCDC_HEOCFG2_XOFFSET (0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET) -#define LCDC_HEOCFG2_YOFFSET_OFFSET 16 -#define LCDC_HEOCFG2_YOFFSET (0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET) - -#define ATMEL_LCDC_HEOCFG3 0x02D8 -#define LCDC_HEOCFG3_XSIZE_OFFSET 0 -#define LCDC_HEOCFG3_XSIZE (0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET) -#define LCDC_HEOCFG3_YSIZE_OFFSET 16 -#define LCDC_HEOCFG3_YSIZE (0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET) - -#define ATMEL_LCDC_HEOCFG4 0x02DC -#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET 0 -#define LCDC_HEOCFG4_XMEM_SIZE (0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET) -#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET 16 -#define LCDC_HEOCFG4_YMEM_SIZE (0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET) - -#define ATMEL_LCDC_HEOCFG5 0x02E0 - -#define ATMEL_LCDC_HEOCFG6 0x02E4 - -#define ATMEL_LCDC_HEOCFG7 0x02E8 - -#define ATMEL_LCDC_HEOCFG8 0x02EC - -#define ATMEL_LCDC_HEOCFG9 0x02F0 -#define LCDC_HEOCFG9_BDEF_OFFSET 0 -#define LCDC_HEOCFG9_BDEF (0xff << LCDC_HEOCFG9_BDEF_OFFSET) -#define LCDC_HEOCFG9_GDEF_OFFSET 8 -#define LCDC_HEOCFG9_GDEF (0xff << LCDC_HEOCFG9_GDEF_OFFSET) -#define LCDC_HEOCFG9_RDEF_OFFSET 16 -#define LCDC_HEOCFG9_RDEF (0xff << LCDC_HEOCFG9_RDEF_OFFSET) - -#define ATMEL_LCDC_HEOCFG10 0x02F4 -#define LCDC_HEOCFG10_BKEY_OFFSET 0 -#define LCDC_HEOCFG10_BKEY (0xff << LCDC_HEOCFG10_BKEY_OFFSET) -#define LCDC_HEOCFG10_GKEY_OFFSET 8 -#define LCDC_HEOCFG10_GKEY (0xff << LCDC_HEOCFG10_GKEY_OFFSET) -#define LCDC_HEOCFG10_RKEY_OFFSET 16 -#define LCDC_HEOCFG10_RKEY (0xff << LCDC_HEOCFG10_RKEY_OFFSET) - -#define ATMEL_LCDC_HEOCFG11 0x02F8 -#define LCDC_HEOCFG11_BMASK_OFFSET 0 -#define LCDC_HEOCFG11_BMASK (0xff << LCDC_HEOCFG11_BMASK_OFFSET) -#define LCDC_HEOCFG11_GMASK_OFFSET 8 -#define LCDC_HEOCFG11_GMASK (0xff << LCDC_HEOCFG11_GMASK_OFFSET) -#define LCDC_HEOCFG11_RMASK_OFFSET 16 -#define LCDC_HEOCFG11_RMASK (0xff << LCDC_HEOCFG11_RMASK_OFFSET) - -#define ATMEL_LCDC_HEOCFG12 0x02FC -#define LCDC_HEOCFG12_CRKEY (0x1 << 0) -#define LCDC_HEOCFG12_INV (0x1 << 1) -#define LCDC_HEOCFG12_ITER2BL (0x1 << 2) -#define LCDC_HEOCFG12_ITER (0x1 << 3) -#define LCDC_HEOCFG12_REVALPHA (0x1 << 4) -#define LCDC_HEOCFG12_GAEN (0x1 << 5) -#define LCDC_HEOCFG12_LAEN (0x1 << 6) -#define LCDC_HEOCFG12_OVR (0x1 << 7) -#define LCDC_HEOCFG12_DMA (0x1 << 8) -#define LCDC_HEOCFG12_REP (0x1 << 9) -#define LCDC_HEOCFG12_DSTKEY (0x1 << 10) -#define LCDC_HEOCFG12_VIDPRI (0x1 << 12) -#define LCDC_HEOCFG12_GA_OFFSET 16 -#define LCDC_HEOCFG12_GA (0xff << LCDC_HEOCFG12_GA_OFFSET) - -#define ATMEL_LCDC_HEOCFG13 0x0300 -#define LCDC_HEOCFG13_XFACTOR_OFFSET 0 -#define LCDC_HEOCFG13_XFACTOR (0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET) -#define LCDC_HEOCFG13_YFACTOR_OFFSET 16 -#define LCDC_HEOCFG13_YFACTOR (0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET) -#define LCDC_HEOCFG13_SCALEN (0x1 << 31) - -#define ATMEL_LCDC_HEOCFG14 0x0304 -#define LCDC_HEOCFG14_CSCRY_OFFSET 0 -#define LCDC_HEOCFG14_CSCRY (0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET) -#define LCDC_HEOCFG14_CSCRU_OFFSET 10 -#define LCDC_HEOCFG14_CSCRU (0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET) -#define LCDC_HEOCFG14_CSCRV_OFFSET 20 -#define LCDC_HEOCFG14_CSCRV (0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET) -#define LCDC_HEOCFG14_CSCYOFF (0x1 << 30) - -#define ATMEL_LCDC_HEOCFG15 0x0308 -#define LCDC_HEOCFG15_CSCGY_OFFSET 0 -#define LCDC_HEOCFG15_CSCGY (0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET) -#define LCDC_HEOCFG15_CSCGU_OFFSET 10 -#define LCDC_HEOCFG15_CSCGU (0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET) -#define LCDC_HEOCFG15_CSCGV_OFFSET 20 -#define LCDC_HEOCFG15_CSCGV (0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET) -#define LCDC_HEOCFG15_CSCUOFF (0x1 << 30) - -#define ATMEL_LCDC_HEOCFG16 0x030C -#define LCDC_HEOCFG16_CSCBY_OFFSET 0 -#define LCDC_HEOCFG16_CSCBY (0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET) -#define LCDC_HEOCFG16_CSCBU_OFFSET 10 -#define LCDC_HEOCFG16_CSCBU (0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET) -#define LCDC_HEOCFG16_CSCBV_OFFSET 20 -#define LCDC_HEOCFG16_CSCBV (0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET) -#define LCDC_HEOCFG16_CSCVOFF (0x1 << 30) - -#define ATMEL_LCDC_HCRCHER 0x0340 -#define LCDC_HCRCHER_CHEN (0x1 << 0) -#define LCDC_HCRCHER_UPDATEEN (0x1 << 1) -#define LCDC_HCRCHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_HCRCHDR 0x0344 -#define LCDC_HCRCHDR_CHDIS (0x1 << 0) -#define LCDC_HCRCHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_HCRCHSR 0x0348 -#define LCDC_HCRCHSR_CHSR (0x1 << 0) -#define LCDC_HCRCHSR_UPDATESR (0x1 << 1) -#define LCDC_HCRCHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_HCRIER 0x034C -#define LCDC_HCRIER_DMA (0x1 << 2) -#define LCDC_HCRIER_DSCR (0x1 << 3) -#define LCDC_HCRIER_ADD (0x1 << 4) -#define LCDC_HCRIER_DONE (0x1 << 5) -#define LCDC_HCRIER_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRIDR 0x0350 -#define LCDC_HCRIDR_DMA (0x1 << 2) -#define LCDC_HCRIDR_DSCR (0x1 << 3) -#define LCDC_HCRIDR_ADD (0x1 << 4) -#define LCDC_HCRIDR_DONE (0x1 << 5) -#define LCDC_HCRIDR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRIMR 0x0354 -#define LCDC_HCRIMR_DMA (0x1 << 2) -#define LCDC_HCRIMR_DSCR (0x1 << 3) -#define LCDC_HCRIMR_ADD (0x1 << 4) -#define LCDC_HCRIMR_DONE (0x1 << 5) -#define LCDC_HCRIMR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRISR 0x0358 -#define LCDC_HCRISR_DMA (0x1 << 2) -#define LCDC_HCRISR_DSCR (0x1 << 3) -#define LCDC_HCRISR_ADD (0x1 << 4) -#define LCDC_HCRISR_DONE (0x1 << 5) -#define LCDC_HCRISR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRHEAD 0x035C - -#define ATMEL_LCDC_HCRADDR 0x0360 - -#define ATMEL_LCDC_HCRCTRL 0x0364 -#define LCDC_HCRCTRL_DFETCH (0x1 << 0) -#define LCDC_HCRCTRL_LFETCH (0x1 << 1) -#define LCDC_HCRCTRL_DMAIEN (0x1 << 2) -#define LCDC_HCRCTRL_DSCRIEN (0x1 << 3) -#define LCDC_HCRCTRL_ADDIEN (0x1 << 4) -#define LCDC_HCRCTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HCRNEXT 0x0368 - -#define ATMEL_LCDC_HCRCFG0 0x036C -#define LCDC_HCRCFG0_BLEN_OFFSET 4 -#define LCDC_HCRCFG0_BLEN (0x3 << LCDC_HCRCFG0_BLEN_OFFSET) -#define LCDC_HCRCFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_HCRCFG0_DLBO (0x1 << 8) - -#define ATMEL_LCDC_HCRCFG1 0x0370 -#define LCDC_HCRCFG1_CLUTEN (0x1 << 0) -#define LCDC_HCRCFG1_RGBMODE_OFFSET 4 -#define LCDC_HCRCFG1_RGBMODE (0xf << LCDC_HCRCFG1_RGBMODE_OFFSET) -#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_HCRCFG1_CLUTMODE_OFFSET 8 -#define LCDC_HCRCFG1_CLUTMODE (0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET) -#define LCDC_HCRCFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_HCRCFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_HCRCFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_HCRCFG1_CLUTMODE_8BPP (0x3 << 8) - -#define ATMEL_LCDC_HCRCFG2 0x0374 -#define LCDC_HCRCFG2_XOFFSET_OFFSET 0 -#define LCDC_HCRCFG2_XOFFSET (0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET) -#define LCDC_HCRCFG2_YOFFSET_OFFSET 16 -#define LCDC_HCRCFG2_YOFFSET (0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET) - -#define ATMEL_LCDC_HCRCFG3 0x0378 -#define LCDC_HCRCFG3_XSIZE_OFFSET 0 -#define LCDC_HCRCFG3_XSIZE (0x7f << LCDC_HCRCFG3_XSIZE_OFFSET) -#define LCDC_HCRCFG3_YSIZE_OFFSET 16 -#define LCDC_HCRCFG3_YSIZE (0x7f << LCDC_HCRCFG3_YSIZE_OFFSET) - -#define ATMEL_LCDC_HCRCFG4 0x037C - -#define ATMEL_LCDC_HCRCFG6 0x0384 -#define LCDC_HCRCFG6_BDEF_OFFSET 0 -#define LCDC_HCRCFG6_BDEF (0xff << LCDC_HCRCFG6_BDEF_OFFSET) -#define LCDC_HCRCFG6_GDEF_OFFSET 8 -#define LCDC_HCRCFG6_GDEF (0xff << LCDC_HCRCFG6_GDEF_OFFSET) -#define LCDC_HCRCFG6_RDEF_OFFSET 16 -#define LCDC_HCRCFG6_RDEF (0xff << LCDC_HCRCFG6_RDEF_OFFSET) - -#define ATMEL_LCDC_HCRCFG7 0x0388 -#define LCDC_HCRCFG7_BKEY_OFFSET 0 -#define LCDC_HCRCFG7_BKEY (0xff << LCDC_HCRCFG7_BKEY_OFFSET) -#define LCDC_HCRCFG7_GKEY_OFFSET 8 -#define LCDC_HCRCFG7_GKEY (0xff << LCDC_HCRCFG7_GKEY_OFFSET) -#define LCDC_HCRCFG7_RKEY_OFFSET 16 -#define LCDC_HCRCFG7_RKEY (0xff << LCDC_HCRCFG7_RKEY_OFFSET) - -#define ATMEL_LCDC_HCRCFG8 0x038C -#define LCDC_HCRCFG8_BMASK_OFFSET 0 -#define LCDC_HCRCFG8_BMASK (0xff << LCDC_HCRCFG8_BMASK_OFFSET) -#define LCDC_HCRCFG8_GMASK_OFFSET 8 -#define LCDC_HCRCFG8_GMASK (0xff << LCDC_HCRCFG8_GMASK_OFFSET) -#define LCDC_HCRCFG8_RMASK_OFFSET 16 -#define LCDC_HCRCFG8_RMASK (0xff << LCDC_HCRCFG8_RMASK_OFFSET) - -#define ATMEL_LCDC_HCRCFG9 0x0390 -#define LCDC_HCRCFG9_CRKEY (0x1 << 0) -#define LCDC_HCRCFG9_INV (0x1 << 1) -#define LCDC_HCRCFG9_ITER2BL (0x1 << 2) -#define LCDC_HCRCFG9_ITER (0x1 << 3) -#define LCDC_HCRCFG9_REVALPHA (0x1 << 4) -#define LCDC_HCRCFG9_GAEN (0x1 << 5) -#define LCDC_HCRCFG9_LAEN (0x1 << 6) -#define LCDC_HCRCFG9_OVR (0x1 << 7) -#define LCDC_HCRCFG9_DMA (0x1 << 8) -#define LCDC_HCRCFG9_REP (0x1 << 9) -#define LCDC_HCRCFG9_DSTKEY (0x1 << 10) -#define LCDC_HCRCFG9_GA_OFFSET 16 -#define LCDC_HCRCFG9_GA_Msk (0xff << LCDC_HCRCFG9_GA_OFFSET) - -#define ATMEL_LCDC_BASECLUT 0x400 -#define ATMEL_LCDC2_BASECLUT 0x600 -#define LCDC_BASECLUT_BCLUT_OFFSET 0 -#define LCDC_BASECLUT_BCLUT (0xff << LCDC_BASECLUT_BCLUT_OFFSET) -#define LCDC_BASECLUT_GCLUT_OFFSET 8 -#define LCDC_BASECLUT_GCLUT (0xff << LCDC_BASECLUT_GCLUT_OFFSET) -#define LCDC_BASECLUT_RCLUT_OFFSET 16 -#define LCDC_BASECLUT_RCLUT (0xff << LCDC_BASECLUT_RCLUT_OFFSET) - -#define ATMEL_LCDC_OVR1CLUT 0x800 -#define ATMEL_LCDC2_OVR1CLUT 0xa00 -#define LCDC_OVR1CLUT_BCLUT_OFFSET 0 -#define LCDC_OVR1CLUT_BCLUT (0xff << LCDC_OVR1CLUT_BCLUT_OFFSET) -#define LCDC_OVR1CLUT_GCLUT_OFFSET 8 -#define LCDC_OVR1CLUT_GCLUT (0xff << LCDC_OVR1CLUT_GCLUT_OFFSET) -#define LCDC_OVR1CLUT_RCLUT_OFFSET 16 -#define LCDC_OVR1CLUT_RCLUT (0xff << LCDC_OVR1CLUT_RCLUT_OFFSET) -#define LCDC_OVR1CLUT_ACLUT_OFFSET 24 -#define LCDC_OVR1CLUT_ACLUT (0xff << LCDC_OVR1CLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_OVR2CLUT 0xe00 -#define LCDC_OVR2CLUT_BCLUT_OFFSET 0 -#define LCDC_OVR2CLUT_BCLUT (0xff << LCDC_OVR2CLUT_BCLUT_OFFSET) -#define LCDC_OVR2CLUT_GCLUT_OFFSET 8 -#define LCDC_OVR2CLUT_GCLUT (0xff << LCDC_OVR2CLUT_GCLUT_OFFSET) -#define LCDC_OVR2CLUT_RCLUT_OFFSET 16 -#define LCDC_OVR2CLUT_RCLUT (0xff << LCDC_OVR2CLUT_RCLUT_OFFSET) -#define LCDC_OVR2CLUT_ACLUT_OFFSET 24 -#define LCDC_OVR2CLUT_ACLUT (0xff << LCDC_OVR2CLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_HEOCLUT 0x1000 -#define ATMEL_LCDC2_HEOCLUT 0x1200 -#define LCDC_HEOCLUT_BCLUT_OFFSET 0 -#define LCDC_HEOCLUT_BCLUT (0xff << LCDC_HEOCLUT_BCLUT_OFFSET) -#define LCDC_HEOCLUT_GCLUT_OFFSET 8 -#define LCDC_HEOCLUT_GCLUT (0xff << LCDC_HEOCLUT_GCLUT_OFFSET) -#define LCDC_HEOCLUT_RCLUT_OFFSET 16 -#define LCDC_HEOCLUT_RCLUT (0xff << LCDC_HEOCLUT_RCLUT_OFFSET) -#define LCDC_HEOCLUT_ACLUT_OFFSET 24 -#define LCDC_HEOCLUT_ACLUT (0xff << LCDC_HEOCLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_HCRCLUT 0x1400 -#define ATMEL_LCDC2_HCRCLUT 0x1600 -#define LCDC_HCRCLUT_BCLUT_OFFSET 0 -#define LCDC_HCRCLUT_BCLUT (0xff << LCDC_HCRCLUT_BCLUT_OFFSET) -#define LCDC_HCRCLUT_GCLUT_OFFSET 8 -#define LCDC_HCRCLUT_GCLUT (0xff << LCDC_HCRCLUT_GCLUT_OFFSET) -#define LCDC_HCRCLUT_RCLUT_OFFSET 16 -#define LCDC_HCRCLUT_RCLUT (0xff << LCDC_HCRCLUT_RCLUT_OFFSET) -#define LCDC_HCRCLUT_ACLUT_OFFSET 24 -#define LCDC_HCRCLUT_ACLUT (0xff << LCDC_HCRCLUT_ACLUT_OFFSET) - -/* Base layer CLUT */ -#define ATMEL_HLCDC_LUT 0x0400 - - -#endif /* __MACH_ATMEL_HLCDC4_H__ */ diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h deleted file mode 100644 index 4a95f89fc9..0000000000 --- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_ARM_HEAD_H -#define __MACH_ARM_HEAD_H - -#ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM -#define AT91_EXV6 ".word _barebox_image_size\n" -#else -#define AT91_EXV6 ".word _barebox_bare_init_size\n" -#endif - -static inline void __barebox_arm_head(void) -{ - __asm__ __volatile__ ( -#ifdef CONFIG_THUMB2_BAREBOX -#error Thumb2 is not supported -#else - "b 2f\n" - "1: b 1b\n" - "1: b 1b\n" - "1: b 1b\n" - "1: b 1b\n" - AT91_EXV6 /* image size to load by the bootrom */ - "1: b 1b\n" - "1: b 1b\n" -#endif - ".asciz \"barebox\"\n" - ".word _text\n" /* text base. If copied there, - * barebox can skip relocation - */ - ".word _barebox_image_size\n" /* image size to copy */ - ".rept 8\n" - ".word 0x55555555\n" - ".endr\n" - "2:\n" - ); -} - -static inline void barebox_arm_head(void) -{ - __barebox_arm_head(); - __asm__ __volatile__ ( - "b barebox_arm_reset_vector\n" - ); -} - -#endif /* __MACH_ARM_HEAD_H */ diff --git a/arch/arm/mach-at91/include/mach/barebox-arm.h b/arch/arm/mach-at91/include/mach/barebox-arm.h deleted file mode 100644 index 4a65c6f8fa..0000000000 --- a/arch/arm/mach-at91/include/mach/barebox-arm.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AT91_BAREBOX_ARM_H_ -#define AT91_BAREBOX_ARM_H_ - -#include <asm/barebox-arm.h> - -#define SAMA5_ENTRY_FUNCTION(name, r4) \ - void name (u32 r0, u32 r1, u32 r2, u32 r3); \ - \ - static void __##name(u32); \ - \ - void NAKED __section(.text_head_entry_##name) name \ - (u32 r0, u32 r1, u32 r2, u32 r3) \ - { \ - register u32 r4 asm("r4"); \ - __barebox_arm_head(); \ - __##name(r4); \ - } \ - static void NAKED noinline __##name \ - (u32 r4) -#endif diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h deleted file mode 100644 index 754a6b7c5e..0000000000 --- a/arch/arm/mach-at91/include/mach/board.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 HP Labs */ - -/* [origin Linux: arch/arm/mach-at91/include/mach/board.h] */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include <mach/hardware.h> -#include <linux/sizes.h> -#include <net.h> -#include <i2c/i2c.h> -#include <spi/spi.h> -#include <linux/mtd/mtd.h> -#include <fb.h> -#include <video/atmel_lcdc.h> -#include <mach/atmel_hlcdc.h> -#include <linux/phy.h> -#include <platform_data/macb.h> - -void at91_set_main_clock(unsigned long rate); - -#define AT91_MAX_USBH_PORTS 3 - - /* USB Host */ -struct at91_usbh_data { - u8 ports; /* number of ports on root hub */ - int vbus_pin[AT91_MAX_USBH_PORTS]; /* port power-control pin */ - u8 vbus_pin_active_low[AT91_MAX_USBH_PORTS]; /* vbus polarity */ -}; -extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); -extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data); - -void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize); - - /* USB Device */ -struct at91_udc_data { - int vbus_pin; /* high == host powering us */ - u8 vbus_active_low; /* vbus polarity */ - u8 vbus_polled; /* Use polling, not interrupt */ - int pullup_pin; /* active == D+ pulled up */ - u8 pullup_active_low; /* true == pullup_pin is active low */ -}; -extern void __init at91_add_device_udc(struct at91_udc_data *data); - - /* NAND / SmartMedia */ -struct atmel_nand_data { - int enable_pin; /* chip enable */ - int det_pin; /* card detect */ - int rdy_pin; /* ready/busy */ - u8 ale; /* address line number connected to ALE */ - u8 cle; /* address line number connected to CLE */ - u8 bus_width_16; /* buswidth is 16 bit */ - u8 ecc_mode; /* NAND_ECC_* */ - u8 ecc_strength; /* number of bits to correct per ECC step */ - u8 ecc_size_shift; /* data bytes covered by a single ECC step.*/ - u8 on_flash_bbt; /* Use flash based bbt */ - u8 has_pmecc; /* Use PMECC */ - u8 bus_on_d0; - - u8 pmecc_corr_cap; - u16 pmecc_sector_size; - u32 pmecc_lookup_table_offset; -}; - -void at91_add_device_nand(struct atmel_nand_data *data); - - /* Ethernet (EMAC & MACB) */ -#define AT91SAM_ETX2_ETX3_ALTERNATIVE (1 << 0) - -void at91_add_device_eth(int id, struct macb_platform_data *data); - -void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices); - -/* SDRAM */ -void at91_add_device_sdram(u32 size); - - /* Serial */ -#define ATMEL_UART_CTS 0x01 -#define ATMEL_UART_RTS 0x02 -#define ATMEL_UART_DSR 0x04 -#define ATMEL_UART_DTR 0x08 -#define ATMEL_UART_DCD 0x10 -#define ATMEL_UART_RI 0x20 - -resource_size_t __init at91_configure_dbgu(void); -resource_size_t __init at91_configure_usart0(unsigned pins); -resource_size_t __init at91_configure_usart1(unsigned pins); -resource_size_t __init at91_configure_usart2(unsigned pins); -resource_size_t __init at91_configure_usart3(unsigned pins); -resource_size_t __init at91_configure_usart4(unsigned pins); -resource_size_t __init at91_configure_usart5(unsigned pins); -resource_size_t __init at91_configure_usart6(unsigned pins); - -#if defined(CONFIG_DRIVER_SERIAL_ATMEL) -static inline struct device_d * at91_register_uart(unsigned id, unsigned pins) -{ - resource_size_t start; - resource_size_t size = SZ_16K; - - switch (id) { - case 0: /* DBGU */ - start = at91_configure_dbgu(); - size = 512; - break; - case 1: - start = at91_configure_usart0(pins); - break; - case 2: - start = at91_configure_usart1(pins); - break; - case 3: - start = at91_configure_usart2(pins); - break; - case 4: - start = at91_configure_usart3(pins); - break; - case 5: - start = at91_configure_usart4(pins); - break; - case 6: - start = at91_configure_usart5(pins); - break; - default: - return NULL; - } - - return add_generic_device("atmel_usart", id, NULL, start, size, - IORESOURCE_MEM, NULL); -} -#else -static inline struct device_d * at91_register_uart(unsigned id, unsigned pins) -{ - return NULL; -} -#endif - -#include <platform_data/atmel-mci.h> - -/* SPI Master platform data */ -struct at91_spi_platform_data { - int *chipselect; /* array of gpio_pins */ - int num_chipselect; /* chipselect array entry count */ -}; - -void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata); - -void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data); - -void at91sam_phy_reset(void __iomem *rstc_base); - -void at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr); -void at91sam9g45_reset(void __iomem *sdram, void __iomem *rstc_cr); - -#endif diff --git a/arch/arm/mach-at91/include/mach/bootstrap.h b/arch/arm/mach-at91/include/mach/bootstrap.h deleted file mode 100644 index a3d19dd54a..0000000000 --- a/arch/arm/mach-at91/include/mach/bootstrap.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Under GPLv2 - */ - -#ifndef __MACH_BOOTSTRAP_H__ -#define __MACH_BOOTSTRAP_H__ - -#ifdef CONFIG_MTD_M25P80 -void * bootstrap_board_read_m25p80(void); -#else -static inline void * bootstrap_board_read_m25p80(void) -{ - return NULL; -} -#endif - -#ifdef CONFIG_MTD_DATAFLASH -void * bootstrap_board_read_dataflash(void); -#else -static inline void * bootstrap_board_read_dataflash(void) -{ - return NULL; -} -#endif - -#endif /* __MACH_BOOTSTRAP_H__ */ diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h deleted file mode 100644 index 37e516947b..0000000000 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ /dev/null @@ -1,312 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2006 SAN People */ -/* SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ - -/* arch/arm/mach-at91/include/mach/cpu.h */ - -#ifndef __MACH_CPU_H__ -#define __MACH_CPU_H__ - -#define ARCH_ID_AT91RM9200 0x09290780 -#define ARCH_ID_AT91SAM9260 0x019803a0 -#define ARCH_ID_AT91SAM9261 0x019703a0 -#define ARCH_ID_AT91SAM9263 0x019607a0 -#define ARCH_ID_AT91SAM9G10 0x019903a0 -#define ARCH_ID_AT91SAM9G20 0x019905a0 -#define ARCH_ID_AT91SAM9RL64 0x019b03a0 -#define ARCH_ID_AT91SAM9G45 0x819b05a0 -#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ -#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ -#define ARCH_ID_AT91SAM9X5 0x819a05a0 -#define ARCH_ID_AT91SAM9N12 0x819a07a0 -#define ARCH_ID_SAMA5 0x8A5C07C0 - -#define ARCH_ID_AT91SAM9XE128 0x329973a0 -#define ARCH_ID_AT91SAM9XE256 0x329a93a0 -#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 - -#define ARCH_ID_AT91M40800 0x14080044 -#define ARCH_ID_AT91R40807 0x44080746 -#define ARCH_ID_AT91M40807 0x14080745 -#define ARCH_ID_AT91R40008 0x44000840 - -#define ARCH_EXID_AT91SAM9M11 0x00000001 -#define ARCH_EXID_AT91SAM9M10 0x00000002 -#define ARCH_EXID_AT91SAM9G46 0x00000003 -#define ARCH_EXID_AT91SAM9G45 0x00000004 - -#define ARCH_EXID_AT91SAM9G15 0x00000000 -#define ARCH_EXID_AT91SAM9G35 0x00000001 -#define ARCH_EXID_AT91SAM9X35 0x00000002 -#define ARCH_EXID_AT91SAM9G25 0x00000003 -#define ARCH_EXID_AT91SAM9X25 0x00000004 - -#define ARCH_EXID_AT91SAM9N12 0x00000006 -#define ARCH_EXID_AT91SAM9CN11 0x00000009 -#define ARCH_EXID_AT91SAM9CN12 0x00000005 - -#define ARCH_EXID_SAMA5D21CU 0x0000005a -#define ARCH_EXID_SAMA5D225C_D1M 0x00000053 -#define ARCH_EXID_SAMA5D22CU 0x00000059 -#define ARCH_EXID_SAMA5D22CN 0x00000069 -#define ARCH_EXID_SAMA5D23CU 0x00000058 -#define ARCH_EXID_SAMA5D24CX 0x00000004 -#define ARCH_EXID_SAMA5D24CU 0x00000014 -#define ARCH_EXID_SAMA5D26CU 0x00000012 -#define ARCH_EXID_SAMA5D27C_D1G 0x00000033 -#define ARCH_EXID_SAMA5D27C_D5M 0x00000032 -#define ARCH_EXID_SAMA5D27CU 0x00000011 -#define ARCH_EXID_SAMA5D27CN 0x00000021 -#define ARCH_EXID_SAMA5D28C_D1G 0x00000013 -#define ARCH_EXID_SAMA5D28CU 0x00000010 -#define ARCH_EXID_SAMA5D28CN 0x00000020 - -#define ARCH_EXID_SAMA5D3 0x00004300 -#define ARCH_EXID_SAMA5D31 0x00444300 -#define ARCH_EXID_SAMA5D33 0x00414300 -#define ARCH_EXID_SAMA5D34 0x00414301 -#define ARCH_EXID_SAMA5D35 0x00584300 -#define ARCH_EXID_SAMA5D36 0x00004301 - -#define ARCH_EXID_SAMA5D4 0x00000007 -#define ARCH_EXID_SAMA5D41 0x00000001 -#define ARCH_EXID_SAMA5D42 0x00000002 -#define ARCH_EXID_SAMA5D43 0x00000003 -#define ARCH_EXID_SAMA5D44 0x00000004 - -#define ARCH_FAMILY_AT91X92 0x09200000 -#define ARCH_FAMILY_AT91SAM9 0x01900000 -#define ARCH_FAMILY_AT91SAM9XE 0x02900000 - -/* RM9200 type */ -#define ARCH_REVISON_9200_BGA (0 << 0) -#define ARCH_REVISON_9200_PQFP (1 << 0) - -#ifndef __ASSEMBLY__ -enum at91_soc_type { - /* 920T */ - AT91_SOC_RM9200, - - /* SAM92xx */ - AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, - - /* SAM9Gxx */ - AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, - - /* SAM9RL */ - AT91_SOC_SAM9RL, - - /* SAM9X5 */ - AT91_SOC_SAM9X5, - - /* SAM9N12 */ - AT91_SOC_SAM9N12, - - /* SAMA5D2 */ - AT91_SOC_SAMA5D2, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D3, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D4, - - /* Unknown type */ - AT91_SOC_NONE -}; - -enum at91_soc_subtype { - /* RM9200 */ - AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, - - /* SAM9260 */ - AT91_SOC_SAM9XE, - - /* SAM9G45 */ - AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, - - /* SAM9X5 */ - AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, - AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, - - /* SAM9N12 */ - AT91_SOC_SAM9CN11, AT91_SOC_SAM9CN12, - - /* SAMA5D2 */ - AT91_SOC_SAMA5D21CU, - AT91_SOC_SAMA5D225C_D1M, AT91_SOC_SAMA5D22CU, AT91_SOC_SAMA5D22CN, - AT91_SOC_SAMA5D23CU, AT91_SOC_SAMA5D24CX, AT91_SOC_SAMA5D24CU, - AT91_SOC_SAMA5D26CU, AT91_SOC_SAMA5D27C_D1G, AT91_SOC_SAMA5D27C_D5M, - AT91_SOC_SAMA5D27CU, AT91_SOC_SAMA5D27CN, AT91_SOC_SAMA5D28C_D1G, - AT91_SOC_SAMA5D28CU, AT91_SOC_SAMA5D28CN, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, - AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43, - AT91_SOC_SAMA5D44, - - /* Unknown subtype */ - AT91_SOC_SUBTYPE_NONE -}; - -struct at91_socinfo { - unsigned int type, subtype; - unsigned int cidr, exid; -}; - -extern struct at91_socinfo at91_soc_initdata; -const char *at91_get_soc_type(struct at91_socinfo *c); -const char *at91_get_soc_subtype(struct at91_socinfo *c); -extern unsigned long at91_bootsource; - -static inline int at91_soc_is_detected(void) -{ - return at91_soc_initdata.type != AT91_SOC_NONE; -} - -#ifdef CONFIG_SOC_AT91RM9200 -#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) -#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) -#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) -#else -#define cpu_is_at91rm9200() (0) -#define cpu_is_at91rm9200_bga() (0) -#define cpu_is_at91rm9200_pqfp() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9260 -#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) -#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#else -#define cpu_is_at91sam9xe() (0) -#define cpu_is_at91sam9260() (0) -#define cpu_is_at91sam9g20() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9261 -#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) -#else -#define cpu_is_at91sam9261() (0) -#define cpu_is_at91sam9g10() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9263 -#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) -#else -#define cpu_is_at91sam9263() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9RL -#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) -#else -#define cpu_is_at91sam9rl() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9G45 -#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) -#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) -#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) -#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) -#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) -#else -#define cpu_is_at91sam9g45() (0) -#define cpu_is_at91sam9g45es() (0) -#define cpu_is_at91sam9m10() (0) -#define cpu_is_at91sam9g46() (0) -#define cpu_is_at91sam9m11() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9X5 -#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) -#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) -#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) -#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) -#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) -#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) -#else -#define cpu_is_at91sam9x5() (0) -#define cpu_is_at91sam9g15() (0) -#define cpu_is_at91sam9g35() (0) -#define cpu_is_at91sam9x35() (0) -#define cpu_is_at91sam9g25() (0) -#define cpu_is_at91sam9x25() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9N12 -#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) -#else -#define cpu_is_at91sam9n12() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D2 -#define cpu_is_sama5d2() (at91_soc_initdata.type == AT91_SOC_SAMA5D2) -#define cpu_is_sama5d21() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D21CU) -#define cpu_is_sama5d22() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CN) -#define cpu_is_sama5d23() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D23CU) -#define cpu_is_sama5d24() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CX \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CU) -#define cpu_is_sama5d26() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D26CU) -#define cpu_is_sama5d27() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D1G \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D5M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CN) -#define cpu_is_sama5d28() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D28C_D1G \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CN) -#else -#define cpu_is_sama5d2() (0) -#define cpu_is_sama5d21() (0) -#define cpu_is_sama5d22() (0) -#define cpu_is_sama5d23() (0) -#define cpu_is_sama5d24() (0) -#define cpu_is_sama5d26() (0) -#define cpu_is_sama5d27() (0) -#define cpu_is_sama5d28() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D3 -#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) -#define cpu_is_sama5d31() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D31) -#define cpu_is_sama5d33() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D33) -#define cpu_is_sama5d34() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D34) -#define cpu_is_sama5d35() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D35) -#define cpu_is_sama5d36() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D36) -#else -#define cpu_is_sama5d3() (0) -#define cpu_is_sama5d31() (0) -#define cpu_is_sama5d33() (0) -#define cpu_is_sama5d34() (0) -#define cpu_is_sama5d35() (0) -#define cpu_is_sama5d36() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D4 -#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) -#define cpu_is_sama5d41() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D41) -#define cpu_is_sama5d42() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D42) -#define cpu_is_sama5d43() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D43) -#define cpu_is_sama5d44() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D44) -#else -#define cpu_is_sama5d4() (0) -#define cpu_is_sama5d41() (0) -#define cpu_is_sama5d42() (0) -#define cpu_is_sama5d43() (0) -#define cpu_is_sama5d44() (0) -#endif - -/* - * Since this is ARM, we will never run on any AVR32 CPU. But these - * definitions may reduce clutter in common drivers. - */ -#define cpu_is_at32ap7000() (0) -#endif /* __ASSEMBLY__ */ - -#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h deleted file mode 100644 index 7daef17636..0000000000 --- a/arch/arm/mach-at91/include/mach/ddramc.h +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Copyright (c) 2006, Atmel Corporation - */ -#ifndef __DDRAMC_H__ -#define __DDRAMC_H__ - -/* Note: reserved bits must always be zeroed */ -struct at91_ddramc_register { - unsigned long mdr; - unsigned long cr; - unsigned long rtr; - unsigned long t0pr; - unsigned long t1pr; - unsigned long t2pr; - unsigned long lpr; - unsigned long lpddr2_lpr; - unsigned long tim_calr; - unsigned long cal_mr4r; -}; - -void at91_ddram_initialize(void __iomem *base_address, - void __iomem *ram_address, - const struct at91_ddramc_register *ddramc_config); - -void at91_lpddr2_sdram_initialize(void __iomem *base_address, - void __iomem *ram_address, - const struct at91_ddramc_register *ddramc_config); - - -void at91_lpddr1_sdram_initialize(void __iomem *base_address, - void __iomem *ram_address, - const struct at91_ddramc_register *ddramc_config); - -void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata); -void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata); - -#endif /* #ifndef __DDRAMC_H__ */ diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h deleted file mode 100644 index b3cbdbc26f..0000000000 --- a/arch/arm/mach-at91/include/mach/debug_ll.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2012 - * Jean-Christophe PLAGNIOL-VILLARD <planioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#ifndef __MACH_DEBUG_LL_H__ -#define __MACH_DEBUG_LL_H__ - -#include <asm/io.h> -#include <mach/gpio.h> -#include <mach/hardware.h> -#include <mach/at91_dbgu.h> - -#define ATMEL_US_CSR 0x0014 -#define ATMEL_US_THR 0x001c -#define ATMEL_US_TXRDY (1 << 1) -#define ATMEL_US_TXEMPTY (1 << 9) - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static inline void at91_dbgu_putc(void __iomem *base, int c) -{ - while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXRDY)) - barrier(); - writel(c, base + ATMEL_US_THR); - - while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) - barrier(); -} - -static inline void PUTC_LL(char c) -{ - at91_dbgu_putc(IOMEM(CONFIG_DEBUG_AT91_UART_BASE), c); -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h b/arch/arm/mach-at91/include/mach/early_udelay.h deleted file mode 100644 index fc9885dd27..0000000000 --- a/arch/arm/mach-at91/include/mach/early_udelay.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __EARLY_UDELAY_H__ -#define __EARLY_UDELAY_H__ - -#include <linux/compiler.h> - -/* requires PIT to be initialized, but not the clocksource framework */ -void early_udelay(unsigned int usec); -void early_udelay_init(void __iomem *pmc_base, - void __iomem *pit_base, - unsigned int clock, - unsigned int master_clock_rate, - unsigned int flags); - -#endif diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h deleted file mode 100644 index ddd6971e37..0000000000 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 only - */ - -#ifndef __AT91_GPIO_H__ -#define __AT91_GPIO_H__ - -#include <dt-bindings/gpio/gpio.h> -#include <asm/io.h> -#include <mach/at91_pio.h> - -#define MAX_NB_GPIO_PER_BANK 32 - -enum at91_mux { - AT91_MUX_GPIO = 0, - AT91_MUX_PERIPH_A = 1, - AT91_MUX_PERIPH_B = 2, - AT91_MUX_PERIPH_C = 3, - AT91_MUX_PERIPH_D = 4, - AT91_MUX_PERIPH_E = 5, - AT91_MUX_PERIPH_F = 6, - AT91_MUX_PERIPH_G = 7, -}; - -static inline unsigned pin_to_bank(unsigned pin) -{ - return pin / MAX_NB_GPIO_PER_BANK; -} - -static inline unsigned pin_to_bank_offset(unsigned pin) -{ - return pin % MAX_NB_GPIO_PER_BANK; -} - -static inline unsigned pin_to_mask(unsigned pin) -{ - return 1 << pin_to_bank_offset(pin); -} - -static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_IDR); -} - -static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) -{ - writel(mask, pio + (on ? PIO_PUER : PIO_PUDR)); -} - -static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) -{ - writel(mask, pio + (on ? PIO_MDER : PIO_MDDR)); -} - -static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_ASR); -} - -static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_BSR); -} - -static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); -} - -static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - if (is_on) - writel(mask, pio + PIO_IFSCDR); - at91_mux_set_deglitch(pio, mask, is_on); -} - -static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - if (is_on) { - writel(mask, pio + PIO_IFSCER); - writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); - writel(mask, pio + PIO_IFER); - } else { - writel(mask, pio + PIO_IFDR); - } -} - -static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) -{ - writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); -} - -static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); -} - -static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_PDR); -} - -static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_PER); -} - -static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input) -{ - writel(mask, pio + (input ? PIO_ODR : PIO_OER)); -} - -static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask, -int value) -{ - writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); -} - -static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask) -{ - u32 pdsr; - - pdsr = readl(pio + PIO_PDSR); - return (pdsr & mask) != 0; -} - -static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask, - enum at91_mux mux, int gpio_state) -{ - at91_mux_disable_interrupt(pio, mask); - - switch(mux) { - case AT91_MUX_GPIO: - at91_mux_gpio_enable(pio, mask); - break; - case AT91_MUX_PERIPH_A: - at91_mux_pio3_set_A_periph(pio, mask); - break; - case AT91_MUX_PERIPH_B: - at91_mux_pio3_set_B_periph(pio, mask); - break; - case AT91_MUX_PERIPH_C: - at91_mux_pio3_set_C_periph(pio, mask); - break; - case AT91_MUX_PERIPH_D: - at91_mux_pio3_set_D_periph(pio, mask); - break; - default: - /* ignore everything else */ - break; - } - if (mux != AT91_MUX_GPIO) - at91_mux_gpio_disable(pio, mask); - - at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP); - at91_mux_pio3_set_pulldown(pio, mask, gpio_state & GPIO_PULL_DOWN); -} - -/* helpers for PIO4 pinctrl (>= sama5d2) */ - -static inline void at91_mux_pio4_set_periph(void __iomem *pio, unsigned mask, u32 func) -{ - writel(mask, pio + PIO4_MSKR); - writel(func, pio + PIO4_CFGR); -} - -static inline void at91_mux_pio4_set_A_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_A); -} - -static inline void at91_mux_pio4_set_B_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_B); -} - -static inline void at91_mux_pio4_set_C_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_C); -} - -static inline void at91_mux_pio4_set_D_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_D); -} - -static inline void at91_mux_pio4_set_E_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_E); -} - -static inline void at91_mux_pio4_set_F_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_F); -} - -static inline void at91_mux_pio4_set_G_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_G); -} - -static inline void at91_mux_pio4_set_func(void __iomem *pio, - unsigned pin_mask, - unsigned cfgr_and_mask, - unsigned cfgr_or_mask) -{ - u32 reg; - writel(pin_mask, pio + PIO4_MSKR); - reg = readl(pio + PIO4_CFGR); - reg &= cfgr_and_mask; - reg |= cfgr_or_mask; - writel(reg, pio + PIO4_CFGR); -} - -static inline void at91_mux_pio4_set_bistate(void __iomem *pio, - unsigned pin_mask, - unsigned func_mask, - bool is_on) -{ - at91_mux_pio4_set_func(pio, pin_mask, ~func_mask, - is_on ? func_mask : 0); -} - -static inline void at91_mux_pio4_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on); -} - -static inline void at91_mux_pio4_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on); - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFSCEN_MASK, is_on); -} - -static inline void at91_mux_pio4_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_PDEN_MASK, is_on); -} - -static inline void at91_mux_pio4_disable_schmitt_trig(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_SCHMITT_MASK, false); -} - -static inline void at91_mux_gpio4_enable(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_func(pio, mask, ~PIO4_CFGR_FUNC_MASK, AT91_MUX_GPIO); -} - -static inline void at91_mux_gpio4_input(void __iomem *pio, unsigned mask, bool input) -{ - u32 cfgr; - - writel(mask, pio + PIO4_MSKR); - - cfgr = readl(pio + PIO4_CFGR); - if (input) - cfgr &= ~PIO4_DIR_MASK; - else - cfgr |= PIO4_DIR_MASK; - writel(cfgr, pio + PIO4_CFGR); -} - -static inline void at91_mux_gpio4_set(void __iomem *pio, unsigned mask, - int value) -{ - writel(mask, pio + (value ? PIO4_SODR : PIO4_CODR)); -} - -static inline int at91_mux_gpio4_get(void __iomem *pio, unsigned mask) -{ - u32 pdsr; - - pdsr = readl(pio + PIO4_PDSR); - return (pdsr & mask) != 0; -} - -#endif /* __AT91_GPIO_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h deleted file mode 100644 index 0d08a99fe4..0000000000 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2003 SAN People */ -/* SPDX-FileCopyrightText: 2003 ATMEL */ - -/* [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* DBGU base */ -/* rm9200, 9260/9g20, 9261/9g10, 9rl */ -#define AT91_BASE_DBGU0 0xfffff200 -/* 9263, 9g45 */ -#define AT91_BASE_DBGU1 0xffffee00 -/* sama5d4 */ -#define AT91_BASE_DBGU2 0xfc069000 - -#include <mach/at91rm9200.h> -#include <mach/at91sam9260.h> -#include <mach/at91sam9261.h> -#include <mach/at91sam9263.h> -#include <mach/at91sam9g45.h> -#include <mach/at91sam9n12.h> -#include <mach/at91sam9x5.h> -#include <mach/sama5d2.h> -#include <mach/sama5d3.h> -#include <mach/sama5d4.h> - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -#define SAMA5_CHIPSELECT_0 0x10000000 -#define SAMA5_DDRCS 0x20000000 -#define SAMA5_CHIPSELECT_1 0x40000000 -#define SAMA5_CHIPSELECT_2 0x50000000 -#define SAMA5_CHIPSELECT_3 0x60000000 - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/iomux.h b/arch/arm/mach-at91/include/mach/iomux.h deleted file mode 100644 index bdd34bed94..0000000000 --- a/arch/arm/mach-at91/include/mach/iomux.h +++ /dev/null @@ -1,252 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* SPDX-FileCopyrightText: 2005 HP Labs */ - -/* [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] */ - -#ifndef __ASM_ARCH_AT91_GPIO_H -#define __ASM_ARCH_AT91_GPIO_H - -#include <io.h> -#include <asm-generic/errno.h> -#include <mach/at91_pio.h> -#include <mach/hardware.h> -#include <mach/gpio.h> - -#define AT91_PIN_PA0 (0x00 + 0) -#define AT91_PIN_PA1 (0x00 + 1) -#define AT91_PIN_PA2 (0x00 + 2) -#define AT91_PIN_PA3 (0x00 + 3) -#define AT91_PIN_PA4 (0x00 + 4) -#define AT91_PIN_PA5 (0x00 + 5) -#define AT91_PIN_PA6 (0x00 + 6) -#define AT91_PIN_PA7 (0x00 + 7) -#define AT91_PIN_PA8 (0x00 + 8) -#define AT91_PIN_PA9 (0x00 + 9) -#define AT91_PIN_PA10 (0x00 + 10) -#define AT91_PIN_PA11 (0x00 + 11) -#define AT91_PIN_PA12 (0x00 + 12) -#define AT91_PIN_PA13 (0x00 + 13) -#define AT91_PIN_PA14 (0x00 + 14) -#define AT91_PIN_PA15 (0x00 + 15) -#define AT91_PIN_PA16 (0x00 + 16) -#define AT91_PIN_PA17 (0x00 + 17) -#define AT91_PIN_PA18 (0x00 + 18) -#define AT91_PIN_PA19 (0x00 + 19) -#define AT91_PIN_PA20 (0x00 + 20) -#define AT91_PIN_PA21 (0x00 + 21) -#define AT91_PIN_PA22 (0x00 + 22) -#define AT91_PIN_PA23 (0x00 + 23) -#define AT91_PIN_PA24 (0x00 + 24) -#define AT91_PIN_PA25 (0x00 + 25) -#define AT91_PIN_PA26 (0x00 + 26) -#define AT91_PIN_PA27 (0x00 + 27) -#define AT91_PIN_PA28 (0x00 + 28) -#define AT91_PIN_PA29 (0x00 + 29) -#define AT91_PIN_PA30 (0x00 + 30) -#define AT91_PIN_PA31 (0x00 + 31) - -#define AT91_PIN_PB0 (0x20 + 0) -#define AT91_PIN_PB1 (0x20 + 1) -#define AT91_PIN_PB2 (0x20 + 2) -#define AT91_PIN_PB3 (0x20 + 3) -#define AT91_PIN_PB4 (0x20 + 4) -#define AT91_PIN_PB5 (0x20 + 5) -#define AT91_PIN_PB6 (0x20 + 6) -#define AT91_PIN_PB7 (0x20 + 7) -#define AT91_PIN_PB8 (0x20 + 8) -#define AT91_PIN_PB9 (0x20 + 9) -#define AT91_PIN_PB10 (0x20 + 10) -#define AT91_PIN_PB11 (0x20 + 11) -#define AT91_PIN_PB12 (0x20 + 12) -#define AT91_PIN_PB13 (0x20 + 13) -#define AT91_PIN_PB14 (0x20 + 14) -#define AT91_PIN_PB15 (0x20 + 15) -#define AT91_PIN_PB16 (0x20 + 16) -#define AT91_PIN_PB17 (0x20 + 17) -#define AT91_PIN_PB18 (0x20 + 18) -#define AT91_PIN_PB19 (0x20 + 19) -#define AT91_PIN_PB20 (0x20 + 20) -#define AT91_PIN_PB21 (0x20 + 21) -#define AT91_PIN_PB22 (0x20 + 22) -#define AT91_PIN_PB23 (0x20 + 23) -#define AT91_PIN_PB24 (0x20 + 24) -#define AT91_PIN_PB25 (0x20 + 25) -#define AT91_PIN_PB26 (0x20 + 26) -#define AT91_PIN_PB27 (0x20 + 27) -#define AT91_PIN_PB28 (0x20 + 28) -#define AT91_PIN_PB29 (0x20 + 29) -#define AT91_PIN_PB30 (0x20 + 30) -#define AT91_PIN_PB31 (0x20 + 31) - -#define AT91_PIN_PC0 (0x40 + 0) -#define AT91_PIN_PC1 (0x40 + 1) -#define AT91_PIN_PC2 (0x40 + 2) -#define AT91_PIN_PC3 (0x40 + 3) -#define AT91_PIN_PC4 (0x40 + 4) -#define AT91_PIN_PC5 (0x40 + 5) -#define AT91_PIN_PC6 (0x40 + 6) -#define AT91_PIN_PC7 (0x40 + 7) -#define AT91_PIN_PC8 (0x40 + 8) -#define AT91_PIN_PC9 (0x40 + 9) -#define AT91_PIN_PC10 (0x40 + 10) -#define AT91_PIN_PC11 (0x40 + 11) -#define AT91_PIN_PC12 (0x40 + 12) -#define AT91_PIN_PC13 (0x40 + 13) -#define AT91_PIN_PC14 (0x40 + 14) -#define AT91_PIN_PC15 (0x40 + 15) -#define AT91_PIN_PC16 (0x40 + 16) -#define AT91_PIN_PC17 (0x40 + 17) -#define AT91_PIN_PC18 (0x40 + 18) -#define AT91_PIN_PC19 (0x40 + 19) -#define AT91_PIN_PC20 (0x40 + 20) -#define AT91_PIN_PC21 (0x40 + 21) -#define AT91_PIN_PC22 (0x40 + 22) -#define AT91_PIN_PC23 (0x40 + 23) -#define AT91_PIN_PC24 (0x40 + 24) -#define AT91_PIN_PC25 (0x40 + 25) -#define AT91_PIN_PC26 (0x40 + 26) -#define AT91_PIN_PC27 (0x40 + 27) -#define AT91_PIN_PC28 (0x40 + 28) -#define AT91_PIN_PC29 (0x40 + 29) -#define AT91_PIN_PC30 (0x40 + 30) -#define AT91_PIN_PC31 (0x40 + 31) - -#define AT91_PIN_PD0 (0x60 + 0) -#define AT91_PIN_PD1 (0x60 + 1) -#define AT91_PIN_PD2 (0x60 + 2) -#define AT91_PIN_PD3 (0x60 + 3) -#define AT91_PIN_PD4 (0x60 + 4) -#define AT91_PIN_PD5 (0x60 + 5) -#define AT91_PIN_PD6 (0x60 + 6) -#define AT91_PIN_PD7 (0x60 + 7) -#define AT91_PIN_PD8 (0x60 + 8) -#define AT91_PIN_PD9 (0x60 + 9) -#define AT91_PIN_PD10 (0x60 + 10) -#define AT91_PIN_PD11 (0x60 + 11) -#define AT91_PIN_PD12 (0x60 + 12) -#define AT91_PIN_PD13 (0x60 + 13) -#define AT91_PIN_PD14 (0x60 + 14) -#define AT91_PIN_PD15 (0x60 + 15) -#define AT91_PIN_PD16 (0x60 + 16) -#define AT91_PIN_PD17 (0x60 + 17) -#define AT91_PIN_PD18 (0x60 + 18) -#define AT91_PIN_PD19 (0x60 + 19) -#define AT91_PIN_PD20 (0x60 + 20) -#define AT91_PIN_PD21 (0x60 + 21) -#define AT91_PIN_PD22 (0x60 + 22) -#define AT91_PIN_PD23 (0x60 + 23) -#define AT91_PIN_PD24 (0x60 + 24) -#define AT91_PIN_PD25 (0x60 + 25) -#define AT91_PIN_PD26 (0x60 + 26) -#define AT91_PIN_PD27 (0x60 + 27) -#define AT91_PIN_PD28 (0x60 + 28) -#define AT91_PIN_PD29 (0x60 + 29) -#define AT91_PIN_PD30 (0x60 + 30) -#define AT91_PIN_PD31 (0x60 + 31) - -#define AT91_PIN_PE0 (0x80 + 0) -#define AT91_PIN_PE1 (0x80 + 1) -#define AT91_PIN_PE2 (0x80 + 2) -#define AT91_PIN_PE3 (0x80 + 3) -#define AT91_PIN_PE4 (0x80 + 4) -#define AT91_PIN_PE5 (0x80 + 5) -#define AT91_PIN_PE6 (0x80 + 6) -#define AT91_PIN_PE7 (0x80 + 7) -#define AT91_PIN_PE8 (0x80 + 8) -#define AT91_PIN_PE9 (0x80 + 9) -#define AT91_PIN_PE10 (0x80 + 10) -#define AT91_PIN_PE11 (0x80 + 11) -#define AT91_PIN_PE12 (0x80 + 12) -#define AT91_PIN_PE13 (0x80 + 13) -#define AT91_PIN_PE14 (0x80 + 14) -#define AT91_PIN_PE15 (0x80 + 15) -#define AT91_PIN_PE16 (0x80 + 16) -#define AT91_PIN_PE17 (0x80 + 17) -#define AT91_PIN_PE18 (0x80 + 18) -#define AT91_PIN_PE19 (0x80 + 19) -#define AT91_PIN_PE20 (0x80 + 20) -#define AT91_PIN_PE21 (0x80 + 21) -#define AT91_PIN_PE22 (0x80 + 22) -#define AT91_PIN_PE23 (0x80 + 23) -#define AT91_PIN_PE24 (0x80 + 24) -#define AT91_PIN_PE25 (0x80 + 25) -#define AT91_PIN_PE26 (0x80 + 26) -#define AT91_PIN_PE27 (0x80 + 27) -#define AT91_PIN_PE28 (0x80 + 28) -#define AT91_PIN_PE29 (0x80 + 29) -#define AT91_PIN_PE30 (0x80 + 30) -#define AT91_PIN_PE31 (0x80 + 31) - -/* - * mux the pin - */ -int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup); - -/* - * mux the pin to the "GPIO" peripheral role. - */ -static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup); -} - -/* - * mux the pin to the "A" internal peripheral role. - */ -static inline int at91_set_A_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_A, use_pullup); -} - -/* - * mux the pin to the "B" internal peripheral role. - */ -static inline int at91_set_B_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_B, use_pullup); -} - -/* - * mux the pin to the "C" internal peripheral role. - */ -static inline int at91_set_C_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_C, use_pullup); -} - -/* - * mux the pin to the "C" internal peripheral role. - */ -static inline int at91_set_D_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_D, use_pullup); -} - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and - * configure it for an input. - */ -int at91_set_gpio_input(unsigned pin, int use_pullup); - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -int at91_set_gpio_output(unsigned pin, int value); - -/* - * enable/disable the glitch filter; mostly used with IRQ handling. - */ -int at91_set_deglitch(unsigned pin, int is_on); - -/* - * enable/disable the multi-driver; This is only valid for output and - * allows the output pin to run as an open collector output. - */ -int at91_set_multi_drive(unsigned pin, int is_on); - -extern int at91_set_debounce(unsigned pin, int is_on, int div); -extern int at91_set_pulldown(unsigned pin, int is_on); -extern int at91_disable_schmitt_trig(unsigned pin); - -#endif /* __ASM_ARCH_AT91SAM9_GPIO_H */ diff --git a/arch/arm/mach-at91/include/mach/matrix.h b/arch/arm/mach-at91/include/mach/matrix.h deleted file mode 100644 index 5dbfcfe414..0000000000 --- a/arch/arm/mach-at91/include/mach/matrix.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause */ -/* - * Copyright (c) 2013, Atmel Corporation - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - */ -#ifndef __MATRIX_H__ -#define __MATRIX_H__ - -#include <linux/compiler.h> - -void at91_matrix_write_protect_enable(void __iomem *matrix_base); -void at91_matrix_write_protect_disable(void __iomem *matrix_base); -void at91_matrix_configure_slave_security(void __iomem *matrix_base, - unsigned int slave, - unsigned int srtop_setting, - unsigned int srsplit_setting, - unsigned int ssr_setting); - -#endif /* #ifndef __MATRIX_H__ */ diff --git a/arch/arm/mach-at91/include/mach/sama5_bootsource.h b/arch/arm/mach-at91/include/mach/sama5_bootsource.h deleted file mode 100644 index 931e1f29c8..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5_bootsource.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AT91_SAMA5_BOOTSOURCE_H_ -#define AT91_SAMA5_BOOTSOURCE_H_ - -#include <errno.h> -#include <bootsource.h> -#include <linux/bitops.h> -#include <linux/bitfield.h> -#include <mach/hardware.h> - -/* Boot modes stored by BootROM in r4 */ -#define SAMA5_BOOTSOURCE_SPI 0 -#define SAMA5_BOOTSOURCE_MCI 1 -#define SAMA5_BOOTSOURCE_SMC 2 -#define SAMA5_BOOTSOURCE_TWI 3 -#define SAMA5_BOOTSOURCE_QSPI 4 -#define SAMA5_BOOTSOURCE_SAM_BA 7 - -#define SAMA5_BOOTSOURCE GENMASK(3, 0) -#define SAMA5_BOOTSOURCE_INSTANCE GENMASK(7, 4) - -static inline int sama5_bootsource(u32 reg) -{ - u32 dev = FIELD_GET(SAMA5_BOOTSOURCE, reg); - - switch(dev) { - case SAMA5_BOOTSOURCE_MCI: - return BOOTSOURCE_MMC; - case SAMA5_BOOTSOURCE_SPI: - return BOOTSOURCE_SPI_NOR; - case SAMA5_BOOTSOURCE_QSPI: - return BOOTSOURCE_SPI; - case SAMA5_BOOTSOURCE_SMC: - return BOOTSOURCE_NAND; - case SAMA5_BOOTSOURCE_SAM_BA: - return BOOTSOURCE_SERIAL; - } - return BOOTSOURCE_UNKNOWN; -} - -static inline int sama5_bootsource_instance(u32 reg) -{ - return FIELD_GET(SAMA5_BOOTSOURCE_INSTANCE, reg); -} - -#define __sama5d2_stashed_bootrom_r4 \ - (*(volatile u32 *)(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 0x4)) - -#define __sama5d3_stashed_bootrom_r4 \ - (*(volatile u32 *)(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 0x4)) - -static inline void __noreturn sama5_boot_xload(void __noreturn (*bb)(void), u32 r4) -{ - asm volatile("mov r4, %0" : : "r"(r4) : ); - asm volatile("bx %0" : : "r"(bb) : ); - __builtin_unreachable(); -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h deleted file mode 100644 index 6a75ac71fc..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause - * - * Copyright (C) 2014, Atmel Corporation - * - * SAMA5D27 System-in-Package DDRAMC configuration - */ - -#include <mach/at91_ddrsdrc.h> -#include <mach/ddramc.h> -#include <mach/sama5d2_ll.h> - -static inline void sama5d2_d1g_ddrconf(void) /* DDR2 1Gbit SDRAM */ -{ - const struct at91_ddramc_register conf = { - .mdr = AT91_DDRC2_DBW_16_BITS | AT91_DDRC2_MD_DDR2_SDRAM, - - .cr = AT91_DDRC2_NC_DDR10_SDR9 | AT91_DDRC2_NR_13 | - AT91_DDRC2_CAS_3 | AT91_DDRC2_DISABLE_RESET_DLL | - AT91_DDRC2_WEAK_STRENGTH_RZQ7 | AT91_DDRC2_ENABLE_DLL | - AT91_DDRC2_NB_BANKS_8 | AT91_DDRC2_NDQS_ENABLED | - AT91_DDRC2_DECOD_INTERLEAVED | AT91_DDRC2_UNAL_SUPPORTED, - - .rtr = 0x511, - - .t0pr = AT91_DDRC2_TRAS_(7) | AT91_DDRC2_TRCD_(3) | - AT91_DDRC2_TWR_(3) | AT91_DDRC2_TRC_(9) | - AT91_DDRC2_TRP_(3) | AT91_DDRC2_TRRD_(2) | - AT91_DDRC2_TWTR_(2) | AT91_DDRC2_TMRD_(2), - - .t1pr = AT91_DDRC2_TRFC_(22) | AT91_DDRC2_TXSNR_(23) | - AT91_DDRC2_TXSRD_(200) | AT91_DDRC2_TXP_(2), - - .t2pr = AT91_DDRC2_TXARD_(2) | AT91_DDRC2_TXARDS_(8) | - AT91_DDRC2_TRPA_(4) | AT91_DDRC2_TRTP_(2) | - AT91_DDRC2_TFAW_(8), - }; - - sama5d2_ddr2_init(&conf); -} diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h deleted file mode 100644 index 90b566ffc4..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Chip-specific header file for the SAMA5D2 family - * - * Copyright (c) 2015, Atmel Corporation - * Copyright (c) 2019 Ahmad Fatoum, Pengutronix - * - * Common definitions. - * Based on SAMA5D2 datasheet: - * http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-Sheet-DS60001476C.pdf - * - */ - -#ifndef SAMA5D2_H -#define SAMA5D2_H - -#include <asm/io.h> -#include <linux/sizes.h> -#include <linux/bitops.h> -#include <linux/bitfield.h> - -/* - * Peripheral identifiers/interrupts. (Table 18-9) - */ -#define SAMA5D2_ID_FIQ 0 /* FIQ Interrupt ID */ -/* 1 */ -#define SAMA5D2_ID_ARM 2 /* Performance Monitor Unit */ -#define SAMA5D2_ID_PIT 3 /* Periodic Interval Timer Interrupt */ -#define SAMA5D2_ID_WDT 4 /* Watchdog Timer Interrupt */ -#define SAMA5D2_ID_GMAC 5 /* Ethernet MAC */ -#define SAMA5D2_ID_XDMAC0 6 /* DMA Controller 0 */ -#define SAMA5D2_ID_XDMAC1 7 /* DMA Controller 1 */ -#define SAMA5D2_ID_ICM 8 /* Integrity Check Monitor */ -#define SAMA5D2_ID_AES 9 /* Advanced Encryption Standard */ -#define SAMA5D2_ID_AESB 10 /* AES bridge */ -#define SAMA5D2_ID_TDES 11 /* Triple Data Encryption Standard */ -#define SAMA5D2_ID_SHA 12 /* SHA Signature */ -#define SAMA5D2_ID_MPDDRC 13 /* MPDDR Controller */ -#define SAMA5D2_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ -#define SAMA5D2_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ -#define SAMA5D2_ID_SECUMOD 16 /* Secure Module */ -#define SAMA5D2_ID_HSMC 17 /* Multi-bit ECC interrupt */ -#define SAMA5D2_ID_PIOA 18 /* Parallel I/O Controller A */ -#define SAMA5D2_ID_FLEXCOM0 19 /* FLEXCOM0 */ -#define SAMA5D2_ID_FLEXCOM1 20 /* FLEXCOM1 */ -#define SAMA5D2_ID_FLEXCOM2 21 /* FLEXCOM2 */ -#define SAMA5D2_ID_FLEXCOM3 22 /* FLEXCOM3 */ -#define SAMA5D2_ID_FLEXCOM4 23 /* FLEXCOM4 */ -#define SAMA5D2_ID_UART0 24 /* UART0 */ -#define SAMA5D2_ID_UART1 25 /* UART1 */ -#define SAMA5D2_ID_UART2 26 /* UART2 */ -#define SAMA5D2_ID_UART3 27 /* UART3 */ -#define SAMA5D2_ID_UART4 28 /* UART4 */ -#define SAMA5D2_ID_TWI0 29 /* Two-wire Interface 0 */ -#define SAMA5D2_ID_TWI1 30 /* Two-wire Interface 1 */ -#define SAMA5D2_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ -#define SAMA5D2_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ -#define SAMA5D2_ID_SPI0 33 /* Serial Peripheral Interface 0 */ -#define SAMA5D2_ID_SPI1 34 /* Serial Peripheral Interface 1 */ -#define SAMA5D2_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ -#define SAMA5D2_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ -/* 37 */ -#define SAMA5D2_ID_PWM 38 /* Pulse Width Modulation Controller0 (ch. 0,1,2,3) */ -/* 39 */ -#define SAMA5D2_ID_ADC 40 /* Touch Screen ADC Controller */ -#define SAMA5D2_ID_UHPHS 41 /* USB Host High Speed */ -#define SAMA5D2_ID_UDPHS 42 /* USB Device High Speed */ -#define SAMA5D2_ID_SSC0 43 /* Serial Synchronous Controller 0 */ -#define SAMA5D2_ID_SSC1 44 /* Serial Synchronous Controller 1 */ -#define SAMA5D2_ID_LCDC 45 /* LCD Controller */ -#define SAMA5D2_ID_ISI 46 /* Image Sensor Interface */ -#define SAMA5D2_ID_TRNG 47 /* True Random Number Generator */ -#define SAMA5D2_ID_PDMIC 48 /* Pulse Density Modulation Interface Controller */ -#define SAMA5D2_ID_IRQ 49 /* IRQ Interrupt ID */ -#define SAMA5D2_ID_SFC 50 /* Fuse Controller */ -#define SAMA5D2_ID_SECURAM 51 /* Secure RAM */ -#define SAMA5D2_ID_QSPI0 52 /* QSPI0 */ -#define SAMA5D2_ID_QSPI1 53 /* QSPI1 */ -#define SAMA5D2_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ -#define SAMA5D2_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ -#define SAMA5D2_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ -#define SAMA5D2_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ -#define SAMA5D2_ID_PTC 58 /* Peripheral Touch Controller */ -#define SAMA5D2_ID_CLASSD 59 /* Audio Class D Amplifier */ -#define SAMA5D2_ID_SFR 60 /* Special Function Register */ -#define SAMA5D2_ID_SAIC 61 /* Secured Advanced Interrupt Controller */ -#define SAMA5D2_ID_AIC 62 /* Advanced Interrupt Controller */ -#define SAMA5D2_ID_L2CC 63 /* L2 Cache Controller */ -#define SAMA5D2_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ -#define SAMA5D2_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ -#define SAMA5D2_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ -#define SAMA5D2_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ -#define SAMA5D2_ID_PIOB 68 /* Parallel I/O Controller B */ -#define SAMA5D2_ID_PIOC 69 /* Parallel I/O Controller C */ -#define SAMA5D2_ID_PIOD 70 /* Parallel I/O Controller D */ -#define SAMA5D2_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 */ -#define SAMA5D2_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 */ -/* 73 */ -#define SAMA5D2_ID_SYS 74 /* System Controller Interrupt */ -#define SAMA5D2_ID_ACC 75 /* Analog Comparator */ -#define SAMA5D2_ID_RXLP 76 /* UART Low-Power */ -#define SAMA5D2_ID_SFRBU 77 /* Special Function Register BackUp */ -#define SAMA5D2_ID_CHIPID 78 /* Chip ID */ - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D2_BASE_LCDC IOMEM(0xf0000000) -#define SAMA5D2_BASE_XDMAC1 IOMEM(0xf0004000) -#define SAMA5D2_BASE_HXISI IOMEM(0xf0008000) -#define SAMA5D2_BASE_MPDDRC IOMEM(0xf000c000) -#define SAMA5D2_BASE_XDMAC0 IOMEM(0xf0010000) -#define SAMA5D2_BASE_PMC IOMEM(0xf0014000) -#define SAMA5D2_BASE_MATRIX64 IOMEM(0xf0018000) /* MATRIX0 */ -#define SAMA5D2_BASE_AESB IOMEM(0xf001c000) -#define SAMA5D2_BASE_QSPI0 IOMEM(0xf0020000) -#define SAMA5D2_BASE_QSPI1 IOMEM(0xf0024000) -#define SAMA5D2_BASE_SHA IOMEM(0xf0028000) -#define SAMA5D2_BASE_AES IOMEM(0xf002c000) - -#define SAMA5D2_BASE_SPI0 IOMEM(0xf8000000) -#define SAMA5D2_BASE_SSC0 IOMEM(0xf8004000) -#define SAMA5D2_BASE_GMAC IOMEM(0xf8008000) -#define SAMA5D2_BASE_TC0 IOMEM(0xf800c000) -#define SAMA5D2_BASE_TC1 IOMEM(0xf8010000) -#define SAMA5D2_BASE_HSMC IOMEM(0xf8014000) -#define SAMA5D2_BASE_PDMIC IOMEM(0xf8018000) -#define SAMA5D2_BASE_UART0 IOMEM(0xf801c000) -#define SAMA5D2_BASE_UART1 IOMEM(0xf8020000) -#define SAMA5D2_BASE_UART2 IOMEM(0xf8024000) -#define SAMA5D2_BASE_TWI0 IOMEM(0xf8028000) -#define SAMA5D2_BASE_PWMC IOMEM(0xf802c000) -#define SAMA5D2_BASE_SFR IOMEM(0xf8030000) -#define SAMA5D2_BASE_FLEXCOM0 IOMEM(0xf8034000) -#define SAMA5D2_BASE_FLEXCOM1 IOMEM(0xf8038000) -#define SAMA5D2_BASE_SAIC IOMEM(0xf803c000) -#define SAMA5D2_BASE_ICM IOMEM(0xf8040000) -#define SAMA5D2_BASE_SECURAM IOMEM(0xf8044000) -#define SAMA5D2_BASE_SYSC IOMEM(0xf8048000) -#define SAMA5D2_BASE_ACC IOMEM(0xf804a000) -#define SAMA5D2_BASE_SFC IOMEM(0xf804c000) -#define SAMA5D2_BASE_I2SC0 IOMEM(0xf8050000) -#define SAMA5D2_BASE_CAN0 IOMEM(0xf8054000) - -#define SAMA5D2_BASE_SPI1 IOMEM(0xfc000000) -#define SAMA5D2_BASE_SSC1 IOMEM(0xfc004000) -#define SAMA5D2_BASE_UART3 IOMEM(0xfc008000) -#define SAMA5D2_BASE_UART4 IOMEM(0xfc00c000) -#define SAMA5D2_BASE_FLEXCOM2 IOMEM(0xfc010000) -#define SAMA5D2_BASE_FLEXCOM3 IOMEM(0xfc014000) -#define SAMA5D2_BASE_FLEXCOM4 IOMEM(0xfc018000) -#define SAMA5D2_BASE_TRNG IOMEM(0xfc01c000) -#define SAMA5D2_BASE_AIC IOMEM(0xfc020000) -#define SAMA5D2_BASE_TWI1 IOMEM(0xfc028000) -#define SAMA5D2_BASE_UDPHS IOMEM(0xfc02c000) -#define SAMA5D2_BASE_ADC IOMEM(0xfc030000) - -#define SAMA5D2_BASE_PIOA IOMEM(0xfc038000) -#define SAMA5D2_BASE_MATRIX32 IOMEM(0xfc03c000) /* MATRIX1 */ -#define SAMA5D2_BASE_SECUMOD IOMEM(0xfc040000) -#define SAMA5D2_BASE_TDES IOMEM(0xfc044000) -#define SAMA5D2_BASE_CLASSD IOMEM(0xfc048000) -#define SAMA5D2_BASE_I2SC1 IOMEM(0xfc04c000) -#define SAMA5D2_BASE_CAN1 IOMEM(0xfc050000) -#define SAMA5D2_BASE_SFRBU IOMEM(0xfc05c000) -#define SAMA5D2_BASE_CHIPID IOMEM(0xfc069000) - -/* - * Address Memory Space - */ -#define SAMA5D2_BASE_INTERNAL_MEM IOMEM(0x00000000) -#define SAMA5D2_BASE_CS0 IOMEM(0x10000000) -#define SAMA5D2_BASE_DDRCS IOMEM(0x20000000) -#define SAMA5D2_BASE_DDRCS_AES IOMEM(0x40000000) -#define SAMA5D2_BASE_CS1 IOMEM(0x60000000) -#define SAMA5D2_BASE_CS2 IOMEM(0x70000000) -#define SAMA5D2_BASE_CS3 IOMEM(0x80000000) -#define SAMA5D2_BASE_QSPI0_AES_MEM IOMEM(0x90000000) -#define SAMA5D2_BASE_QSPI1_AES_MEM IOMEM(0x98000000) -#define SAMA5D2_BASE_SDHC0 IOMEM(0xa0000000) -#define SAMA5D2_BASE_SDHC1 IOMEM(0xb0000000) -#define SAMA5D2_BASE_NFC_CMD_REG IOMEM(0xc0000000) -#define SAMA5D2_BASE_QSPI0_MEM IOMEM(0xd0000000) -#define SAMA5D2_BASE_QSPI1_MEM IOMEM(0xd8000000) -#define SAMA5D2_BASE_PERIPH IOMEM(0xf0000000) - -/* - * Internal Memories - */ -#define SAMA5D2_BASE_ROM IOMEM(0x00000000) /* ROM */ -#define SAMA5D2_BASE_ECC_ROM IOMEM(0x00060000) /* ECC ROM */ -#define SAMA5D2_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */ -#define SAMA5D2_BASE_SRAM0 0x00200000 /* SRAM0 */ -#define SAMA5D2_BASE_SRAM1 0x00220000 /* SRAM1 */ -#define SAMA5D2_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */ -#define SAMA5D2_BASE_UHP_OHCI IOMEM(0x00400000) /* UHP OHCI */ -#define SAMA5D2_BASE_UHP_EHCI IOMEM(0x00500000) /* UHP EHCI */ -#define SAMA5D2_BASE_AXI_MATRIX IOMEM(0x00600000) /* AXI Maxtrix */ -#define SAMA5D2_BASE_DAP IOMEM(0x00700000) /* DAP */ -#define SAMA5D2_BASE_PTC IOMEM(0x00800000) /* PTC */ -#define SAMA5D2_BASE_L2CC IOMEM(0x00A00000) /* L2CC */ - -/* - * Other misc defines - */ -#define SAMA5D2_BASE_PMECC (SAMA5D2_BASE_HSMC + 0x70) -#define SAMA5D2_BASE_PMERRLOC (SAMA5D2_BASE_HSMC + 0x500) - -#define SAMA5D2_PMECC (SAMA5D2_BASE_PMECC - SAMA5D2_BASE_SYS) -#define SAMA5D2_PMERRLOC (SAMA5D2_BASE_PMERRLOC - SAMA5D2_BASE_SYS) - -#define SAMA5D2_BASE_PIOB (SAMA5D2_BASE_PIOA + 0x40) -#define SAMA5D2_BASE_PIOC (SAMA5D2_BASE_PIOB + 0x40) -#define SAMA5D2_BASE_PIOD (SAMA5D2_BASE_PIOC + 0x40) - -/* SYSC spawns */ -#define SAMA5D2_BASE_RSTC SAMA5D2_BASE_SYSC -#define SAMA5D2_BASE_SHDC (SAMA5D2_BASE_SYSC + 0x10) -#define SAMA5D2_BASE_PITC (SAMA5D2_BASE_SYSC + 0x30) -#define SAMA5D2_BASE_WDT (SAMA5D2_BASE_SYSC + 0x40) -#define SAMA5D2_BASE_SCKCR (SAMA5D2_BASE_SYSC + 0x50) -#define SAMA5D2_BASE_RTCC (SAMA5D2_BASE_SYSC + 0xb0) - -#define SAMA5D2_BASE_SMC (SAMA5D2_BASE_HSMC + 0x700) - -#define SAMA5D2_NUM_PIO 4 -#define SAMA5D2_NUM_TWI 2 - -/* AICREDIR Unlock Key */ -#define SAMA5D2_AICREDIR_KEY 0xB6D81C4D - -/* - * Matrix Slaves ID - */ -/* MATRIX0(H64MX) Matrix Slaves */ -/* Bridge from H64MX to AXIMX (Internal ROM, Cryto Library, PKCC RAM) */ -#define SAMA5D2_H64MX_SLAVE_BRIDGE_TO_AXIMX 0 -#define SAMA5D2_H64MX_SLAVE_PERI_BRIDGE 1 /* H64MX Peripheral Bridge */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_0 2 /* DDR2 Port0-AESOTF */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_1 3 /* DDR2 Port1 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_2 4 /* DDR2 Port2 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_3 5 /* DDR2 Port3 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_4 6 /* DDR2 Port4 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_5 7 /* DDR2 Port5 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_6 8 /* DDR2 Port6 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_7 9 /* DDR2 Port7 */ -#define SAMA5D2_H64MX_SLAVE_INTERNAL_SRAM 10 /* Internal SRAM 128K */ -#define SAMA5D2_H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K (Cache L2) */ -#define SAMA5D2_H64MX_SLAVE_QSPI0 12 /* QSPI0 */ -#define SAMA5D2_H64MX_SLAVE_QSPI1 13 /* QSPI1 */ -#define SAMA5D2_H64MX_SLAVE_AESB 14 /* AESB */ - -/* MATRIX1(H32MX) Matrix Slaves */ -#define SAMA5D2_H32MX_BRIDGE_TO_H64MX 0 /* Bridge from H32MX to H64MX */ -#define SAMA5D2_H32MX_PERI_BRIDGE_0 1 /* H32MX Peripheral Bridge 0 */ -#define SAMA5D2_H32MX_PERI_BRIDGE_1 2 /* H32MX Peripheral Bridge 1 */ -#define SAMA5D2_H32MX_EXTERNAL_EBI 3 /* External Bus Interface */ -#define SAMA5D2_H32MX_NFC_CMD_REG 3 /* NFC command Register */ -#define SAMA5D2_H32MX_NFC_SRAM 4 /* NFC SRAM */ -#define SAMA5D2_H32MX_USB 5 - -#define SAMA5D2_SRAM_BASE SAMA5D2_BASE_SRAM0 -#define SAMA5D2_SRAM_SIZE (128 * SZ_1K) - -static inline void __iomem *sama5d2_pio_map_bank(int bank, unsigned *id) -{ - switch(bank + 'A') { - case 'A': - *id = SAMA5D2_ID_PIOA; - return SAMA5D2_BASE_PIOA; - case 'B': - *id = SAMA5D2_ID_PIOB; - return SAMA5D2_BASE_PIOB; - case 'C': - *id = SAMA5D2_ID_PIOC; - return SAMA5D2_BASE_PIOC; - case 'D': - *id = SAMA5D2_ID_PIOD; - return SAMA5D2_BASE_PIOD; - } - - return NULL; -} - -#define SAMA5D2_BUREG_INDEX GENMASK(1, 0) -#define SAMA5D2_BUREG_VALID BIT(2) - -#define SAMA5D2_SFC_DR(x) (SAMA5D2_BASE_SFC + 0x20 + 4 * (x)) - -#define SAMA5D2_BOOTCFG_QSPI_0 GENMASK(1, 0) -#define SAMA5D2_BOOTCFG_QSPI_1 GENMASK(3, 2) -#define SAMA5D2_BOOTCFG_SPI_0 GENMASK(5, 4) -#define SAMA5D2_BOOTCFG_SPI_1 GENMASK(7, 6) -#define SAMA5D2_BOOTCFG_NFC GENMASK(9, 8) -#define SAMA5D2_BOOTCFG_SDMMC_0 BIT(10) -#define SAMA5D2_BOOTCFG_SDMMC_1 BIT(11) -#define SAMA5D2_BOOTCFG_UART GENMASK(15, 12) -#define SAMA5D2_BOOTCFG_JTAG GENMASK(17, 16) -#define SAMA5D2_BOOTCFG_EXT_MEM_BOOT_EN BIT(18) -#define SAMA5D2_BOOTCFG_QSPI_XIP BIT(21) -#define SAMA5D2_DISABLE_BSC_CR BIT(22) -#define SAMA5D2_DISABLE_MONITOR BIT(24) -#define SAMA5D2_SECURE_MODE BIT(29) - -static inline u32 sama5d2_bootcfg(void) -{ - u32 __iomem *bureg = SAMA5D2_BASE_SECURAM + 0x1400; - u32 bsc_cr = readl(SAMA5D2_BASE_SYSC + 0x54); - u32 __iomem *bootcfg; - - if (bsc_cr & SAMA5D2_BUREG_VALID) - bootcfg = &bureg[FIELD_GET(SAMA5D2_BUREG_INDEX, bsc_cr)]; - else - bootcfg = SAMA5D2_SFC_DR(512 / 32); - - return readl(bootcfg); -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2_ll.h b/arch/arm/mach-at91/include/mach/sama5d2_ll.h deleted file mode 100644 index c78279d7fc..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d2_ll.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_SAMA5D2_LL__ -#define __MACH_SAMA5D2_LL__ - -#include <mach/sama5d2.h> -#include <mach/at91_pmc_ll.h> -#include <mach/iomux.h> -#include <mach/debug_ll.h> -#include <mach/early_udelay.h> -#include <mach/ddramc.h> - -#include <common.h> - -void sama5d2_lowlevel_init(void); - -static inline void sama5d2_pmc_enable_periph_clock(int clk) -{ - at91_pmc_sam9x5_enable_periph_clock(SAMA5D2_BASE_PMC, clk); -} - -/* requires relocation */ -static inline void sama5d2_udelay_init(unsigned int msc) -{ - early_udelay_init(SAMA5D2_BASE_PMC, SAMA5D2_BASE_PITC, - SAMA5D2_ID_PIT, msc, AT91_PMC_LL_SAMA5D2); -} - - -void sama5d2_ddr2_init(const struct at91_ddramc_register *ddramc_reg_config); - -static inline int sama5d2_pmc_enable_generic_clock(unsigned int periph_id, - unsigned int clk_source, - unsigned int div) -{ - return at91_pmc_enable_generic_clock(SAMA5D2_BASE_PMC, - SAMA5D2_BASE_SFR, - periph_id, clk_source, div, - AT91_PMC_LL_SAMA5D2); -} - -static inline int sama5d2_dbgu_setup_ll(unsigned dbgu_id, - unsigned pin, unsigned periph, - unsigned mck) -{ - unsigned mask, bank, pio_id; - void __iomem *dbgu_base, *pio_base; - - mask = pin_to_mask(pin); - bank = pin_to_bank(pin); - - switch (dbgu_id) { - case SAMA5D2_ID_UART0: - dbgu_base = SAMA5D2_BASE_UART0; - break; - case SAMA5D2_ID_UART1: - dbgu_base = SAMA5D2_BASE_UART1; - break; - case SAMA5D2_ID_UART2: - dbgu_base = SAMA5D2_BASE_UART2; - break; - case SAMA5D2_ID_UART3: - dbgu_base = SAMA5D2_BASE_UART3; - break; - case SAMA5D2_ID_UART4: - dbgu_base = SAMA5D2_BASE_UART4; - break; - default: - return -EINVAL; - } - - pio_base = sama5d2_pio_map_bank(bank, &pio_id); - if (!pio_base) - return -EINVAL; - - sama5d2_pmc_enable_periph_clock(pio_id); - - at91_mux_pio4_set_periph(pio_base, mask, periph); - - sama5d2_pmc_enable_periph_clock(dbgu_id); - - at91_dbgu_setup_ll(dbgu_base, mck / 2, CONFIG_BAUDRATE); - - return 0; -} - -struct sama5d2_uart_pinmux { - void __iomem *base; - u8 id, dtxd, periph; -}; - -#define SAMA5D2_UART(idx, pio, periph) (struct sama5d2_uart_pinmux) { \ - SAMA5D2_BASE_UART##idx, SAMA5D2_ID_UART##idx, \ - AT91_PIN_##pio, AT91_MUX_PERIPH_##periph } - -static inline void __iomem *sama5d2_resetup_uart_console(unsigned mck) -{ - struct sama5d2_uart_pinmux pinmux; - - /* Table 48-2 I/O Lines and 16.4.4 Boot Configuration Word */ - - switch (FIELD_GET(SAMA5D2_BOOTCFG_UART, sama5d2_bootcfg())) { - case 0: /* UART_1_IOSET_1 */ - pinmux = SAMA5D2_UART(1, PD3, A); - break; - case 1: /* UART_0_IOSET_1 */ - pinmux = SAMA5D2_UART(0, PB27, C); - break; - case 2: /* UART_1_IOSET_2 */ - pinmux = SAMA5D2_UART(1, PC8, E); - break; - case 3: /* UART_2_IOSET_1 */ - pinmux = SAMA5D2_UART(2, PD5, B); - break; - case 4: /* UART_2_IOSET_2 */ - pinmux = SAMA5D2_UART(2, PD24, A); - break; - case 5: /* UART_2_IOSET_3 */ - pinmux = SAMA5D2_UART(2, PD20, C); - break; - case 6: /* UART_3_IOSET_1 */ - pinmux = SAMA5D2_UART(3, PC13, D); - break; - case 7: /* UART_3_IOSET_2 */ - pinmux = SAMA5D2_UART(3, PD0, C); - break; - case 8: /* UART_3_IOSET_3 */ - pinmux = SAMA5D2_UART(3, PB12, C); - break; - case 9: /* UART_4_IOSET_1 */ - pinmux = SAMA5D2_UART(4, PB4, A); - break; - default: - return NULL; - } - - sama5d2_dbgu_setup_ll(pinmux.id, pinmux.dtxd, pinmux.periph, mck); - return pinmux.base; -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h deleted file mode 100644 index 6f829282c6..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause - * - * Copyright (C) 2014, Atmel Corporation - * - * SAMA5D27 System-in-Package DDRAMC configuration - */ - -#include <mach/at91_ddrsdrc.h> -#include <mach/ddramc.h> -#include <mach/sama5d3_ll.h> - -static inline void sama5d3_xplained_ddrconf(void) -{ - const struct at91_ddramc_register conf = { - .mdr = AT91_DDRC2_DBW_32_BITS | AT91_DDRC2_MD_DDR2_SDRAM, - - .cr = AT91_DDRC2_NC_DDR10_SDR9 - | AT91_DDRC2_NR_13 - | AT91_DDRC2_CAS_3 - | AT91_DDRC2_DISABLE_RESET_DLL - | AT91_DDRC2_ENABLE_DLL - | AT91_DDRC2_ENRDM_ENABLE - | AT91_DDRC2_NB_BANKS_8 - | AT91_DDRC2_NDQS_DISABLED - | AT91_DDRC2_DECOD_INTERLEAVED - | AT91_DDRC2_UNAL_SUPPORTED, - - /* - * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us. - * With a 133 MHz frequency, the refresh timer count register must to be - * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824 - * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F. - */ - .rtr = 0x40F, /* Refresh timer: 7.812us */ - - /* One clock cycle @ 133 MHz = 7.5 ns */ - .t0pr = AT91_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */ - | AT91_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */ - | AT91_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */ - | AT91_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */ - | AT91_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */ - | AT91_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */ - | AT91_DDRC2_TWTR_(2) /* 2 clock cycles min */ - | AT91_DDRC2_TMRD_(2), /* 2 clock cycles */ - - .t1pr = AT91_DDRC2_TXP_(2) /* 2 clock cycles */ - | AT91_DDRC2_TXSRD_(200) /* 200 clock cycles */ - | AT91_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */ - | AT91_DDRC2_TRFC_(17), /* 17 * 7.5 = 127.5 ns */ - - .t2pr = AT91_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */ - | AT91_DDRC2_TRTP_(2) /* 2 clock cycles min */ - | AT91_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */ - | AT91_DDRC2_TXARDS_(8) /* = TXARD */ - | AT91_DDRC2_TXARD_(8), /* MR12 = 1 */ - }; - u32 reg; - - /* enable ddr2 clock */ - sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC); - at91_pmc_enable_system_clock(IOMEM(SAMA5D3_BASE_PMC), AT91CAP9_PMC_DDR); - - - /* Init the special register for sama5d3x */ - /* MPDDRC DLL Slave Offset Register: DDR2 configuration */ - reg = AT91_MPDDRC_S0OFF_1 - | AT91_MPDDRC_S2OFF_1 - | AT91_MPDDRC_S3OFF_1; - writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_SOR); - - /* MPDDRC DLL Master Offset Register */ - /* write master + clk90 offset */ - reg = AT91_MPDDRC_MOFF_7 - | AT91_MPDDRC_CLK90OFF_31 - | AT91_MPDDRC_SELOFF_ENABLED | AT91_MPDDRC_KEY; - writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_MOR); - - /* MPDDRC I/O Calibration Register */ - /* DDR2 RZQ = 50 Ohm */ - /* TZQIO = 4 */ - reg = AT91_MPDDRC_RDIV_DDR2_RZQ_50 - | AT91_MPDDRC_TZQIO_4; - writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR); - - /* DDRAM2 Controller initialize */ - at91_ddram_initialize(IOMEM(SAMA5D3_BASE_MPDDRC), IOMEM(SAMA5_DDRCS), - &conf); -} diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h deleted file mode 100644 index cd2102c20e..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D3 family - * - * Copyright (C) 2009-2012 Atmel Corporation. - * - * Common definitions. - * Based on SAMA5D3 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D3_H -#define SAMA5D3_H - -/* - * Peripheral identifiers/interrupts. - */ -#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ -#define SAMA5D3_ID_PIT 3 /* Periodic Interval Timer Interrupt */ -#define SAMA5D3_ID_WDT 4 /* Watchdog timer Interrupt */ -#define SAMA5D3_ID_HSMC5 5 /* Static Memory Controller */ -#define SAMA5D3_ID_PIOA 6 /* Parallel I/O Controller A */ -#define SAMA5D3_ID_PIOB 7 /* Parallel I/O Controller B */ -#define SAMA5D3_ID_PIOC 8 /* Parallel I/O Controller C */ -#define SAMA5D3_ID_PIOD 9 /* Parallel I/O Controller D */ -#define SAMA5D3_ID_PIOE 10 /* Parallel I/O Controller E */ -#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ -#define SAMA5D3_ID_USART0 12 /* USART0 */ -#define SAMA5D3_ID_USART1 13 /* USART1 */ -#define SAMA5D3_ID_USART2 14 /* USART2 */ -#define SAMA5D3_ID_USART3 15 /* USART3 */ -#define SAMA5D3_ID_UART0 16 /* UART0 */ -#define SAMA5D3_ID_UART1 17 /* UART1 */ -#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ -#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ -#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ -#define SAMA5D3_ID_HSMCI0 21 /* High Speed Multimedia Card Interface 0 */ -#define SAMA5D3_ID_HSMCI1 22 /* High Speed Multimedia Card Interface 1 */ -#define SAMA5D3_ID_HSMCI2 23 /* High Speed Multimedia Card Interface 2 */ -#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ -#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ -#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 (ch. 0, 1, 2) */ -#define SAMA5D3_ID_TC1 27 /* Timer Counter 1 (ch. 3, 4, 5) */ -#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ -#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ -#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ -#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ -#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ -#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ -#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ -#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ -#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ -#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ -#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ -#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ -#define SAMA5D3_ID_CAN0 40 /* CAN controller 0 */ -#define SAMA5D3_ID_CAN1 41 /* CAN controller 1 */ -#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ -#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ -#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ -#define SAMA5D3_ID_TRNG 45 /* True Random Number Generator */ -#define SAMA5D3_ID_ARM 46 /* Performance Monitor Unit */ -#define SAMA5D3_ID_AIC 47 /* Advanced Interrupt Controller */ -#define SAMA5D3_ID_FUSE 48 /* Fuse Controller */ -#define SAMA5D3_ID_MPDDRC 49 /* MPDDR controller */ - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D3_BASE_HSMCI0 0xf0000000 /* (MMCI) Base Address */ -#define SAMA5D3_BASE_SPI0 0xf0004000 -#define SAMA5D3_BASE_TC0 0xf0010000 /* (TC0) Base Address */ -#define SAMA5D3_BASE_TC1 0xf0010040 /* (TC1) Base Address */ -#define SAMA5D3_BASE_USART0 0xf001c000 -#define SAMA5D3_BASE_USART1 0xf0020000 -#define SAMA5D3_BASE_GMAC 0xf0028000 /* (GMAC) Base Address */ -#define SAMA5D3_BASE_LCDC 0xf0030000 /* (HLCDC5) Base Address */ -#define SAMA5D3_BASE_HSMCI1 0xf8000000 -#define SAMA5D3_BASE_HSMCI2 0xf8004000 -#define SAMA5D3_BASE_SPI1 0xf8008000 -#define SAMA5D3_BASE_EMAC 0xf802c000 /* (EMAC) Base Address */ -#define SAMA5D3_BASE_UDPHS 0xf8030000 - -#define SAMA5D3_BASE_PIOA 0xfffff200 -#define SAMA5D3_BASE_PIOB 0xfffff400 -#define SAMA5D3_BASE_PIOC 0xfffff600 -#define SAMA5D3_BASE_PIOD 0xfffff800 -#define SAMA5D3_BASE_PIOE 0xfffffa00 -#define SAMA5D3_BASE_MPDDRC 0xffffea00 -#define SAMA5D3_BASE_HSMC 0xffffc000 -#define SAMA5D3_BASE_RSTC 0xfffffe00 -#define SAMA5D3_BASE_PIT 0xfffffe30 -#define SAMA5D3_BASE_WDT 0xfffffe40 -#define SAMA5D3_BASE_PMC 0xfffffc00 -#define SAMA5D3_BASE_PMECC 0xffffc070 -#define SAMA5D3_BASE_PMERRLOC 0xffffc500 - -/* - * Internal Memory. - */ -#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ - -#define SAMA5D3_ROM_BASE 0x00100000 -#define SAMA5D3_ROM_SIZE SZ_1M - -#define SAMA5D3_UDPHS_FIFO 0x00500000 -#define SAMA5D3_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ -#define SAMA5D3_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3_ll.h b/arch/arm/mach-at91/include/mach/sama5d3_ll.h deleted file mode 100644 index b5b6b5d820..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d3_ll.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __SAMA5D3_LL_H__ -#define __SAMA5D3_LL_H__ - -#include <mach/at91_pmc_ll.h> -#include <mach/debug_ll.h> -#include <mach/early_udelay.h> - -void sama5d3_lowlevel_init(void); - -static inline void sama5d3_pmc_enable_periph_clock(int clk) -{ - at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk); -} - -/* requires relocation */ -static inline void sama5d3_udelay_init(unsigned int msc) -{ - early_udelay_init(IOMEM(SAMA5D3_BASE_PMC), IOMEM(SAMA5D3_BASE_PIT), - SAMA5D3_ID_PIT, msc, AT91_PMC_LL_SAMA5D3); -} - -#endif /* __SAMA5D3_LL_H__ */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h deleted file mode 100644 index 6d621e0111..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D4 family - * - * Copyright (C) 2014 Atmel Corporation, - * Bo Shen <voice.shen@atmel.com> - * - * Common definitions. - * Based on SAMA5D4 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D4_H -#define SAMA5D4_H - -/* - * Peripheral identifiers/interrupts. - */ -#define SAMA5D4_ID_PIT 3 -#define SAMA5D4_ID_WDT 4 -#define SAMA5D4_ID_PIOD 5 -#define SAMA5D4_ID_USART0 6 -#define SAMA5D4_ID_USART1 7 -#define SAMA5D4_ID_DMA0 8 -#define SAMA5D4_ID_ICM 9 -#define SAMA5D4_ID_PKCC 10 -#define SAMA5D4_ID_SCI 11 -#define SAMA5D4_ID_AES 12 -#define SAMA5D4_ID_AESB 13 -#define SAMA5D4_ID_TDES 14 -#define SAMA5D4_ID_SHA 15 -#define SAMA5D4_ID_MPDDRC 16 -#define SAMA5D4_ID_MATRIX1 17 -#define SAMA5D4_ID_MATRIX0 18 -#define SAMA5D4_ID_VDEC 19 -#define SAMA5D4_ID_SECUMOD 20 -#define SAMA5D4_ID_MSADCC 21 -#define SAMA5D4_ID_HSMC 22 -#define SAMA5D4_ID_PIOA 23 -#define SAMA5D4_ID_PIOB 24 -#define SAMA5D4_ID_PIOC 25 -#define SAMA5D4_ID_PIOE 26 -#define SAMA5D4_ID_UART0 27 -#define SAMA5D4_ID_UART1 28 -#define SAMA5D4_ID_USART2 29 -#define SAMA5D4_ID_USART3 30 -#define SAMA5D4_ID_USART4 31 -#define SAMA5D4_ID_TWI0 32 -#define SAMA5D4_ID_TWI1 33 -#define SAMA5D4_ID_TWI2 34 -#define SAMA5D4_ID_HSMCI0 35 -#define SAMA5D4_ID_HSMCI1 36 -#define SAMA5D4_ID_SPI0 37 -#define SAMA5D4_ID_SPI1 38 -#define SAMA5D4_ID_SPI2 39 -#define SAMA5D4_ID_TC0 40 -#define SAMA5D4_ID_TC1 41 -#define SAMA5D4_ID_TC2 42 -#define SAMA5D4_ID_PWM 43 -#define SAMA5D4_ID_ADC 44 -#define SAMA5D4_ID_DBGU 45 -#define SAMA5D4_ID_UHPHS 46 -#define SAMA5D4_ID_UDPHS 47 -#define SAMA5D4_ID_SSC0 48 -#define SAMA5D4_ID_SSC1 49 -#define SAMA5D4_ID_DMA1 50 -#define SAMA5D4_ID_LCDC 51 -#define SAMA5D4_ID_ISI 52 -#define SAMA5D4_ID_TRNG 53 -#define SAMA5D4_ID_GMAC0 54 -#define SAMA5D4_ID_IRQ 56 -#define SAMA5D4_ID_IRQ 56 -#define SAMA5D4_ID_SFC 57 -#define SAMA5D4_ID_SECURAM 59 -#define SAMA5D4_ID_CTB 60 -#define SAMA5D4_ID_SMD 61 -#define SAMA5D4_ID_TWI3 62 -#define SAMA5D4_ID_CATB 63 -#define SAMA5D4_ID_SFR 64 -#define SAMA5D4_ID_AIC 65 -#define SAMA5D4_ID_SAIC 66 -#define SAMA5D4_ID_L2CC 67 - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D4_BASE_LCDC 0xf0000000 /* (HLCDC5) Base Address */ -#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ -#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ -#define SAMA5D4_BASE_HSMCI0 0xf8000000 /* (MMCI0) Base Address */ -#define SAMA5D4_BASE_UART0 0xf8004000 /* (UART0) Base Address */ -#define SAMA5D4_BASE_SPI0 0xf8010000 /* (SPI0) Base Address */ -#define SAMA5D4_BASE_TC0 0xf801c000 /* (TC0) Base Address */ -#define SAMA5D4_BASE_GMAC0 0xf8020000 /* (GMAC0) Base Address */ -#define SAMA5D4_BASE_USART0 0xf802c000 /* (USART0) Base Address */ -#define SAMA5D4_BASE_USART1 0xf8030000 /* (USART1) Base Address */ -#define SAMA5D4_BASE_HSMCI1 0xfc000000 /* (HSMCI1) Base Address */ -#define SAMA5D4_BASE_UART1 0xfc004000 /* (UART1) Base Address */ -#define SAMA5D4_BASE_USART2 0xfc008000 /* (USART2) Base Address */ -#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3) Base Address */ -#define SAMA5D4_BASE_USART4 0xfc010000 /* (USART4) Base Address */ -#define SAMA5D4_BASE_SPI1 0xfc018000 /* (SPI1) Base Address */ -#define SAMA5D4_BASE_GMAC1 0xfc028000 /* (GMAC1) Base Address */ -#define SAMA5D4_BASE_HSMC 0xfc05c000 /* (HSMC) Base Address */ -#define SAMA5D4_BASE_PMECC 0xfc05c070 /* (PMECC) Base Address */ -#define SAMA5D4_BASE_PMERRLOC 0xfc05c500 /* (PMERRLOC) Base Address */ -#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ -#define SAMA5D4_BASE_RSTC 0xfc068600 -#define SAMA5D4_BASE_PIT 0xfc068630 /* (PIT) Base Address */ -#define SAMA5D4_BASE_DBGU 0xfc069000 /* (DBGU) Base Address */ -#define SAMA5D4_BASE_PIOA 0xfc06a000 /* (PIOA) Base Address */ -#define SAMA5D4_BASE_PIOB 0xfc06b000 /* (PIOB) Base Address */ -#define SAMA5D4_BASE_PIOC 0xfc06c000 /* (PIOC) Base Address */ -#define SAMA5D4_BASE_PIOE 0xfc06d000 /* (PIOE) Base Address */ -#define SAMA5D4_BASE_AIC 0xfc06e000 /* (AIC) Base Address */ - -#define SAMA5D4_CHIPSELECT_3 0x80000000 - -/* - * Internal Memory. - */ -#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/tz_matrix.h b/arch/arm/mach-at91/include/mach/tz_matrix.h deleted file mode 100644 index 85589bfa65..0000000000 --- a/arch/arm/mach-at91/include/mach/tz_matrix.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: BSD-1-Clause */ -/* - * Copyright (c) 2013, Atmel Corporation - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - */ -#ifndef __TZ_MATRIX_H__ -#define __TZ_MATRIX_H__ - -#define MATRIX_MCFG(n) (0x0000 + (n) * 4)/* Master Configuration Register */ -#define MATRIX_SCFG(n) (0x0040 + (n) * 4)/* Slave Configuration Register */ -#define MATRIX_PRAS(n) (0x0080 + (n) * 8)/* Priority Register A for Slave */ -#define MATRIX_PRBS(n) (0x0084 + (n) * 8)/* Priority Register B for Slave */ - -#define MATRIX_MRCR 0x0100 /* Master Remap Control Register */ -#define MATRIX_MEIER 0x0150 /* Master Error Interrupt Enable Register */ -#define MATRIX_MEIDR 0x0154 /* Master Error Interrupt Disable Register */ -#define MATRIX_MEIMR 0x0158 /* Master Error Interrupt Mask Register */ -#define MATRIX_MESR 0x015c /* Master Error Statue Register */ - -/* Master n Error Address Register */ -#define MATRIX_MEAR(n) (0x0160 + (n) * 4) - -#define MATRIX_WPMR 0x01E4 /* Write Protect Mode Register */ -#define MATRIX_WPSR 0x01E8 /* Write Protect Status Register */ - -/* Security Slave n Register */ -#define MATRIX_SSR(n) (0x0200 + (n) * 4) -/* Security Area Split Slave n Register */ -#define MATRIX_SASSR(n) (0x0240 + (n) * 4) -/* Security Region Top Slave n Register */ -#define MATRIX_SRTSR(n) (0x0280 + (n) * 4) - -/* Security Peripheral Select n Register */ -#define MATRIX_SPSELR(n) (0x02c0 + (n) * 4) - -/**************************************************************************/ -/* Write Protect Mode Register (MATRIX_WPMR) */ -#define MATRIX_WPMR_WPEN (1 << 0) /* Write Protect Enable */ -#define MATRIX_WPMR_WPEN_DISABLE (0 << 0) -#define MATRIX_WPMR_WPEN_ENABLE (1 << 0) -#define MATRIX_WPMR_WPKEY (PASSWD << 8) /* Write Protect KEY */ -#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154 << 8) - -/* Security Slave Registers (MATRIX_SSRx) */ -#define MATRIX_LANSECH(n, bit) ((bit) << n) -#define MATRIX_LANSECH_S(n) (0x00 << n) -#define MATRIX_LANSECH_NS(n) (0x01 << n) -#define MATRIX_RDNSECH(n, bit) ((bit) << (n + 8)) -#define MATRIX_RDNSECH_S(n) (0x00 << (n + 8)) -#define MATRIX_RDNSECH_NS(n) (0x01 << (n + 8)) -#define MATRIX_WRNSECH(n, bit) ((bit) << (n + 16)) -#define MATRIX_WRNSECH_S(n) (0x00 << (n + 16)) -#define MATRIX_WRNSECH_NS(n) (0x01 << (n + 16)) - -/* Security Areas Split Slave Registers (MATRIX_SASSRx) */ -#define MATRIX_SASPLIT(n, value) ((value) << (4 * n)) -#define MATRIX_SASPLIT_VALUE_4K 0x00 -#define MATRIX_SASPLIT_VALUE_8K 0x01 -#define MATRIX_SASPLIT_VALUE_16K 0x02 -#define MATRIX_SASPLIT_VALUE_32K 0x03 -#define MATRIX_SASPLIT_VALUE_64K 0x04 -#define MATRIX_SASPLIT_VALUE_128K 0x05 -#define MATRIX_SASPLIT_VALUE_256K 0x06 -#define MATRIX_SASPLIT_VALUE_512K 0x07 -#define MATRIX_SASPLIT_VALUE_1M 0x08 -#define MATRIX_SASPLIT_VALUE_2M 0x09 -#define MATRIX_SASPLIT_VALUE_4M 0x0a -#define MATRIX_SASPLIT_VALUE_8M 0x0b -#define MATRIX_SASPLIT_VALUE_16M 0x0c -#define MATRIX_SASPLIT_VALUE_32M 0x0d -#define MATRIX_SASPLIT_VALUE_64M 0x0e -#define MATRIX_SASPLIT_VALUE_128M 0x0f - -/* Security Region Top Slave Registers (MATRIX_SRTSRx) */ -#define MATRIX_SRTOP(n, value) ((value) << (4 * n)) -#define MATRIX_SRTOP_VALUE_4K 0x00 -#define MATRIX_SRTOP_VALUE_8K 0x01 -#define MATRIX_SRTOP_VALUE_16K 0x02 -#define MATRIX_SRTOP_VALUE_32K 0x03 -#define MATRIX_SRTOP_VALUE_64K 0x04 -#define MATRIX_SRTOP_VALUE_128K 0x05 -#define MATRIX_SRTOP_VALUE_256K 0x06 -#define MATRIX_SRTOP_VALUE_512K 0x07 -#define MATRIX_SRTOP_VALUE_1M 0x08 -#define MATRIX_SRTOP_VALUE_2M 0x09 -#define MATRIX_SRTOP_VALUE_4M 0x0a -#define MATRIX_SRTOP_VALUE_8M 0x0b -#define MATRIX_SRTOP_VALUE_16M 0x0c -#define MATRIX_SRTOP_VALUE_32M 0x0d -#define MATRIX_SRTOP_VALUE_64M 0x0e -#define MATRIX_SRTOP_VALUE_128M 0x0f - -#endif /* #ifndef __TZ_MATRIX_H__ */ diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h deleted file mode 100644 index e9336d59c9..0000000000 --- a/arch/arm/mach-at91/include/mach/xload.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_XLOAD_H -#define __MACH_XLOAD_H - -#include <linux/compiler.h> -#include <pbl.h> - -void __noreturn sama5d2_sdhci_start_image(u32 r4); -void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock, - unsigned int slot); - -int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base); -int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base, - unsigned int clock, unsigned int slot); - -#endif /* __MACH_XLOAD_H */ |