diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8m.c')
-rw-r--r-- | arch/arm/mach-imx/imx8m.c | 131 |
1 files changed, 29 insertions, 102 deletions
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d2ed7d52a9..52e42ee9ef 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -1,47 +1,31 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> +#include <linux/sizes.h> #include <io.h> #include <asm/syscounter.h> #include <asm/system.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/imx8mq.h> -#include <mach/imx8m-ccm-regs.h> -#include <mach/reset-reason.h> -#include <mach/ocotp.h> -#include <mach/imx8mq-regs.h> -#include <mach/imx8m-ccm-regs.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> +#include <linux/bitfield.h> #include <linux/iopoll.h> -#include <linux/arm-smccc.h> -#define FSL_SIP_BUILDINFO 0xC2000003 -#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +#define IMX_SIP_BUILDINFO 0xC2000003 +#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 void imx8m_clock_set_target_val(int clock_id, u32 val) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(val, ccm + IMX8M_CCM_TARGET_ROOTn(clock_id)); } void imx8m_ccgr_clock_enable(int index) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), ccm + IMX8M_CCM_CCGRn_SET(index)); @@ -49,85 +33,12 @@ void imx8m_ccgr_clock_enable(int index) void imx8m_ccgr_clock_disable(int index) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), ccm + IMX8M_CCM_CCGRn_CLR(index)); } -u64 imx8m_uid(void) -{ - return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR)); -} - -static int imx8m_init(const char *cputypestr) -{ - void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR); - struct arm_smccc_res res; - - /* - * Reset reasons seem to be identical to that of i.MX7 - */ - imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); - pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid()); - - if (IS_ENABLED(CONFIG_ARM_SMCCC) && - IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) { - arm_smccc_smc(FSL_SIP_BUILDINFO, - FSL_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0, 0, 0, 0, 0, &res); - pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0); - } - - return 0; -} - -int imx8mm_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MM_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mm_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MM: - cputypestr = "i.MX8MM"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision()); - - return imx8m_init(cputypestr); -} - -int imx8mq_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MQ_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mq_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MQ: - cputypestr = "i.MX8MQ"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision()); - - return imx8m_init(cputypestr); -} - #define INTPLL_DIV20_CLKE_MASK BIT(27) #define INTPLL_DIV10_CLKE_MASK BIT(25) #define INTPLL_DIV8_CLKE_MASK BIT(23) @@ -145,7 +56,7 @@ int imx8mq_init(void) #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114 -void imx8mm_early_clock_init(void) +static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */ { void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); @@ -188,9 +99,9 @@ void imx8mm_early_clock_init(void) IMX8M_CCM_TARGET_ROOTn_MUX(3)); imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); - /* Configure SYS_PLL3 to 750MHz */ + /* Configure SYS_PLL3 */ clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, - 750000000UL, 25000000UL); + pll3_freq, 25000000UL); clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), IMX8M_CCM_TARGET_ROOTn_MUX(7), @@ -213,6 +124,22 @@ void imx8mm_early_clock_init(void) FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0)); } +void imx8mm_early_clock_init(void) +{ + __imx8m_early_clock_init(750000000UL); +} + +void imx8mn_early_clock_init(void) +{ + __imx8m_early_clock_init(600000000UL); +} + +void imx8mp_early_clock_init(void) +{ + __imx8m_early_clock_init(750000000UL); +} + + #define KEEP_ALIVE 0x18 #define VER_L 0x1c #define VER_H 0x20 |