diff options
Diffstat (limited to 'arch/arm/mach-imx')
141 files changed, 5259 insertions, 25089 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6dd5cb2aca..6125813773 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,43 +1,6 @@ -if ARCH_IMX +# SPDX-License-Identifier: GPL-2.0-only -config ARCH_TEXT_BASE - hex - default 0x83f00000 if MACH_EUKREA_CPUIMX25 - default 0xa0000000 if MACH_EUKREA_CPUIMX27 - default 0x87f00000 if MACH_EUKREA_CPUIMX35 - default 0x97f00000 if MACH_EUKREA_CPUIMX51SD - default 0xc0000000 if MACH_IMX21ADS - default 0xa0000000 if MACH_IMX27ADS - default 0x83f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 - default 0x87f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR - default 0x87f00000 if MACH_FREESCALE_MX35_3STACK - default 0xa7f00000 if MACH_PCA100 - default 0xa0000000 if MACH_PCM038 - default 0x87f00000 if MACH_PCM037 - default 0x87f00000 if MACH_MX31MOBOARD - default 0x87f00000 if MACH_PCM043 - default 0xa7e00000 if MACH_NESO - default 0x97f00000 if MACH_FREESCALE_MX51_PDK - default 0x7ff00000 if MACH_FREESCALE_MX53_LOCO - default 0x7ff00000 if MACH_FREESCALE_MX53_SMD - default 0x7ff00000 if MACH_FREESCALE_MX53_VMX53 - default 0x87f00000 if MACH_GUF_CUPID - default 0x93d00000 if MACH_TX25 - default 0x7ff00000 if MACH_TQMA53 - default 0x97f00000 if MACH_TX51 - default 0x4fc00000 if MACH_SABRELITE - default 0x8fe00000 if MACH_TX53 - default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK - default 0x17800000 if MACH_SABRESD - default 0x4fc00000 if MACH_REALQ7 - default 0x4fc00000 if MACH_GK802 - default 0x87f00000 if MACH_KINDLE3 - default 0x2fc00000 if MACH_TQMA6X - default 0x4fc00000 if MACH_DFI_FS700_M60 - default 0x4fc00000 if MACH_UDOO - default 0x4fc00000 if MACH_VARISCITE_MX6 - default 0x4fc00000 if MACH_PHYTEC_SOM_IMX6 - default 0x9fc00000 if MACH_WARP7 +if ARCH_IMX config ARCH_IMX_IMXIMAGE bool @@ -64,10 +27,25 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND depends on MTD_WRITE default y +config USB_GADGET_DRIVER_ARC_PBL + bool + config RESET_IMX_SRC def_bool y depends on ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53 +config ARCH_IMX_ATF + def_bool y + depends on ARCH_IMX8M || ARCH_IMX9 + +config ARCH_IMX_ROMAPI + def_bool y + depends on ARCH_IMX8M || ARCH_IMX9 + +config ARCH_IMX_SCRATCHMEM + def_bool y + depends on ARCH_IMX8M || ARCH_IMX9 + # # PMIC configuration found on i.MX51 Babbadge board # @@ -77,7 +55,7 @@ config MACH_FREESCALE_MX51_PDK_POWER select DRIVER_SPI_IMX select MFD_MC13XXX -comment "Freescale i.MX System-on-Chip" +menu "i.MX boards" config ARCH_IMX1 bool @@ -146,7 +124,7 @@ config ARCH_IMX6 select ARCH_HAS_IMX_GPT select CPU_V7 select PINCTRL_IMX_IOMUX_V3 - select OFTREE + select OFDEVICE select COMMON_CLK_OF_PROVIDER select HW_HAS_PCI @@ -157,8 +135,6 @@ config ARCH_IMX6SL config ARCH_IMX6SX bool select ARCH_IMX6 - select OFTREE - select COMMON_CLK_OF_PROVIDER config ARCH_IMX6UL bool @@ -179,21 +155,45 @@ config ARCH_IMX8M select CPU_V8 select PINCTRL_IMX_IOMUX_V3 select OFTREE - select SYS_SUPPORTS_64BIT_KERNEL select COMMON_CLK_OF_PROVIDER select ARCH_HAS_FEC_IMX select HW_HAS_PCI select IMX8M_DRAM select PBL_VERIFY_PIGGY if HABV4 + select ARM_USE_COMPRESSED_DTB + select SOC_BUS + imply FSL_CAAM_RNG_PBL_INIT if HAVE_OPTEE config ARCH_IMX8MM select ARCH_IMX8M bool +config ARCH_IMX8MN + select ARCH_IMX8M + bool + +config ARCH_IMX8MP + select ARCH_IMX8M + bool + config ARCH_IMX8MQ select ARCH_IMX8M bool +config ARCH_IMX9 + select AHAB + bool + +config ARCH_IMX93 + bool + select ARCH_IMX9 + select CPU_V8 + select PINCTRL_IMX_IOMUX_V3 + select OFTREE + select COMMON_CLK_OF_PROVIDER + select ARM_USE_COMPRESSED_DTB + select ARCH_HAS_FEC_IMX + config ARCH_VF610 bool select ARCH_HAS_L2X0 @@ -208,11 +208,12 @@ config ARCH_VF610 select IMX_OCOTP # Needed for clock adjustement select CLOCKSOURCE_ARM_GLOBAL_TIMER -config IMX_MULTI_BOARDS - bool "Allow multiple boards to be selected" - select HAVE_PBL_MULTI_IMAGES +config MACH_ZII_COMMON + bool + +if 32BIT -if IMX_MULTI_BOARDS +comment "i.MX1 boards" config MACH_SCB9328 bool "Synertronixx scb9328" @@ -221,6 +222,8 @@ config MACH_SCB9328 help Say Y here if you are using the Synertronixx scb9328 board +comment "i.MX25 boards" + config MACH_TX25 bool "Ka-Ro TX25" select ARCH_IMX25 @@ -228,6 +231,8 @@ config MACH_TX25 help Say Y here if you are using the Ka-Ro tx25 board +comment "i.MX27 boards" + config MACH_PCA100 bool "phyCard-i.MX27" select ARCH_IMX27 @@ -247,6 +252,8 @@ config MACH_PCM038 Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped with a Freescale i.MX27 Processor +comment "i.MX50 boards" + config MACH_KINDLE_MX50 bool "i.MX50 based Amazon Kindle 4 and 5" select ARCH_IMX50 @@ -263,6 +270,8 @@ config MACH_KINDLE_MX50 Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or EY21 (Kindle Paperwhite). +comment "i.MX51 boards" + config MACH_CCMX51 bool "ConnectCore i.MX51" select ARCH_IMX51 @@ -270,7 +279,6 @@ config MACH_CCMX51 select SPI select DRIVER_SPI_IMX select MFD_MC13XXX - select RELOCATABLE help Say Y here if you are using Digi ConnectCore (W)i-i.MX51 equipped with a Freescale i.MX51 Processor @@ -284,17 +292,13 @@ config MACH_EFIKA_MX_SMARTBOOK help Choose this to compile barebox for the Efika MX Smartbook -config MACH_EMBEDSKY_E9 - bool "Embedsky E9 Mini-PC" - select ARCH_IMX6 - help - Choose this to compile barebox for the Embedsky E9 Mini PC - config MACH_FREESCALE_MX51_PDK bool "Freescale i.MX51 PDK" select ARCH_IMX51 select MACH_FREESCALE_MX51_PDK_POWER +comment "i.MX53 boards" + config MACH_CCMX53 bool "Digi ConnectCore i.MX53" select ARCH_IMX53 @@ -314,6 +318,12 @@ config MACH_GUF_VINCELL bool "Garz-Fricke Vincell" select ARCH_IMX53 +config MACH_TX53 + bool "Ka-Ro TX53" + select ARCH_IMX53 + help + Say Y here if you are using the Ka-Ro tx53 board + config MACH_TQMA53 bool "TQ i.MX53 TQMa53" select ARCH_IMX53 @@ -325,52 +335,63 @@ config MACH_FREESCALE_MX53_VMX53 Say Y here if you are using the Voipac Technologies X53-DMM-668 module equipped with a Freescale i.MX53 Processor -config MACH_TX53 - bool "Ka-Ro TX53" - select ARCH_IMX53 - help - Say Y here if you are using the Ka-Ro tx53 board +config MACH_ZII_RDU1 + bool "ZII i.MX51 RDU1" + select ARCH_IMX51 + select MACH_FREESCALE_MX51_PDK_POWER + select CRC8 + select MACH_ZII_COMMON + select ARM_USE_COMPRESSED_DTB -config MACH_PHYTEC_SOM_IMX6 - bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" - select ARCH_IMX6 - select ARCH_IMX6UL +comment "i.MX6 boards" -config MACH_KONTRON_SAMX6I - bool "Kontron sAMX6i" - select ARCH_IMX6 +config MACH_ADVANTECH_ROM_742X + bool "Advantech ROM 742X" + select ARCH_IMX6 + select ARM_USE_COMPRESSED_DTB -config MACH_DFI_FS700_M60 - bool "DFI i.MX6 FS700 M60 Q7 Board" +config MACH_NITROGEN6 + bool "BoundaryDevices Nitrogen6 boards" select ARCH_IMX6 -config MACH_GUF_SANTARO - bool "Garz+Fricke Santaro Board" +config MACH_CM_FX6 + bool "CM FX6" select ARCH_IMX6 - select I2C - select I2C_IMX + select MCI_IMX_ESDHC_PBL config MACH_REALQ7 bool "DataModul i.MX6Q Real Qseven Board" select ARCH_IMX6 -config MACH_GK802 - bool "Zealz GK802 Mini PC" +config MACH_DFI_FS700_M60 + bool "DFI i.MX6 FS700 M60 Q7 Board" select ARCH_IMX6 +config MACH_DIGI_CCIMX6ULSBCPRO + bool "Digi Internal CC-IMX6UL SBC Pro" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + config MACH_ELTEC_HIPERCAM bool "ELTEC HiPerCam" select ARCH_IMX6 -config MACH_TQMA6X - bool "TQ tqma6x on mba6x" +config MACH_EMBEDSKY_E9 + bool "Embedsky E9 Mini-PC" select ARCH_IMX6 + help + Choose this to compile barebox for the Embedsky E9 Mini PC -config MACH_TX6X - bool "Karo TX6x" +config MACH_EMBEST_MARSBOARD + bool "Embest MarSboard" select ARCH_IMX6 - select I2C - select I2C_IMX + select ARM_USE_COMPRESSED_DTB + +config MACH_EMBEST_RIOTBOARD + bool "Embest RIoTboard" + select ARCH_IMX6 + imply AT803X_PHY config MACH_SABRELITE bool "Freescale i.MX6 Sabre Lite" @@ -386,10 +407,75 @@ config MACH_FREESCALE_IMX6SX_SABRESDB select I2C select I2C_IMX -config MACH_NITROGEN6 - bool "BoundaryDevices Nitrogen6 boards" +config MACH_UDOO + bool "Freescale i.MX6 UDOO Board" select ARCH_IMX6 +config MACH_UDOO_NEO + bool "Freescale i.MX6 UDOO Neo Board (full variant)" + select ARCH_IMX6SX + +config MACH_GUF_SANTARO + bool "Garz+Fricke Santaro Board" + select ARCH_IMX6 + select I2C + select I2C_IMX + +config MACH_GW_VENTANA + bool "Gateworks Ventana SBC" + select ARCH_IMX6 + select I2C + select I2C_IMX + +config MACH_GRINN_LITEBOARD + bool "Grinn liteboard" + select ARCH_IMX6UL + +config MACH_TX6X + bool "Karo TX6x" + select ARCH_IMX6 + select I2C + select I2C_IMX + +config MACH_KONTRON_SAMX6I + bool "Kontron sAMX6i" + select ARCH_IMX6 + +config MACH_NOVENA + bool "Kosagi Novena board" + select ARCH_IMX6 + select ARM_USE_COMPRESSED_DTB + select DDR_SPD + select I2C_IMX_EARLY + select MCI_IMX_ESDHC_PBL + select USB_GADGET_DRIVER_ARC_PBL + +config MACH_NXP_IMX6ULL_EVK + bool "NXP i.MX6ull EVK Board" + select ARCH_IMX6UL + +config MACH_PHYTEC_SOM_IMX6 + bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" + select ARCH_IMX6 + select ARCH_IMX6UL + select I2C + select I2C_IMX + +config MACH_PROTONIC_IMX6 + bool "Protonic-Holland i.MX6 based boards" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + select IMX_OCOTP + +config MACH_SKOV_IMX6 + bool "Skov IMX6" + select ARCH_IMX6 + select ARM_USE_COMPRESSED_DTB + select MCI_IMX_ESDHC_PBL + select DSA + select DRIVER_NET_KSZ8873 + config MACH_SOLIDRUN_MICROSOM bool "SolidRun MicroSOM based devices" select ARCH_IMX6 @@ -406,22 +492,16 @@ config MACH_TECHNEXION_WANDBOARD select ARM_USE_COMPRESSED_DTB select MCI_IMX_ESDHC_PBL -config MACH_EMBEST_MARSBOARD - bool "Embest MarSboard" - select ARCH_IMX6 - select ARM_USE_COMPRESSED_DTB - -config MACH_EMBEST_RIOTBOARD - bool "Embest RIoTboard" - select ARCH_IMX6 - -config MACH_UDOO - bool "Freescale i.MX6 UDOO Board" +config MACH_TQMA6X + bool "TQ tqma6x on mba6x" select ARCH_IMX6 -config MACH_UDOO_NEO - bool "i.MX6 UDOO Neo Board (full variant)" - select ARCH_IMX6SX +config MACH_TQMA6UL + bool "TQ tqma6ul on mba6ulx" + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + select BOARD_TQ + select I2C_IMX_EARLY config MACH_VARISCITE_MX6 bool "Variscite i.MX6 Quad SOM" @@ -429,39 +509,14 @@ config MACH_VARISCITE_MX6 select I2C select I2C_IMX -config MACH_GW_VENTANA - bool "Gateworks Ventana SBC" - select ARCH_IMX6 - select I2C - select I2C_IMX - -config MACH_CM_FX6 - bool "CM FX6" - select ARCH_IMX6 - -config MACH_ADVANTECH_ROM_742X - bool "Advantech ROM 742X" - select ARCH_IMX6 +config MACH_WEBASTO_CCBV2 + bool "Webasto Common Communication Board V2" + select ARCH_IMX6UL select ARM_USE_COMPRESSED_DTB -config MACH_WARP7 - bool "NXP i.MX7: element 14 WaRP7 Board" - select ARCH_IMX7 - -config MACH_VF610_TWR - bool "Freescale VF610 Tower Board" - select ARCH_VF610 - -config MACH_ZII_COMMON - bool - -config MACH_ZII_RDU1 - bool "ZII i.MX51 RDU1" - select ARCH_IMX51 - select MACH_FREESCALE_MX51_PDK_POWER - select CRC8 - select MACH_ZII_COMMON - select ARM_USE_COMPRESSED_DTB +config MACH_GK802 + bool "Zealz GK802 Mini PC" + select ARCH_IMX6 config MACH_ZII_RDU2 bool "ZII i.MX6Q(+) RDU2" @@ -470,30 +525,21 @@ config MACH_ZII_RDU2 select MACH_ZII_COMMON select ARM_USE_COMPRESSED_DTB -config MACH_ZII_IMX8MQ_DEV - bool "ZII i.MX8MQ based devices" - select ARCH_IMX8MQ - select FIRMWARE_IMX_LPDDR4_PMU_TRAIN - select FIRMWARE_IMX8MQ_ATF - select ARM_SMCCC - select MCI_IMX_ESDHC_PBL - select MACH_ZII_COMMON - select ARM_USE_COMPRESSED_DTB +comment "i.MX7 boards" -config MACH_ZII_VF610_DEV - bool "ZII VF610 Dev Family" - select ARCH_VF610 - select CLKDEV_LOOKUP - select MACH_ZII_COMMON +config MACH_MEERKAT96 + bool "96Boards: i.MX7 Meerkat96" + select ARCH_IMX7 select ARM_USE_COMPRESSED_DTB -config MACH_ZII_IMX7D_DEV - bool "ZII i.MX7D based devices" +config MACH_AC_SXB + bool "Atlas Copco: SXB board" select ARCH_IMX7 + select MCI_IMX_ESDHC_PBL select ARM_USE_COMPRESSED_DTB -config MACH_PHYTEC_PHYCORE_IMX7 - bool "Phytec phyCORE i.MX7" +config MACH_WARP7 + bool "NXP i.MX7: element 14 WaRP7 Board" select ARCH_IMX7 config MACH_FREESCALE_MX7_SABRESD @@ -508,13 +554,95 @@ config MACH_FREESCALE_MX7_SABRESD https://goo.gl/6EKGdk -config MACH_NXP_IMX6ULL_EVK - bool "NXP i.MX6ull EVK Board" - select ARCH_IMX6UL +config MACH_PHYTEC_PHYCORE_IMX7 + bool "Phytec phyCORE i.MX7" + select ARCH_IMX7 + +config MACH_VARISCITE_SOM_MX7 + bool "Variscite VAR-SOM-MX7" + select ARCH_IMX7 + select ARM_USE_COMPRESSED_DTB + help + Support for boards that use a Variscite SOM-MX7, like: + - Gossen Metrawatt e143_01 + +config MACH_ZII_IMX7D_DEV + bool "ZII i.MX7D based devices" + select ARCH_IMX7 + select ARM_USE_COMPRESSED_DTB + +config MACH_KAMSTRUP_MX7_CONCENTRATOR + bool "Kamstrup i.MX7 Concentrator" + select ARCH_IMX7 + select ARM_USE_COMPRESSED_DTB + +comment "VF610 boards" + +config MACH_VF610_TWR + bool "Freescale VF610 Tower Board" + select ARCH_VF610 + +config MACH_ZII_VF610_DEV + bool "ZII VF610 Dev Family" + select ARCH_VF610 + select MACH_ZII_COMMON + select ARM_USE_COMPRESSED_DTB + +endif + +if 64BIT + +comment "i.MX8M boards" + +config MACH_CONGATEC_QMX8P_SOM + bool + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + +config MACH_KOENIGBAUER_ALPHAJET + bool "Koenig+Bauer AlphaJet" + select MACH_CONGATEC_QMX8P_SOM + +config MACH_INNOCOMM_WB15 + bool "InnoComm WB15 (i.MX8MM) EVK" + select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MM_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + select USB_GADGET_DRIVER_ARC_PBL + imply AT803X_PHY + +config MACH_KARO_QSXP_ML81 + bool "Karo QSXP ML81 (i.MX8MP) SOM on QSBASE4 Board" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + +config MACH_MNT_REFORM + bool "MNT Reform" + select ARCH_IMX8MQ + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MQ_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select I2C_IMX_EARLY config MACH_NXP_IMX8MM_EVK bool "NXP i.MX8MM EVK Board" select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN select FIRMWARE_IMX8MM_ATF select ARM_SMCCC select MCI_IMX_ESDHC_PBL @@ -522,6 +650,27 @@ config MACH_NXP_IMX8MM_EVK select I2C_IMX_EARLY select USB_GADGET_DRIVER_ARC_PBL +config MACH_NXP_IMX8MN_EVK + bool "NXP i.MX8MN EVK Board" + select ARCH_IMX8MN + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX_DDR4_PMU_TRAIN + select FIRMWARE_IMX8MN_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + +config MACH_NXP_IMX8MP_EVK + bool "NXP i.MX8MP EVK Board" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + config MACH_NXP_IMX8MQ_EVK bool "NXP i.MX8MQ EVK Board" select ARCH_IMX8MQ @@ -530,6 +679,19 @@ config MACH_NXP_IMX8MQ_EVK select ARM_SMCCC select MCI_IMX_ESDHC_PBL +config MACH_PHYTEC_SOM_IMX8MM + bool "Phytec i.MX8MM SOM" + select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MM_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + select USB_GADGET_DRIVER_ARC_PBL + select BOARD_PHYTEC_SOM_IMX8M_DETECTION + imply AT803X_PHY + config MACH_PHYTEC_SOM_IMX8MQ bool "Phytec i.MX8M SOM" select ARCH_IMX8MQ @@ -538,249 +700,85 @@ config MACH_PHYTEC_SOM_IMX8MQ select ARM_SMCCC select MCI_IMX_ESDHC_PBL -config MACH_GRINN_LITEBOARD - bool "Grinn liteboard" - select ARCH_IMX6UL - -config MACH_DIGI_CCIMX6ULSBCPRO - bool "Digi Internal CC-IMX6UL SBC Pro" - select ARCH_IMX6 - select ARCH_IMX6UL - select ARM_USE_COMPRESSED_DTB - -endif - -# ---------------------------------------------------------- - -choice - prompt "Select Board" - depends on !IMX_MULTI_BOARDS - -# ---------------------------------------------------------- - -comment "i.MX21 Boards" - -config MACH_IMX21ADS - bool "Freescale i.MX21ADS" - select ARCH_IMX21 - select HAS_CS8900 - help - Say Y here if you are using the Freescale i.MX21ads board equipped - with a Freescale i.MX21 Processor - -# ---------------------------------------------------------- - -comment "i.MX25 Boards" - -config MACH_EUKREA_CPUIMX25 - bool "Eukrea CPUIMX25" - select ARCH_IMX25 - help - Say Y here if you are using the Eukrea Electromatique's CPUIMX25 - equipped with a Freescale i.MX25 Processor - -config MACH_FREESCALE_MX25_3STACK - bool "Freescale MX25 3stack" - select ARCH_IMX25 - select I2C - select MFD_MC34704 - help - Say Y here if you are using the Freescale MX25 3stack board equipped - with a Freescale i.MX25 Processor - -# ---------------------------------------------------------- - -comment "i.MX27 Boards" - -config MACH_EUKREA_CPUIMX27 - bool "EUKREA CPUIMX27" - select ARCH_IMX27 - help - Say Y here if you are using Eukrea's CPUIMX27 equipped - with a Freescale i.MX27 Processor - -config MACH_IMX27ADS - bool "Freescale i.MX27ADS" - select ARCH_IMX27 - help - Say Y here if you are using the Freescale i.MX27ads board equipped - with a Freescale i.MX27 Processor - -config MACH_NESO - bool "Garz+Fricke Neso" - select ARCH_IMX27 +config MACH_POLYHEX_DEBIX + bool "Polyhex DEBIX i.MX8MP Boards" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY help - Say Y here if you are using the Garz+Fricke Neso board equipped - with a Freescale i.MX27 Processor - -# ---------------------------------------------------------- + Support for DEBIX Model-A/B and SOM A + SOM A I/O board -comment "i.MX31 Boards" +config MACH_PROTONIC_IMX8M + bool "Protonic-Holland i.MX8Mx based boards" + select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MM_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select USB_GADGET_DRIVER_ARC_PBL -config MACH_PCM037 - bool "phyCORE-i.MX31" - select ARCH_IMX31 - select USB_ULPI if USB - select ARCH_HAS_L2X0 - help - Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped - with a Freescale i.MX31 Processor +config MACH_SKOV_IMX8MP + bool "Skov i.MX8MP based boards" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY -config MACH_MX31MOBOARD - bool "mx31moboard-i.MX31" - select ARCH_IMX31 - select USB_ULPI if USB - select ARCH_HAS_L2X0 - help - Say Y here if you are using EPFL mx31moboard board equipped - with a Freescale i.MX31 Processor +config MACH_TQ_MBA8MPXL + bool "TQ i.MX8MP Dual/Quad on MBa8MPxL Board" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY -# ---------------------------------------------------------- +config MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP + bool "Variscite DT8MCustomBoard with DART-MX8M-PLUS" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY -comment "i.MX35 Boards" +config MACH_ZII_IMX8MQ_DEV + bool "ZII i.MX8MQ based devices" + select ARCH_IMX8MQ + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MQ_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select MACH_ZII_COMMON -config MACH_EUKREA_CPUIMX35 - bool "EUKREA CPUIMX35" - select ARCH_IMX35 - select ARCH_HAS_L2X0 - help - Say Y here if you are using Eukrea's CPUIMX35 equipped - with a Freescale i.MX35 Processor +comment "i.MX93 boards" -config MACH_FREESCALE_MX35_3STACK - bool "Freescale MX35 3stack" - select ARCH_IMX35 +config MACH_TQMA93XX + bool "TQ i.MX93 on TQMA93XX Board" + select ARCH_IMX93 + select IMX9_DRAM + select BOARD_TQ select I2C - select I2C_IMX - select MFD_MC13XXX - select MFD_MC9SDZ60 - help - Say Y here if you are using the Freescale MX35 3stack board equipped - with a Freescale i.MX35 Processor - -config MACH_PCM043 - bool "phyCORE-i.MX35" - select ARCH_IMX35 - select ARCH_HAS_L2X0 - help - Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped - with a Freescale i.MX35 Processor - -config MACH_GUF_CUPID - bool "Garz+Fricke Cupid" - select ARCH_IMX35 - select ARCH_HAS_L2X0 - help - Say Y here if you are using the Garz+Fricke Neso board equipped - with a Freescale i.MX35 Processor - -config MACH_KINDLE3 - bool "Amazon Kindle3" - select ARCH_IMX35 - select ARCH_HAS_L2X0 - help - Say Y here if you are using the Amazon Model No. D00901 Kindle - -# ---------------------------------------------------------- - -comment "i.MX51 Boards" - -config MACH_EUKREA_CPUIMX51SD - bool "EUKREA CPUIMX51" - select ARCH_IMX51 - help - Say Y here if you are using Eukrea's CPUIMX51 equipped - with a Freescale i.MX51 Processor - -config MACH_TX51 - bool "Ka-Ro TX51" - select ARCH_IMX51 - help - Say Y here if you are using the Ka-Ro tx51 board - -# ---------------------------------------------------------- - -comment "i.MX53 Boards" - -config MACH_FREESCALE_MX53_SMD - bool "Freescale i.MX53 SMD" - select ARCH_IMX53 - -endchoice - -# ---------------------------------------------------------- - -menu "Board specific settings" - -if MACH_PCM037 - -choice - prompt "SDRAM Bank0" -config PCM037_SDRAM_BANK0_128MB - bool "128MB" -config PCM037_SDRAM_BANK0_256MB - bool "256MB" -endchoice - -choice - prompt "SDRAM Bank1" -config PCM037_SDRAM_BANK1_NONE - bool "none" -config PCM037_SDRAM_BANK1_128MB - bool "128MB" -config PCM037_SDRAM_BANK1_256MB - bool "256MB" -endchoice - -endif - -if MACH_EUKREA_CPUIMX27 - -choice - prompt "SDRAM Size" -config EUKREA_CPUIMX27_SDRAM_128MB - bool "128 MB" -config EUKREA_CPUIMX27_SDRAM_256MB - bool "256 MB" -endchoice - -choice - prompt "NOR Flash Size" -config EUKREA_CPUIMX27_NOR_32MB - bool "<= 32 MB" -config EUKREA_CPUIMX27_NOR_64MB - bool "> 32 MB" -endchoice - -choice - prompt "Quad UART Port" - depends on DRIVER_SERIAL_NS16550 -config EUKREA_CPUIMX27_QUART1 - bool "Q1" -config EUKREA_CPUIMX27_QUART2 - bool "Q2" -config EUKREA_CPUIMX27_QUART3 - bool "Q3" -config EUKREA_CPUIMX27_QUART4 - bool "Q4" -endchoice - -endif - -if MACH_FREESCALE_MX25_3STACK - -choice - prompt "SDRAM Type" -config FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 - bool "64 MB (DDR2)" -config FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR - bool "128 MB (mDDR)" -endchoice + select I2C_IMX_LPI2C + select FIRMWARE_IMX93_ATF + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN endif endmenu +# ---------------------------------------------------------- + menu "i.MX specific settings" config IMX_IIM @@ -810,18 +808,32 @@ config IMX_IIM_FUSE_BLOW enable it: imx_iim0.permanent_write_enable=1 +config IMX_SAVE_BOOTROM_LOG + bool + default CMD_BOOTROM + config HAB bool +config AHAB + bool + select HAB + config HABV4 tristate "HABv4 support" select HAB select NVMEM select IMX_OCOTP - depends on ARCH_IMX6 || ARCH_IMX8MQ + depends on ARCH_IMX6 || ARCH_IMX8M depends on OFDEVICE help - High Assurance Boot, as found on i.MX28/i.MX6/i.MX8MQ. + High Assurance Boot, as found on i.MX28/i.MX6/i.MX8M. + +config HABV4_QSPI + depends on HABV4 + bool "HABv4 QPSI support" + help + Enable this option to build signed QSPI/FlexSPI images. config HAB_CERTS_ENV depends on HAB @@ -894,11 +906,13 @@ if HABV4 config HABV4_IMAGE_SIGNED bool "build signed images" help - enable the creation of a signed image, if the habv4-imx6-gencsf.h - included in the flash-header and the NXP cst Tool is available + enable the creation of a signed image, if the habv4-imx*-gencsf.h + file appropriate for the SoC is included in the flash-header and + the NXP cst Tool is available config HABV4_IMAGE_SIGNED_USB bool "build signed USB images" + depends on ARCH_IMX6 help enable the creation of a usb signed image, if the habv4-imx6-gencsf.h included in the flash-header and the NXP cst Tool is available @@ -906,8 +920,9 @@ config HABV4_IMAGE_SIGNED_USB config HABV4_IMAGE_SIGNED_ENCRYPTED bool "build signed encrypted images" help - enable the creation of the encrypted image, if the habv4-imx6-gencsf.h - included in the flash-header and the NXP cst Tool is available + enable the creation of the encrypted image, if the habv4-imx*-gencsf.h + file appropriate for the SoC is included in the flash-header and + the NXP cst Tool is available endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e45f758e9c..a2d9702bf4 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_ARCH_IMX1) += imx1.o obj-$(CONFIG_ARCH_IMX25) += imx25.o obj-$(CONFIG_ARCH_IMX21) += imx21.o @@ -16,14 +18,23 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o obj-pbl-$(CONFIG_ARCH_IMX8M) += imx8m.o -lwl-$(CONFIG_ARCH_IMX8M) += atf.o +obj-pbl-$(CONFIG_ARCH_IMX_SCRATCHMEM) += scratch.o +obj-$(CONFIG_ARCH_IMX9) += imx9.o +lwl-$(CONFIG_ARCH_IMX_ATF) += atf.o +obj-pbl-$(CONFIG_ARCH_IMX8M) += tzasc.o +obj-pbl-$(CONFIG_ARCH_IMX_ROMAPI) += romapi.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o obj-y += devices.o imx.o -obj-pbl-y += esdctl.o boot.o +obj-$(CONFIG_CMD_BOOTROM) += bootrom-cmd.o +obj-pbl-y += esdctl.o boot.o imx.o obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o +pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o obj-$(CONFIG_RESET_IMX_SRC) += src.o lwl-y += cpu_init.o -pbl-y += xload-spi.o xload-common.o xload-imx-nand.o +pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o +pbl-y += xload-qspi.o +obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o +obj-pbl-$(CONFIG_ARCH_IMX9) += imx93-trdc.o diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c index 4ced8cd083..8b80460268 100644 --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -1,5 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/sections.h> #include <common.h> -#include <mach/atf.h> +#include <firmware.h> +#include <mach/imx/atf.h> +#include <mach/imx/generic.h> +#include <mach/imx/xload.h> +#include <mach/imx/romapi.h> +#include <mach/imx/esdctl.h> +#include <asm-generic/memory_layout.h> +#include <asm/barebox-arm.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/imx9-regs.h> +#include <soc/fsl/fsl_udc.h> +#include <soc/fsl/caam.h> +#include <tee/optee.h> +#include <mach/imx/ele.h> /** * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it @@ -11,28 +27,29 @@ * This function: * * 1. Copies built-in BL31 blob to an address i.MX8M's BL31 - * expects to be placed + * expects to be placed (TF-A v2.8+ is position-independent) * * 2. Sets up temporary stack pointer for EL2, which is execution * level that BL31 will drop us off at after it completes its * initialization routine * * 3. Transfers control to BL31 - * - * NOTE: This function expects NXP's implementation of ATF that can be - * found at: - * https://source.codeaurora.org/external/imx/imx-atf - * - * any other implementation may or may not work - * */ -static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest) +static __noreturn void imx8m_atf_start_bl31(const void *fw, size_t fw_size, void *atf_dest) { void __noreturn (*bl31)(void) = atf_dest; + int ret; - if (WARN_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT)) - return; + BUG_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT); + + if (IS_ENABLED(CONFIG_FSL_CAAM_RNG_PBL_INIT)) { + ret = imx_early_caam_init(MX8M_CAAM_BASE_ADDR); + if (ret) + pr_debug("CAAM early init failed: %d\n", ret); + else + pr_debug("CAAM early init successful\n"); + } memcpy(bl31, fw, fw_size); @@ -40,14 +57,385 @@ static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest) "r" (atf_dest - 16) : "cc"); bl31(); + __builtin_unreachable(); +} + +void imx8mm_load_bl33(void *bl33) +{ + enum bootsource src; + int instance; + + imx8mm_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8m_esdhc_load_image(instance, bl33); + break; + case BOOTSOURCE_SERIAL: + if (!IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC_PBL)) { + printf("Serial bootmode not supported\n"); + break; + } + + /* + * Traditionally imx-usb-loader sends the PBL twice. The first + * PBL is loaded to OCRAM and executed. Then the full barebox + * image including the PBL is sent again and received here. We + * might change that in the future in imx-usb-loader so that the + * PBL is sent only once and we only receive the rest of the + * image here. To prepare that step we check if we get a full + * barebox image or piggydata only. When it's piggydata only move + * it to the place where it would be if it would have been a + * full image. + */ + imx8mm_barebox_load_usb(bl33); + + if (!strcmp("barebox", bl33 + 0x20)) { + /* Found the barebox marker, so this is a PBL + piggydata */ + pr_debug("received PBL + piggydata\n"); + } else { + /* no barebox marker, so this is piggydata only */ + pr_debug("received piggydata\n"); + memmove(bl33 + barebox_pbl_size, bl33, + barebox_image_size - barebox_pbl_size); + } + + break; + case BOOTSOURCE_SPI: + imx8mm_qspi_load_image(instance, bl33); + break; + default: + printf("Unsupported bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy(bl33, __image_start, barebox_pbl_size); +} + +static void imx_adjust_optee_memory(void **bl32, void **bl32_image, size_t *bl32_size) +{ + struct optee_header *hdr = *bl32_image; + u64 membase; + + if (optee_verify_header(hdr)) + return; + + imx_scratch_save_optee_hdr(hdr); + + membase = (u64)hdr->init_load_addr_hi << 32; + membase |= hdr->init_load_addr_lo; + + *bl32 = (void *)membase; + *bl32_size -= sizeof(*hdr); + *bl32_image += sizeof(*hdr); +} + +__noreturn void imx8mm_load_and_start_image_via_tfa(void) +{ + __imx8mm_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR); +} + +__noreturn void __imx8mm_load_and_start_image_via_tfa(void *bl33) +{ + const void *bl31; + size_t bl31_size; + unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32); + + imx_set_cpu_type(IMX_CPU_IMX8MM); + imx8mm_init_scratch_space(); + imx8m_save_bootrom_log(); + imx8mm_load_bl33(bl33); + + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) { + void *bl32 = (void *)arm_mem_optee(endmem); + size_t bl32_size; + void *bl32_image; + + imx8m_tzc380_init(); + get_builtin_firmware_ext(imx8mm_bl32_bin, + bl33, &bl32_image, + &bl32_size); + + imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size); + + memcpy(bl32, bl32_image, bl32_size); + + get_builtin_firmware(imx8mm_bl31_bin_optee, &bl31, &bl31_size); + } else { + get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size); + } + + imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MM_ATF_BL31_BASE_ADDR); +} + +void imx8mp_load_bl33(void *bl33) +{ + enum bootsource src; + int instance; + + imx8mp_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8mp_esdhc_load_image(instance, bl33); + break; + case BOOTSOURCE_SERIAL: + imx8mp_romapi_load_image(bl33); + break; + case BOOTSOURCE_SPI: + imx8mp_qspi_load_image(instance, bl33); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy(bl33, __image_start, barebox_pbl_size); } -void imx8mm_atf_load_bl31(const void *fw, size_t fw_size) +__noreturn void imx8mp_load_and_start_image_via_tfa(void) { - imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR); + __imx8mp_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR); } -void imx8mq_atf_load_bl31(const void *fw, size_t fw_size) +__noreturn void __imx8mp_load_and_start_image_via_tfa(void *bl33) +{ + const void *bl31; + size_t bl31_size; + unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32); + + imx_set_cpu_type(IMX_CPU_IMX8MP); + imx8mp_init_scratch_space(); + imx8m_save_bootrom_log(); + imx8mp_load_bl33(bl33); + + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) { + void *bl32 = (void *)arm_mem_optee(endmem); + size_t bl32_size; + void *bl32_image; + + imx8m_tzc380_init(); + get_builtin_firmware_ext(imx8mp_bl32_bin, + bl33, &bl32_image, + &bl32_size); + + imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size); + + memcpy(bl32, bl32_image, bl32_size); + + get_builtin_firmware(imx8mp_bl31_bin_optee, &bl31, &bl31_size); + } else { + get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size); + } + + imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MP_ATF_BL31_BASE_ADDR); +} + + +void imx8mn_load_bl33(void *bl33) { - imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR); + enum bootsource src; + int instance; + + imx8mn_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8mn_esdhc_load_image(instance, bl33); + break; + case BOOTSOURCE_SERIAL: + imx8mn_romapi_load_image(bl33); + break; + case BOOTSOURCE_SPI: + imx8mn_qspi_load_image(instance, bl33); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy(bl33, __image_start, barebox_pbl_size); +} + +__noreturn void imx8mn_load_and_start_image_via_tfa(void) +{ + __imx8mn_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR); +} + +__noreturn void __imx8mn_load_and_start_image_via_tfa(void *bl33) +{ + const void *bl31; + size_t bl31_size; + unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(16); + + imx_set_cpu_type(IMX_CPU_IMX8MN); + imx8mn_init_scratch_space(); + imx8m_save_bootrom_log(); + imx8mn_load_bl33(bl33); + + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MN_OPTEE)) { + void *bl32 = (void *)arm_mem_optee(endmem); + size_t bl32_size; + void *bl32_image; + + imx8m_tzc380_init(); + get_builtin_firmware_ext(imx8mn_bl32_bin, + bl33, &bl32_image, + &bl32_size); + + imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size); + + memcpy(bl32, bl32_image, bl32_size); + + get_builtin_firmware(imx8mn_bl31_bin_optee, &bl31, &bl31_size); + } else { + get_builtin_firmware(imx8mn_bl31_bin, &bl31, &bl31_size); + } + + imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MN_ATF_BL31_BASE_ADDR); +} + +void imx8mq_load_bl33(void *bl33) +{ + enum bootsource src; + int instance; + + imx8mq_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8m_esdhc_load_image(instance, bl33); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy(bl33, __image_start, barebox_pbl_size); +} + +__noreturn void imx8mq_load_and_start_image_via_tfa(void) +{ + __imx8mq_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR); +} + +__noreturn void __imx8mq_load_and_start_image_via_tfa(void *bl33) +{ + const void *bl31; + size_t bl31_size; + unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32); + + imx_set_cpu_type(IMX_CPU_IMX8MQ); + imx8mq_init_scratch_space(); + imx8m_save_bootrom_log(); + imx8mq_load_bl33(bl33); + + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_OPTEE)) { + void *bl32 = (void *)arm_mem_optee(endmem); + size_t bl32_size; + void *bl32_image; + + imx8m_tzc380_init(); + get_builtin_firmware_ext(imx8mq_bl32_bin, + bl33, &bl32_image, + &bl32_size); + + imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size); + + memcpy(bl32, bl32_image, bl32_size); + + get_builtin_firmware(imx8mq_bl31_bin_optee, &bl31, &bl31_size); + } else { + get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); + } + + imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR); +} + +void __noreturn imx93_load_and_start_image_via_tfa(void) +{ + unsigned long atf_dest = MX93_ATF_BL31_BASE_ADDR; + void __noreturn (*bl31)(void) = (void *)atf_dest; + const void *tfa; + size_t tfa_size; + void *bl33 = (void *)MX93_ATF_BL33_BASE_ADDR; + unsigned long endmem = MX9_DDR_CSD1_BASE_ADDR + imx9_ddrc_sdram_size(); + + imx_set_cpu_type(IMX_CPU_IMX93); + imx93_init_scratch_space(true); + + /* + * On completion the TF-A will jump to MX93_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + * + * The second purpose of this memcpy is for USB booting. When booting + * from USB the image comes in as a stream, so the PBL is transferred + * only once. As we jump into the PBL again in SDRAM we need to copy + * it there. The USB protocol transfers data in chunks of 1024 bytes, + * so align the copy size up to the next 1KiB boundary. + */ + memcpy((void *)MX93_ATF_BL33_BASE_ADDR, __image_start, ALIGN(barebox_pbl_size, 1024)); + + if (IS_ENABLED(CONFIG_FIRMWARE_IMX93_OPTEE)) { + void *bl32 = (void *)arm_mem_optee(endmem); + size_t bl32_size; + void *bl32_image; + + imx93_ele_load_fw(bl33); + + get_builtin_firmware_ext(imx93_bl32_bin, + bl33, &bl32_image, + &bl32_size); + + imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size); + + memcpy(bl32, bl32_image, bl32_size); + + get_builtin_firmware(imx93_bl31_bin_optee, &tfa, &tfa_size); + } else { + get_builtin_firmware(imx93_bl31_bin, &tfa, &tfa_size); + } + + memcpy(bl31, tfa, tfa_size); + + asm volatile("msr sp_el2, %0" : : + "r" (MX93_ATF_BL33_BASE_ADDR - 16) : + "cc"); + bl31(); + __builtin_unreachable(); } diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index ef868301cd..3fea22d05f 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <bootsource.h> @@ -19,20 +8,23 @@ #include <magicvar.h> #include <io.h> -#include <mach/generic.h> -#include <mach/imx25-regs.h> -#include <mach/imx27-regs.h> -#include <mach/imx35-regs.h> -#include <mach/imx51-regs.h> -#include <mach/imx53-regs.h> -#include <mach/imx6-regs.h> -#include <mach/imx7-regs.h> -#include <mach/imx8mm-regs.h> -#include <mach/imx8mq-regs.h> -#include <mach/vf610-regs.h> -#include <mach/imx8mq.h> -#include <mach/imx6.h> - +#include <mach/imx/clock-imx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx35-regs.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx7-regs.h> +#include <mach/imx/imx8mm-regs.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/imx8mq-regs.h> +#include <mach/imx/vf610-regs.h> +#include <mach/imx/imx8mq.h> +#include <mach/imx/imx6.h> + +#include <soc/fsl/fsl_udc.h> static void imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *)) @@ -42,8 +34,7 @@ imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *)) get_boot_source(&src, &instance); - bootsource_set(src); - bootsource_set_instance(instance); + bootsource_set(src, instance); } @@ -211,7 +202,8 @@ void imx51_boot_save_loc(void) } #define IMX53_SRC_SBMR 0x4 -#define SRC_SBMR_BMOD GENMASK(25, 24) +#define IMX53_SRC_SBMR_BMOD GENMASK(25, 24) +#define IMX8MP_SRC_SBMR_BMOD GENMASK(27, 24) #define IMX53_BMOD_SERIAL 0b11 #define __BOOT_CFG(n, m, l) GENMASK((m) + ((n) - 1) * 8, \ @@ -243,7 +235,17 @@ __MAKE_BOOT_CFG_BITS(4) static unsigned int imx53_get_bmod(uint32_t r) { - return FIELD_GET(SRC_SBMR_BMOD, r); + return FIELD_GET(IMX53_SRC_SBMR_BMOD, r); +} + +static unsigned int imx8mp_get_bmod(uint32_t r) +{ + return FIELD_GET(IMX8MP_SRC_SBMR_BMOD, r); +} + +static unsigned int imx8mm_get_bcfg(uint32_t r) +{ + return FIELD_GET(BOOT_CFG2(6, 4), r); } static int imx53_bootsource_internal(uint32_t r) @@ -293,6 +295,8 @@ void imx53_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(cfg1)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } @@ -315,8 +319,7 @@ void imx53_boot_save_loc(void) imx53_get_boot_source(&src, &instance); - bootsource_set(src); - bootsource_set_instance(instance); + bootsource_set(src, instance); } #define IMX6_SRC_SBMR1 0x04 @@ -325,6 +328,9 @@ void imx53_boot_save_loc(void) #define IMX6_SRC_GPR10 0x44 #define IMX6_BMOD_SERIAL 0b01 #define IMX6_BMOD_RESERVED 0b11 +#define IMX8MM_BCFG_FSPI 0b100 +#define IMX8MP_BMOD_FUSES 0b0000 +#define IMX8MP_BMOD_SERIAL 0b0001 #define IMX6_BMOD_FUSES 0b00 #define BT_FUSE_SEL BIT(4) #define GPR10_BOOT_FROM_GPR9 BIT(28) @@ -346,6 +352,23 @@ static bool imx6_bootsource_serial(uint32_t sbmr2) !(sbmr2 & BT_FUSE_SEL)); } +static bool imx8mp_bootsource_serial(uint32_t sbmr2) +{ + return imx8mp_get_bmod(sbmr2) == IMX8MP_BMOD_SERIAL || + /* + * If boot from fuses is selected and fuses are not + * programmed by setting BT_FUSE_SEL, ROM code will + * fallback to serial mode + */ + (imx8mp_get_bmod(sbmr2) == IMX8MP_BMOD_FUSES && + !(sbmr2 & BT_FUSE_SEL)); +} + +static bool imx8mm_bootsource_qspi(uint32_t sbmr1) +{ + return imx8mm_get_bcfg(sbmr1) == IMX8MM_BCFG_FSPI; +} + static bool imx6_bootsource_serial_forced(uint32_t bootmode) { if (cpu_mx6_is_mx6ul() || cpu_mx6_is_mx6ull()) @@ -407,6 +430,11 @@ static u32 imx6_get_src_boot_mode(void __iomem *src_base) return readl(src_base + IMX6_SRC_SBMR1); } +static inline bool imx6_usboh3_clk_active(void) +{ + return (readl(MXC_CCM_CCGR6) & 0x3) == 0x3; +} + void imx6_get_boot_source(enum bootsource *src, int *instance) { void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR); @@ -420,6 +448,26 @@ void imx6_get_boot_source(enum bootsource *src, int *instance) bootsrc = imx53_bootsource_internal(bootmode); + /* + * imx6_bootsource_serial() can't detect cases where the boot ROM + * decided to use the serial downloader as a fall back (primary + * boot source failed). + * + * Infer that the boot ROM used the USB serial downloader by + * checking whether both the UDC and the clock enabling access + * to its MMIO region are currently active... + * This assumes: + * - On fresh boots, PBL doesn't itself start a stopped UDC + * - In barebox proper, boot source is saved before the UDC driver + * may enable the UDC + */ + + if (imx6_usboh3_clk_active() && + is_chipidea_udc_running(IOMEM(MX6_OTG_BASE_ADDR))) { + *src = BOOTSOURCE_SERIAL; + return; + } + if (imx6_bootsource_serial(sbmr2) || imx6_bootsource_serial_forced(bootsrc)) { *src = BOOTSOURCE_SERIAL; @@ -447,6 +495,8 @@ void imx6_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(bootmode)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } } @@ -478,11 +528,6 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance, { const struct imx_boot_sw_info *info; - if (imx6_bootsource_serial(sbmr2)) { - *src = BOOTSOURCE_SERIAL; - return; - } - info = (const void *)(unsigned long) readl(boot_sw_info_pointer_addr); @@ -501,11 +546,17 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance, break; case 4: *src = BOOTSOURCE_SPI; /* Really: qspi */ + *instance = info->boot_device_instance; break; case 5: *src = BOOTSOURCE_NOR; break; + case 14: /* observed on i.MX8MP for USB "serial" booting */ + case 15: /* observed on i.MX8MM for USB "serial" booting */ + *src = BOOTSOURCE_SERIAL; + break; default: + *src = BOOTSOURCE_UNKNOWN; break; } } @@ -515,6 +566,11 @@ void imx7_get_boot_source(enum bootsource *src, int *instance) void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR); uint32_t sbmr2 = readl(src_base + 0x70); + if (imx6_bootsource_serial(sbmr2)) { + *src = BOOTSOURCE_SERIAL; + return; + } + __imx7_get_boot_source(src, instance, IMX7_BOOT_SW_INFO_POINTER_ADDR, sbmr2); } @@ -609,6 +665,8 @@ void vf610_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(sbmr1)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } } @@ -628,6 +686,11 @@ void imx8mq_get_boot_source(enum bootsource *src, int *instance) IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 : IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0; + if (imx6_bootsource_serial(sbmr2)) { + *src = BOOTSOURCE_SERIAL; + return; + } + __imx7_get_boot_source(src, instance, addr, sbmr2); } @@ -640,14 +703,56 @@ void imx8mm_get_boot_source(enum bootsource *src, int *instance) { unsigned long addr; void __iomem *src_base = IOMEM(MX8MM_SRC_BASE_ADDR); + uint32_t sbmr1 = readl(src_base + 0x58); uint32_t sbmr2 = readl(src_base + 0x70); + if (imx6_bootsource_serial(sbmr2)) { + *src = BOOTSOURCE_SERIAL; + return; + } + addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0; __imx7_get_boot_source(src, instance, addr, sbmr2); + + if (*src != BOOTSOURCE_UNKNOWN) + return; + + if (imx8mm_bootsource_qspi(sbmr1)) { + *src = BOOTSOURCE_SPI; /* Really: qspi */ + *instance = 0; + return; + } } void imx8mm_boot_save_loc(void) { imx_boot_save_loc(imx8mm_get_boot_source); } + +void imx8mp_get_boot_source(enum bootsource *src, int *instance) +{ + unsigned long addr; + void __iomem *src_base = IOMEM(MX8MP_SRC_BASE_ADDR); + uint32_t sbmr2 = readl(src_base + 0x70); + + if (imx8mp_bootsource_serial(sbmr2)) { + *src = BOOTSOURCE_SERIAL; + return; + } + + addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0; + + __imx7_get_boot_source(src, instance, addr, sbmr2); +} + +void imx8mp_boot_save_loc(void) +{ + imx_boot_save_loc(imx8mp_get_boot_source); +} + +void imx8mn_get_boot_source(enum bootsource *src, int *instance) + __alias(imx8mp_get_boot_source); + +void imx8mn_boot_save_loc(void) + __alias(imx8mp_boot_save_loc); diff --git a/arch/arm/mach-imx/bootrom-cmd.c b/arch/arm/mach-imx/bootrom-cmd.c new file mode 100644 index 0000000000..08e393b01a --- /dev/null +++ b/arch/arm/mach-imx/bootrom-cmd.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <command.h> +#include <errno.h> +#include <getopt.h> +#include <printk.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/romapi.h> + +/* i.MX7 and later ID field is swapped compared to i.MX6 */ +#define ROM_EVENT_FORMAT_V0_RES GENMASK(31, 24) +#define ROM_EVENT_FORMAT_V0_ID GENMASK(23, 0) +#define ROM_EVENT_FORMAT_V1_ID GENMASK(31, 24) +#define ROM_EVENT_FORMAT_V1_ID_TYPE GENMASK(31, 28) +#define ROM_EVENT_FORMAT_V1_ID_IDX GENMASK(27, 24) +#define ROM_EVENT_FORMAT_V1_RES GENMASK(23, 0) + +static const char *lookup(const char *table[], size_t table_size, size_t idx) +{ + const char *str = NULL; + + if (idx < table_size) + str = table[idx]; + + return str ?: "unknown"; +} + +#define LOOKUP(table, idx) lookup(table, ARRAY_SIZE(table), idx) + +static const char *boot_mode_0x1y[] = { + "Fuse", "Serial Download", "Internal Download", "Test Mode" +}; + +static const char *secure_config_0x2y[] = { + "FAB", "Field Return", "Open", "Closed" +}; + +static const char *boot_image_0x5y[] = { + "primary", "secondary" +}; + +static const char *boot_device_0x6y[] = { + "RAW NAND", "SD or EMMC", NULL, NULL, "ECSPI NOR", NULL, NULL, "QSPI NOR" +}; + +/* Parse the ROM event ID defintion version 1 log, see AN12853 */ +static int imx8m_bootrom_decode_log(const u32 *rom_log) +{ + int i; + + if (!rom_log) + return -ENODATA; + + for (i = 0; i < 128; i++) { + u8 event_id = FIELD_GET(ROM_EVENT_FORMAT_V1_ID, rom_log[i]); + u8 event_id_idx = FIELD_GET(ROM_EVENT_FORMAT_V1_ID_IDX, rom_log[i]); + const char *arg = NULL; + + printf("[%02x] ", event_id); + switch (event_id) { + case 0x0: + printf("End of list\n"); + return 0; + case 0x01: + printf("ROM event version 0x%02x\n", rom_log[i] & 0xFF); + continue; + + case 0x10 ... 0x13: + printf("Boot mode is Boot from %s\n", + LOOKUP(boot_mode_0x1y, event_id_idx)); + continue; + + case 0x20 ... 0x23: + printf("Secure config is %s\n", + LOOKUP(secure_config_0x2y, event_id_idx)); + continue; + + case 0x30 ... 0x31: + case 0xe0: + printf("Internal use\n"); + continue; + + case 0x40 ... 0x41: + printf("FUSE_SEL_VALUE Fuse is %sblown\n", + event_id_idx ? "" : "not "); + continue; + + case 0x50 ... 0x51: + printf("Boot from the %s boot image\n", + LOOKUP(boot_image_0x5y, event_id_idx)); + continue; + + case 0x74: + arg = "SPI NAND"; + fallthrough; + case 0x60 ... 0x67: + printf("Primary boot from %s device\n", + arg ?: LOOKUP(boot_device_0x6y, event_id_idx)); + continue; + + case 0x71: + printf("Recovery boot from ECSPI NOR device\n"); + continue; + case 0x72: + printf("No Recovery boot device\n"); + continue; + case 0x73: + printf("Manufacture boot from SD or EMMC\n"); + continue; + + case 0x80: + printf("Start to perform the device initialization: @%u ticks\n", + rom_log[++i]); + continue; + case 0x81: + printf("The boot device initialization completes: @%u ticks\n", + rom_log[++i]); + continue; + case 0x82: + printf("Start to execute boot device driver pre-config @%u ticks\n", + rom_log[++i]); + continue; + case 0x83: + printf("Boot device driver pre-config completes\n"); + continue; + case 0x8E: + printf("Boot device driver pre-config fails\n"); + continue; + case 0x8f: + printf("boot device initialization fails: @%u ticks\n", + rom_log[++i]); + continue; + + case 0x90: + printf("Start to read data from boot device: @ offset %08x\n", + rom_log[++i]); + continue; + case 0x91: + printf("Reading data from boot device completes: @%u ticks\n", + rom_log[++i]); + continue; + case 0x9f: + printf("Reading data from boot device fails: @%u ticks\n", + rom_log[++i]); + continue; + + case 0xa0: + printf("Image authentication result: %s(0x%08x) @%u ticks\n", + (rom_log[i+1] & 0xFF) == 0xF0 ? "PASS " : "", + rom_log[i+1], rom_log[i+2]); + i += 2; + continue; + case 0xa1: + printf("IVT header is not valid\n"); + continue; + + case 0xc0: + printf("Jump to the boot image soon: @ offset 0x%08x @ %u ticks\n", + rom_log[i+1], rom_log[i+2]); + i += 2; + continue; + + case 0xd0: + printf("Enters serial download processing\n"); + continue; + + case 0xf0: + printf("Enters ROM exception handler\n"); + continue; + default: + printf("Unknown\n"); + continue; + } + } + + return -EILSEQ; +} + +static int do_bootrom(int argc, char *argv[]) +{ + union { + const u32 *ptr; + ulong addr; + } rom_log = { NULL }; + bool log = false; + int ret, opt; + + while((opt = getopt(argc, argv, "la:")) > 0) { + switch(opt) { + case 'a': + ret = kstrtoul(optarg, 0, &rom_log.addr); + if (ret) + return ret; + case 'l': + log = true; + break; + default: + return COMMAND_ERROR_USAGE; + } + } + + if (!rom_log.addr) + rom_log.ptr = imx8m_get_bootrom_log(); + + if (log) + return imx8m_bootrom_decode_log(rom_log.ptr); + + return COMMAND_ERROR_USAGE; +} + +BAREBOX_CMD_HELP_START(bootrom) +BAREBOX_CMD_HELP_TEXT("List information about the specified files or directories.") +BAREBOX_CMD_HELP_TEXT("") +BAREBOX_CMD_HELP_TEXT("Options:") +BAREBOX_CMD_HELP_OPT ("-l", "list event log") +BAREBOX_CMD_HELP_OPT ("-a ADDR", "event log address (default PBL scratch space)") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(bootrom) + .cmd = do_bootrom, + BAREBOX_CMD_DESC("Interact with BootROM on i.MX8M") + BAREBOX_CMD_OPTS("[-la]") + BAREBOX_CMD_HELP(cmd_bootrom_help) + BAREBOX_CMD_GROUP(CMD_GRP_INFO) +BAREBOX_CMD_END diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index c6a0ac7c50..c5a47d9b91 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -1,26 +1,17 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <asm/barebox-arm-head.h> #include <asm/errata.h> #include <linux/types.h> #include <linux/bitops.h> -#include <mach/generic.h> -#include <mach/imx7-regs.h> -#include <mach/imx8mq-regs.h> -#include <common.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx7-regs.h> +#include <mach/imx/imx8mq-regs.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/imx9-regs.h> +#include <mach/imx/trdc.h> #include <io.h> #include <asm/syscounter.h> #include <asm/system.h> @@ -60,6 +51,7 @@ void imx6ul_cpu_lowlevel_init(void) void imx7_cpu_lowlevel_init(void) { + cortex_a7_lowlevel_init(); arm_cpu_lowlevel_init(); imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR)); } @@ -79,11 +71,60 @@ static void imx8m_cpu_lowlevel_init(void) void imx8mm_cpu_lowlevel_init(void) { + /* ungate system counter */ + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); + imx8m_cpu_lowlevel_init(); } +void imx8mn_cpu_lowlevel_init(void) + __alias(imx8mm_cpu_lowlevel_init); + +void imx8mp_cpu_lowlevel_init(void) + __alias(imx8mm_cpu_lowlevel_init); + void imx8mq_cpu_lowlevel_init(void) { imx8m_cpu_lowlevel_init(); } + +#define CCM_AUTHEN_TZ_NS BIT(9) + +#define OSCPLLa_AUTHEN(n) (0x5030 + (n) * 0x40) /* 0..18 */ +#define CLOCK_ROOT_AUTHEN(n) (0x30 + (n) * 0x80) /* 0..94 */ +#define LPCGa_AUTHEN(n) (0x8030 + (n) * 0x40) /* 0..126 */ +#define GPR_SHARED0_AUTHEN(n) (0x4810 + (n) * 0x10) /* 0..3 */ +#define SET 4 + +#define SRC_SP_ISO_CTRL 0x10c + +void imx93_cpu_lowlevel_init(void) +{ + void __iomem *ccm = IOMEM(MX9_CCM_BASE_ADDR); + void __iomem *src = IOMEM(MX9_SRC_BASE_ADDR); + int i; + + arm_cpu_lowlevel_init(); + + if (current_el() != 3) + return; + + imx9_trdc_init(); + + imx_cpu_timer_init(IOMEM(MX9_SYSCNT_CTRL_BASE_ADDR)); + + for (i = 0; i <= 18; i++) + writel(CCM_AUTHEN_TZ_NS, ccm + OSCPLLa_AUTHEN(i) + SET); + for (i = 0; i <= 94; i++) + writel(CCM_AUTHEN_TZ_NS, ccm + CLOCK_ROOT_AUTHEN(i) + SET); + for (i = 0; i <= 126 ; i++) + writel(CCM_AUTHEN_TZ_NS, ccm + LPCGa_AUTHEN(i) + SET); + for (i = 0; i <= 3 ; i++) + writel(CCM_AUTHEN_TZ_NS, ccm + GPR_SHARED0_AUTHEN(i) + SET); + + /* clear isolation for usbphy, dsi, csi*/ + writel(0x0, src + SRC_SP_ISO_CTRL); + +} + #endif diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index a0609e282a..7572738d0e 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -1,94 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <driver.h> -#include <mach/devices.h> +#include <mach/imx/devices.h> -static inline struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata) +static inline struct device *imx_add_device(char *name, int id, void *base, int size, void *pdata) { return add_generic_device(name, id, NULL, (resource_size_t)base, size, IORESOURCE_MEM, pdata); } -struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata) +struct device *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata) { return imx_add_device("imx27-fec", -1, base, 0x1000, pdata); } -struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata) +struct device *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata) { return imx_add_device("imx6-fec", -1, base, 0x1000, pdata); } -struct device_d *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata) +struct device *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata) { return imx_add_device("imx27-spi", id, base, 0x1000, pdata); } -struct device_d *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata) +struct device *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata) { return imx_add_device("imx35-spi", id, base, 0x1000, pdata); } -struct device_d *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata) +struct device *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata) { return imx_add_device("imx51-spi", id, base, 0x1000, pdata); } -struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata) +struct device *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata) { return imx_add_device("i2c-fsl", id, base, 0x1000, pdata); } -struct device_d *imx_add_uart_imx1(void *base, int id) +struct device *imx_add_uart_imx1(void *base, int id) { return imx_add_device("imx1-uart", id, base, 0x1000, NULL); } -struct device_d *imx_add_uart_imx21(void *base, int id) +struct device *imx_add_uart_imx21(void *base, int id) { return imx_add_device("imx21-uart", id, base, 0x1000, NULL); } -struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata) +struct device *imx_add_nand(void *base, struct imx_nand_platform_data *pdata) { return imx_add_device("imx_nand", -1, base, 0x1000, pdata); } -struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata) +struct device *imx_add_fb(void *base, struct imx_fb_platform_data *pdata) { return imx_add_device("imxfb", -1, base, 0x1000, pdata); } -struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata) +struct device *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata) { return imx_add_device("imx-ipu-fb", -1, base, 0x1000, pdata); } -struct device_d *imx_add_mmc(void *base, int id, void *pdata) +struct device *imx_add_mmc(void *base, int id, void *pdata) { return imx_add_device("imx-mmc", id, base, 0x1000, pdata); } -struct device_d *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata) +struct device *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata) { return imx_add_device("imx25-esdhc", id, base, 0x1000, pdata); } -struct device_d *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata) +struct device *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata) { return imx_add_device("imx5-esdhc", id, base, 0x1000, pdata); } -struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata) +struct device *imx_add_kpp(void *base, struct matrix_keymap_data *pdata) { return imx_add_device("imx-kpp", -1, base, 0x1000, pdata); } -struct device_d *imx_add_pata(void *base) +struct device *imx_add_pata(void *base) { return imx_add_device("imx-pata", -1, base, 0x1000, NULL); } -struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata) +struct device *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata) { return imx_add_device("imx-usb", id, base, 0x200, pdata); } diff --git a/arch/arm/mach-imx/ele.c b/arch/arm/mach-imx/ele.c new file mode 100644 index 0000000000..48e8749b31 --- /dev/null +++ b/arch/arm/mach-imx/ele.c @@ -0,0 +1,704 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2022 NXP + */ +#define pr_fmt(fmt) "ele: " fmt + +#include <common.h> +#include <io.h> +#include <mach/imx/ele.h> +#include <mach/imx/imx9-regs.h> +#include <linux/iopoll.h> +#include <firmware.h> +#include <linux/bitfield.h> + +#define MU_SR_TE0_MASK BIT(0) +#define MU_SR_RF0_MASK BIT(0) +#define MU_TR_COUNT 8 +#define MU_RR_COUNT 4 + +struct mu_type { + u32 ver; + u32 par; + u32 cr; + u32 sr; + u32 reserved0[60]; + u32 fcr; + u32 fsr; + u32 reserved1[2]; + u32 gier; + u32 gcr; + u32 gsr; + u32 reserved2; + u32 tcr; + u32 tsr; + u32 rcr; + u32 rsr; + u32 reserved3[52]; + u32 tr[16]; + u32 reserved4[16]; + u32 rr[16]; + u32 reserved5[14]; + u32 mu_attr; +}; + +static int mu_hal_sendmsg(void __iomem *base, u32 reg_index, u32 msg) +{ + struct mu_type *mu_base = base; + u32 mask = MU_SR_TE0_MASK << reg_index; + u32 val; + int ret; + + /* Wait TX register to be empty. */ + ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000); + if (ret < 0) { + pr_debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + writel(msg, &mu_base->tr[reg_index]); + + return 0; +} + +static int mu_hal_receivemsg(void __iomem *base, u32 reg_index, u32 *msg) +{ + struct mu_type *mu_base = base; + u32 mask = MU_SR_RF0_MASK << reg_index; + u32 val; + int ret; + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000000); + if (ret < 0) + return -ETIMEDOUT; + + *msg = readl(&mu_base->rr[reg_index]); + + return 0; +} + +static int mu_read(void __iomem *base, struct ele_msg *msg) +{ + int ret, i; + + /* Read first word */ + ret = mu_hal_receivemsg(base, 0, (u32 *)msg); + if (ret) + return ret; + + /* Read remaining words */ + for (i = 1; i < msg->size; i++) { + ret = mu_hal_receivemsg(base, i % MU_RR_COUNT, &msg->data[i - 1]); + if (ret) + return ret; + } + + return 0; +} + +static int mu_write(void __iomem *base, struct ele_msg *msg) +{ + int ret, i; + + /* Write first word */ + ret = mu_hal_sendmsg(base, 0, *((u32 *)msg)); + if (ret) + return ret; + + /* Write remaining words */ + for (i = 1; i < msg->size; i++) { + ret = mu_hal_sendmsg(base, i % MU_TR_COUNT, msg->data[i - 1]); + if (ret) + return ret; + } + + return 0; +} + +static int imx9_s3mua_call(struct ele_msg *msg) +{ + void __iomem *s3mua = IOMEM(MX9_S3MUA_BASE_ADDR); + u32 result; + int ret; + + ret = mu_write(s3mua, msg); + if (ret) + return ret; + + ret = mu_read(s3mua, msg); + if (ret) + return ret; + + result = msg->data[0]; + if ((result & 0xff) == 0xd6) + return 0; + + return -EIO; +} + +int ele_call(struct ele_msg *msg) +{ + return imx9_s3mua_call(msg); +} + +int ele_get_info(struct ele_get_info_data *info) +{ + struct ele_msg msg = { + .version = ELE_VERSION, + .tag = ELE_CMD_TAG, + .size = 4, + .command = ELE_GET_INFO_REQ, + .data = { + upper_32_bits((unsigned long)info), + lower_32_bits((unsigned long)info), + sizeof(struct ele_get_info_data), + }, + }; + int ret; + + ret = ele_call(&msg); + if (ret) + pr_err("Could not get ELE info: ret %d, response 0x%x\n", + ret, msg.data[0]); + + return ret; +} + +static int ele_get_start_trng(void) +{ + struct ele_msg msg = { + .version = ELE_VERSION, + .tag = ELE_CMD_TAG, + .size = 1, + .command = ELE_START_RNG, + }; + int ret; + + ret = ele_call(&msg); + if (ret) + pr_err("Could not start TRNG, response 0x%x\n", msg.data[0]); + + return ret; +} + +int imx93_ele_load_fw(void *bl33) +{ + struct ele_get_info_data info = {}; + struct ele_msg msg = { + .version = ELE_VERSION, + .tag = ELE_CMD_TAG, + .size = 4, + .command = ELE_FW_AUTH_REQ, + }; + void *firmware; + int size, ret; + int rev = 0; + + ele_get_info(&info); + + rev = FIELD_GET(ELE_INFO_SOC_REV, info.soc); + + switch (rev) { + case 0xa0: + get_builtin_firmware_ext(mx93a0_ahab_container_img, bl33, &firmware, &size); + break; + case 0xa1: + get_builtin_firmware_ext(mx93a1_ahab_container_img, bl33, &firmware, &size); + break; + default: + pr_err("Unknown unhandled SoC revision %2x\n", rev); + return -EINVAL; + } + + /* Address of the container header */ + msg.data[0] = lower_32_bits((unsigned long)firmware); + /* Actual address of the container header */ + msg.data[2] = lower_32_bits((unsigned long)firmware); + + ret = ele_call(&msg); + if (ret) + pr_err("Could not start ELE firmware: ret %d, response 0x%x\n", + ret, msg.data[0]); + + if (rev >= 0xa1) + ele_get_start_trng(); + + return 0; +} + +/* + * ele_read_common_fuse - read a fuse + * @fuse_id: The fuse to read (in 32bit word number) + * fuse_word: The value read from the fuse + * @response: on return contains the response from ELE + * + * This reads the shadow value of the fuse @fuse_id. + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_read_common_fuse(u16 fuse_id, u32 *fuse_word, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_READ_FUSE_REQ; + msg.data[0] = fuse_id; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + *fuse_word = msg.data[1]; + + return ret; +} + +/* + * ele_read_shadow_fuse - read a fuse + * @fuse_id: The fuse to read (in 32bit word number) + * fuse_word: The value read from the fuse + * @response: on return contains the response from ELE + * + * This reads the shadow value of the fuse @fuse_id. + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_read_shadow_fuse(u16 fuse_id, u32 *fuse_word, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_READ_SHADOW_REQ; + msg.data[0] = fuse_id; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + *fuse_word = msg.data[1]; + + return ret; +} + +/* + * ele_write_fuse - write a fuse + * @fuse_id: The fuse to write to (in 32bit word number) + * @fuse_val: The value to write to the fuse + * @lock: lock fuse after writing + * @response: on return contains the response from ELE + * + * This writes the 32bit given in @fuse_val to the fuses at @fuse_id. This is + * a permanent change, be careful. + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_FUSE_REQ; + msg.data[0] = (32 << 16) | (fuse_id << 5); + + if (lock) + msg.data[0] |= (1 << 31); + + msg.data[1] = fuse_val; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + return ret; +} + +/* + * ele_write_shadow_fuse - write a fuse + * @fuse_id: The fuse to write to + * @fuse_val: The value to write to the fuse + * @lock: lock fuse after writing + * @response: on return contains the response from ELE + * + * This writes the 32bit given in @fuse_val to the fuses at @fuse_id. This is + * a permanent change, be careful. + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_write_shadow_fuse(u16 fuse_id, u32 fuse_val, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SHADOW_REQ; + msg.data[0] = fuse_id; + + msg.data[1] = fuse_val; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + return ret; +} + +/* + * ele_forward_lifecycle - forward lifecycle + * @lc: The lifecycle value to forward to + * @response: on return contains the response from ELE + * + * This changes the chip's lifecycle value. Mainly useful to forward to + * from ELE_LIFECYCLE_OEM_OPEN to ELE_LIFECYCLE_OEM_CLOSED. When doing + * this the SoC will only boot authenticated images. Make sure the correct + * SRK has been fused beforehand, otherwise you brick your board. + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_forward_lifecycle(enum ele_lifecycle lc, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_FWD_LIFECYCLE_UP_REQ; + msg.data[0] = lc; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + return ret; +} + +/* + * ele_authenticate_container - authenticate a container image + * @addr: the address of the container + * @response: on return contains the response from ELE + * + * This authenticates a container with the ELE. On return the result + * of the authentication will be encoded in @response + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_authenticate_container(unsigned long addr, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_OEM_CNTN_AUTH_REQ; + msg.data[0] = upper_32_bits(addr); + msg.data[1] = lower_32_bits(addr); + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + return ret; +} + +/* + * ele_release_container - release a container image + * @response: on return contains the response from ELE + * + * This releases a container image. Must be called when done with an + * image previously authenticated with ele_authenticate_container() + * + * Return: 0 when the ELE call succeeds, negative error code otherwise + */ +int ele_release_container(u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_RELEASE_CONTAINER_REQ; + + ret = imx9_s3mua_call(&msg); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response) +{ + struct ele_msg msg; + int ret; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_RELEASE_RDC_REQ; + + switch (xrdc) { + case 0: + msg.data[0] = (0x74 << 8) | core_id; + break; + case 1: + msg.data[0] = (0x78 << 8) | core_id; + break; + case 2: + msg.data[0] = (0x82 << 8) | core_id; + break; + case 3: + msg.data[0] = (0x86 << 8) | core_id; + break; + default: + return -EINVAL; + } + + ret = ele_call(&msg); + if (ret) + pr_err("%s: ret %d, core id %u, response 0x%x\n", + __func__, ret, core_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +struct ele_str { + u8 id; + const char *str; +}; + +static struct ele_str ele_ind[] = { + { .id = ELE_ROM_PING_FAILURE_IND, .str = "ELE_ROM_PING_FAILURE" }, + { .id = ELE_FW_PING_FAILURE_IND, .str = "ELE_FW_PING_FAILURE" }, + { .id = ELE_BAD_SIGNATURE_FAILURE_IND, .str = "ELE_BAD_SIGNATURE_FAILURE" }, + { .id = ELE_BAD_HASH_FAILURE_IND, .str = "ELE_BAD_HASH_FAILURE" }, + { .id = ELE_INVALID_LIFECYCLE_IND, .str = "ELE_INVALID_LIFECYCLE" }, + { .id = ELE_PERMISSION_DENIED_FAILURE_IND, .str = "ELE_PERMISSION_DENIED_FAILURE" }, + { .id = ELE_INVALID_MESSAGE_FAILURE_IND, .str = "ELE_INVALID_MESSAGE_FAILURE" }, + { .id = ELE_BAD_VALUE_FAILURE_IND, .str = "ELE_BAD_VALUE_FAILURE" }, + { .id = ELE_BAD_FUSE_ID_FAILURE_IND, .str = "ELE_BAD_FUSE_ID_FAILURE" }, + { .id = ELE_BAD_CONTAINER_FAILURE_IND, .str = "ELE_BAD_CONTAINER_FAILURE" }, + { .id = ELE_BAD_VERSION_FAILURE_IND, .str = "ELE_BAD_VERSION_FAILURE" }, + { .id = ELE_INVALID_KEY_FAILURE_IND, .str = "ELE_INVALID_KEY_FAILURE" }, + { .id = ELE_BAD_KEY_HASH_FAILURE_IND, .str = "ELE_BAD_KEY_HASH_FAILURE" }, + { .id = ELE_NO_VALID_CONTAINER_FAILURE_IND, .str = "ELE_NO_VALID_CONTAINER_FAILURE" }, + { .id = ELE_BAD_CERTIFICATE_FAILURE_IND, .str = "ELE_BAD_CERTIFICATE_FAILURE" }, + { .id = ELE_BAD_UID_FAILURE_IND, .str = "ELE_BAD_UID_FAILURE" }, + { .id = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND, .str = "ELE_BAD_MONOTONIC_COUNTER_FAILURE" }, + { .id = ELE_MUST_SIGNED_FAILURE_IND, .str = "ELE_MUST_SIGNED_FAILURE" }, + { .id = ELE_NO_AUTHENTICATION_FAILURE_IND, .str = "ELE_NO_AUTHENTICATION_FAILURE" }, + { .id = ELE_BAD_SRK_SET_FAILURE_IND, .str = "ELE_BAD_SRK_SET_FAILURE" }, + { .id = ELE_UNALIGNED_PAYLOAD_FAILURE_IND, .str = "ELE_UNALIGNED_PAYLOAD_FAILURE" }, + { .id = ELE_WRONG_SIZE_FAILURE_IND, .str = "ELE_WRONG_SIZE_FAILURE" }, + { .id = ELE_ENCRYPTION_FAILURE_IND, .str = "ELE_ENCRYPTION_FAILURE" }, + { .id = ELE_DECRYPTION_FAILURE_IND, .str = "ELE_DECRYPTION_FAILURE" }, + { .id = ELE_OTP_PROGFAIL_FAILURE_IND, .str = "ELE_OTP_PROGFAIL_FAILURE" }, + { .id = ELE_OTP_LOCKED_FAILURE_IND, .str = "ELE_OTP_LOCKED_FAILURE" }, + { .id = ELE_OTP_INVALID_IDX_FAILURE_IND, .str = "ELE_OTP_INVALID_IDX_FAILURE" }, + { .id = ELE_TIME_OUT_FAILURE_IND, .str = "ELE_TIME_OUT_FAILURE" }, + { .id = ELE_BAD_PAYLOAD_FAILURE_IND, .str = "ELE_BAD_PAYLOAD_FAILURE" }, + { .id = ELE_WRONG_ADDRESS_FAILURE_IND, .str = "ELE_WRONG_ADDRESS_FAILURE" }, + { .id = ELE_DMA_FAILURE_IND, .str = "ELE_DMA_FAILURE" }, + { .id = ELE_DISABLED_FEATURE_FAILURE_IND, .str = "ELE_DISABLED_FEATURE_FAILURE" }, + { .id = ELE_MUST_ATTEST_FAILURE_IND, .str = "ELE_MUST_ATTEST_FAILURE" }, + { .id = ELE_RNG_NOT_STARTED_FAILURE_IND, .str = "ELE_RNG_NOT_STARTED_FAILURE" }, + { .id = ELE_CRC_ERROR_IND, .str = "ELE_CRC_ERROR" }, + { .id = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND, .str = "ELE_AUTH_SKIPPED_OR_FAILED_FAILURE" }, + { .id = ELE_INCONSISTENT_PAR_FAILURE_IND, .str = "ELE_INCONSISTENT_PAR_FAILURE" }, + { .id = ELE_RNG_INST_FAILURE_FAILURE_IND, .str = "ELE_RNG_INST_FAILURE_FAILURE" }, + { .id = ELE_LOCKED_REG_FAILURE_IND, .str = "ELE_LOCKED_REG_FAILURE" }, + { .id = ELE_BAD_ID_FAILURE_IND, .str = "ELE_BAD_ID_FAILURE" }, + { .id = ELE_INVALID_OPERATION_FAILURE_IND, .str = "ELE_INVALID_OPERATION_FAILURE" }, + { .id = ELE_NON_SECURE_STATE_FAILURE_IND, .str = "ELE_NON_SECURE_STATE_FAILURE" }, + { .id = ELE_MSG_TRUNCATED_IND, .str = "ELE_MSG_TRUNCATED" }, + { .id = ELE_BAD_IMAGE_NUM_FAILURE_IND, .str = "ELE_BAD_IMAGE_NUM_FAILURE" }, + { .id = ELE_BAD_IMAGE_ADDR_FAILURE_IND, .str = "ELE_BAD_IMAGE_ADDR_FAILURE" }, + { .id = ELE_BAD_IMAGE_PARAM_FAILURE_IND, .str = "ELE_BAD_IMAGE_PARAM_FAILURE" }, + { .id = ELE_BAD_IMAGE_TYPE_FAILURE_IND, .str = "ELE_BAD_IMAGE_TYPE_FAILURE" }, + { .id = ELE_CORRUPTED_SRK_FAILURE_IND, .str = "ELE_CORRUPTED_SRK_FAILURE" }, + { .id = ELE_OUT_OF_MEMORY_IND, .str = "ELE_OUT_OF_MEMORY" }, + { .id = ELE_CSTM_FAILURE_IND, .str = "ELE_CSTM_FAILURE" }, + { .id = ELE_OLD_VERSION_FAILURE_IND, .str = "ELE_OLD_VERSION_FAILURE" }, + { .id = ELE_WRONG_BOOT_MODE_FAILURE_IND, .str = "ELE_WRONG_BOOT_MODE_FAILURE" }, + { .id = ELE_APC_ALREADY_ENABLED_FAILURE_IND, .str = "ELE_APC_ALREADY_ENABLED_FAILURE" }, + { .id = ELE_RTC_ALREADY_ENABLED_FAILURE_IND, .str = "ELE_RTC_ALREADY_ENABLED_FAILURE" }, + { .id = ELE_ABORT_IND, .str = "ELE_ABORT" }, +}; + +static struct ele_str ele_ipc[] = { + { .id = ELE_IPC_MU_RTD, .str = "MU RTD" }, + { .id = ELE_IPC_MU_APD, .str = "MU APD" }, +}; + +static struct ele_str ele_command[] = { + { .id = ELE_PING_REQ, .str = "ELE_PING" }, + { .id = ELE_FW_AUTH_REQ, .str = "ELE_FW_AUTH" }, + { .id = ELE_RESTART_RST_TIMER_REQ, .str = "ELE_RESTART_RST_TIMER" }, + { .id = ELE_DUMP_DEBUG_BUFFER_REQ, .str = "ELE_DUMP_DEBUG_BUFFER" }, + { .id = ELE_OEM_CNTN_AUTH_REQ, .str = "ELE_OEM_CNTN_AUTH" }, + { .id = ELE_VERIFY_IMAGE_REQ, .str = "ELE_VERIFY_IMAGE" }, + { .id = ELE_RELEASE_CONTAINER_REQ, .str = "ELE_RELEASE_CONTAINER" }, + { .id = ELE_WRITE_SECURE_FUSE_REQ, .str = "ELE_WRITE_SECURE_FUSE" }, + { .id = ELE_FWD_LIFECYCLE_UP_REQ, .str = "ELE_FWD_LIFECYCLE_UP" }, + { .id = ELE_READ_FUSE_REQ, .str = "ELE_READ_FUSE" }, + { .id = ELE_GET_FW_VERSION_REQ, .str = "ELE_GET_FW_VERSION" }, + { .id = ELE_RET_LIFECYCLE_UP_REQ, .str = "ELE_RET_LIFECYCLE_UP" }, + { .id = ELE_GET_EVENTS_REQ, .str = "ELE_GET_EVENTS" }, + { .id = ELE_ENABLE_PATCH_REQ, .str = "ELE_ENABLE_PATCH" }, + { .id = ELE_RELEASE_RDC_REQ, .str = "ELE_RELEASE_RDC" }, + { .id = ELE_GET_FW_STATUS_REQ, .str = "ELE_GET_FW_STATUS" }, + { .id = ELE_ENABLE_OTFAD_REQ, .str = "ELE_ENABLE_OTFAD" }, + { .id = ELE_RESET_REQ, .str = "ELE_RESET" }, + { .id = ELE_UPDATE_OTP_CLKDIV_REQ, .str = "ELE_UPDATE_OTP_CLKDIV" }, + { .id = ELE_POWER_DOWN_REQ, .str = "ELE_POWER_DOWN" }, + { .id = ELE_ENABLE_APC_REQ, .str = "ELE_ENABLE_APC" }, + { .id = ELE_ENABLE_RTC_REQ, .str = "ELE_ENABLE_RTC" }, + { .id = ELE_DEEP_POWER_DOWN_REQ, .str = "ELE_DEEP_POWER_DOWN" }, + { .id = ELE_STOP_RST_TIMER_REQ, .str = "ELE_STOP_RST_TIMER" }, + { .id = ELE_WRITE_FUSE_REQ, .str = "ELE_WRITE_FUSE" }, + { .id = ELE_RELEASE_CAAM_REQ, .str = "ELE_RELEASE_CAAM" }, + { .id = ELE_RESET_A35_CTX_REQ, .str = "ELE_RESET_A35_CTX" }, + { .id = ELE_MOVE_TO_UNSECURED_REQ, .str = "ELE_MOVE_TO_UNSECURED" }, + { .id = ELE_GET_INFO_REQ, .str = "ELE_GET_INFO" }, + { .id = ELE_ATTEST_REQ, .str = "ELE_ATTEST" }, + { .id = ELE_RELEASE_PATCH_REQ, .str = "ELE_RELEASE_PATCH" }, + { .id = ELE_OTP_SEQ_SWITH_REQ, .str = "ELE_OTP_SEQ_SWITH" }, +}; + +static struct ele_str ele_status[] = { + { .id = ELE_SUCCESS_IND, .str = "ELE_SUCCESS" }, + { .id = ELE_FAILURE_IND, .str = "ELE_FAILURE" }, +}; + +static const struct ele_str *get_idx(struct ele_str *str, int size, int id) +{ + u32 i; + + for (i = 0; i < size; i++) { + if (str[i].id == id) + return &str[i]; + } + + return NULL; +} + +#define ELE_EVENT_IPC GENMASK(31, 24) +#define ELE_EVENT_COMMAND GENMASK(23, 16) +#define ELE_EVENT_IND GENMASK(15, 8) +#define ELE_EVENT_STATUS GENMASK(7, 0) + +static void display_event(u32 event) +{ + int ipc = FIELD_GET(ELE_EVENT_IPC, event); + int command = FIELD_GET(ELE_EVENT_COMMAND, event); + int ind = FIELD_GET(ELE_EVENT_IND, event); + int status = FIELD_GET(ELE_EVENT_STATUS, event); + const struct ele_str *ipc_str = get_idx(ARRAY_AND_SIZE(ele_ipc), ipc); + const struct ele_str *command_str = get_idx(ARRAY_AND_SIZE(ele_command), command); + const struct ele_str *ind_str = get_idx(ARRAY_AND_SIZE(ele_ind), ind); + const struct ele_str *status_str = get_idx(ARRAY_AND_SIZE(ele_status), status); + + pr_info("Event 0x%08x:\n", event); + pr_info(" IPC = %s (0x%02x)\n", ipc_str ? ipc_str->str : "INVALID", ipc); + pr_info(" CMD = %s (0x%02x)\n", command_str ? command_str->str : "INVALID", command); + pr_info(" IND = %s (0x%02x)\n", ind_str ? ind_str->str : "INVALID", ind); + pr_info(" STA = %s (0x%02x)\n", status_str ? status_str->str : "INVALID", status); +} + +#define AHAB_MAX_EVENTS 8 + +static int ahab_get_events(u32 *events) +{ + struct ele_msg msg; + int ret, i = 0; + u32 n_events; + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_EVENTS_REQ; + + ret = imx9_s3mua_call(&msg); + if (ret) { + pr_err("%s: ret %d, response 0x%x\n", __func__, ret, msg.data[0]); + + return ret; + } + + n_events = msg.data[1] & 0xffff; + + if (n_events > AHAB_MAX_EVENTS) + n_events = AHAB_MAX_EVENTS; + + for (; i < n_events; i++) + events[i] = msg.data[i + 2]; + + return n_events; +} + +unsigned int imx93_ahab_read_lifecycle(void) +{ + return readl(MX9_OCOTP_BASE_ADDR + 0x41c) & 0x3ff; +} + +static const char *ele_life_cycle(u32 lc) +{ + switch (lc) { + case ELE_LIFECYCLE_BLANK: return "BLANK"; + case ELE_LIFECYCLE_FAB: return "FAB"; + case ELE_LIFECYCLE_NXP_PROVISIONED: return "NXP Provisioned"; + case ELE_LIFECYCLE_OEM_OPEN: return "OEM Open"; + case ELE_LIFECYCLE_OEM_CLOSED: return "OEM closed"; + case ELE_LIFECYCLE_FIELD_RETURN_OEM: return "Field Return OEM"; + case ELE_LIFECYCLE_FIELD_RETURN_NXP: return "Field Return NXP"; + case ELE_LIFECYCLE_OEM_LOCKED: return "OEM Locked"; + case ELE_LIFECYCLE_BRICKED: return "BRICKED"; + default: return "Unknown"; + } +} + +int ele_print_events(void) +{ + unsigned int lc; + u32 events[AHAB_MAX_EVENTS]; + int i, ret; + + lc = imx93_ahab_read_lifecycle(); + pr_info("Current lifecycle: %s\n", ele_life_cycle(lc)); + + ret = ahab_get_events(events); + if (ret < 0) + return ret; + + if (!ret) { + pr_info("No Events Found!\n"); + return 0; + } + + for (i = 0; i < ret; i++) + display_event(events[i]); + + return 0; +} diff --git a/arch/arm/mach-imx/esdctl-v4.c b/arch/arm/mach-imx/esdctl-v4.c index d9f6e919a1..26f476f0f5 100644 --- a/arch/arm/mach-imx/esdctl-v4.c +++ b/arch/arm/mach-imx/esdctl-v4.c @@ -1,22 +1,12 @@ -/* - * esdctl-v4.c - i.MX sdram controller functions for i.MX53 - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* esdctl-v4.c - i.MX sdram controller functions for i.MX53 */ #include <common.h> #include <io.h> -#include <mach/esdctl-v4.h> -#include <mach/imx53-regs.h> +#include <mach/imx/esdctl-v4.h> +#include <mach/imx/imx53-regs.h> #include <asm/system.h> void imx_esdctlv4_do_write_leveling(void) diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 5d595addb8..701ca0ac1f 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -1,17 +1,7 @@ -/* - * esdctl.c - i.MX sdram controller functions - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* esdctl.c - i.MX sdram controller functions */ #include <common.h> #include <io.h> @@ -23,26 +13,29 @@ #include <linux/bitfield.h> #include <asm/barebox-arm.h> #include <asm/memory.h> -#include <mach/esdctl.h> -#include <mach/esdctl-v4.h> -#include <mach/imx6-mmdc.h> -#include <mach/imx1-regs.h> -#include <mach/imx21-regs.h> -#include <mach/imx25-regs.h> -#include <mach/imx27-regs.h> -#include <mach/imx31-regs.h> -#include <mach/imx35-regs.h> -#include <mach/imx51-regs.h> -#include <mach/imx53-regs.h> -#include <mach/imx6-regs.h> -#include <mach/vf610-ddrmc.h> -#include <mach/imx8m-regs.h> -#include <mach/imx7-regs.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/esdctl-v4.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx1-regs.h> +#include <mach/imx/imx21-regs.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx31-regs.h> +#include <mach/imx/imx35-regs.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/vf610-ddrmc.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/imx7-regs.h> +#include <mach/imx/imx9-regs.h> +#include <mach/imx/scratch.h> +#include <tee/optee.h> struct imx_esdctl_data { unsigned long base0; unsigned long base1; - void (*add_mem)(void *esdctlbase, struct imx_esdctl_data *); + int (*add_mem)(void *esdctlbase, struct imx_esdctl_data *); }; static int imx_esdctl_disabled; @@ -192,9 +185,11 @@ static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs) return memory_sdram_size(cols, rows, banks, width); } -static void add_mem(unsigned long base0, unsigned long size0, +static int add_mem(unsigned long base0, unsigned long size0, unsigned long base1, unsigned long size1) { + int ret0 = 0, ret1 = 0; + debug("%s: cs0 base: 0x%08lx cs0 size: 0x%08lx\n", __func__, base0, size0); debug("%s: cs1 base: 0x%08lx cs1 size: 0x%08lx\n", __func__, base1, size1); @@ -202,16 +197,16 @@ static void add_mem(unsigned long base0, unsigned long size0, /* * concatenate both chip selects to a single bank */ - arm_add_mem_device("ram0", base0, size0 + size1); - - return; + return arm_add_mem_device("ram0", base0, size0 + size1); } if (size0) - arm_add_mem_device("ram0", base0, size0); + ret0 = arm_add_mem_device("ram0", base0, size0); if (size1) - arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1); + ret1 = arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1); + + return ret0 ? ret0 : ret1; } /* @@ -234,35 +229,35 @@ static inline void imx_esdctl_v2_disable_default(void __iomem *esdctlbase) } } -static void imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data) +static int imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data) { - add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0), + return add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0), data->base1, imx_v1_sdram_size(esdctlbase, 1)); } -static void imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data) +static int imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data) { - add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0), + return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0), data->base1, imx_v2_sdram_size(esdctlbase, 1)); } -static void imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data) +static int imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data) { imx_esdctl_v2_disable_default(esdctlbase); - add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0), + return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0), data->base1, imx_v2_sdram_size(esdctlbase, 1)); } -static void imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data) +static int imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data) { - add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0), + return add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0), data->base1, imx_v3_sdram_size(esdctlbase, 1)); } -static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data) +static int imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data) { - add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0), + return add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0), data->base1, imx_v4_sdram_size(esdctlbase, 1)); } @@ -291,9 +286,9 @@ static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase) return size; } -static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +static int imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) { - arm_add_mem_device("ram0", data->base0, + return arm_add_mem_device("ram0", data->base0, imx6_mmdc_sdram_size(mmdcbase)); } @@ -313,9 +308,9 @@ static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc) return memory_sdram_size(cols, rows, banks, width); } -static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) { - arm_add_mem_device("ram0", data->base0, + return arm_add_mem_device("ram0", data->base0, vf610_ddrmc_sdram_size(mmdcbase)); } @@ -325,9 +320,11 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP0_CS_BIT0 GENMASK(4, 0) #define DDRC_MSTR 0x0000 +#define DDRC_MSTR_DDR4 BIT(4) #define DDRC_MSTR_LPDDR4 BIT(5) #define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12) #define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24) +#define DDRC_MSTR_DEVICE_CONFIG GENMASK(31, 30) #define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8) @@ -354,24 +351,31 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8) #define DDRC_ADDRMAP7_ROW_B16 GENMASK( 3, 0) +#define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8) +#define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0) + +#define DDRC_ADDRMAP_LENGTH 9 + static unsigned int imx_ddrc_count_bits(unsigned int bits, const u8 config[], unsigned int config_num) { unsigned int i; - for (i = 0; i < config_num && config[i] == 0b1111; i++) - bits--; + + for (i = 0; i < config_num; i++) { + if (config[i] == 0b1111) + bits--; + } return bits; } static resource_size_t -imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], +imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], u8 col_max, const u8 col_b[], unsigned int col_b_num, u8 row_max, const u8 row_b[], unsigned int row_b_num, - bool reduced_adress_space) + bool reduced_adress_space, unsigned int mstr) { - const u32 mstr = readl(ddrc + DDRC_MSTR); unsigned int banks, ranks, columns, rows, active_ranks, width; resource_size_t size; @@ -392,15 +396,22 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], BUG(); } + /* + * mstr is ignored for some SoCs/RAM types and may yield wrong + * results when used for calculation. Callers of this function + * are expected to fix it up as necessary. + * Bus width in bytes, 0 means half byte or 4-bit mode + */ + width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; + switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) { case 0b00: /* Full DQ bus */ - width = 4; break; - case 0b01: /* Half DQ bus */ - width = 2; + case 0b01: /* Half DQ bus */ + width >>= 1; break; case 0b10: /* Quarter DQ bus */ - width = 1; + width >>= 2; break; default: BUG(); @@ -417,17 +428,43 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111) banks++; + if (mstr & DDRC_MSTR_DDR4) { + /* FIXME: DDR register spreasheet claims this to be + * 6-bit and 63 meaning bank group address bit 0 is 0, + * but reference manual claims 5-bit without 'neutral' value + * See MX8M_Mini_DDR4_RPA_v17, MX8M_Nano_DDR4_RPA_v8 + */ + if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111) + banks++; + if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111) + banks++; + } + columns = imx_ddrc_count_bits(col_max, col_b, col_b_num); rows = imx_ddrc_count_bits(row_max, row_b, row_b_num); - size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks; + /* + * Special case when bus width is 0 or x4 mode, + * calculate the mem size and then divide the size by 2. + */ + if (width) + size = memory_sdram_size(columns, rows, 1 << banks, width); + else + size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1; + size <<= ranks; return reduced_adress_space ? size * 3 / 4 : size; } -static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) +static void imx_ddrc_set_mstr_device_config(u32 *mstr, unsigned bits) +{ + *mstr &= ~DDRC_MSTR_DEVICE_CONFIG; + *mstr |= FIELD_PREP(DDRC_MSTR_DEVICE_CONFIG, fls(bits / 8)); +} + +static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswidth) { - const u32 addrmap[] = { + const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { readl(ddrc + DDRC_ADDRMAP(0)), readl(ddrc + DDRC_ADDRMAP(1)), readl(ddrc + DDRC_ADDRMAP(2)), @@ -435,7 +472,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) readl(ddrc + DDRC_ADDRMAP(4)), readl(ddrc + DDRC_ADDRMAP(5)), readl(ddrc + DDRC_ADDRMAP(6)), - readl(ddrc + DDRC_ADDRMAP(7)) + readl(ddrc + DDRC_ADDRMAP(7)), + readl(ddrc + DDRC_ADDRMAP(8)) }; const u8 col_b[] = { /* @@ -453,15 +491,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]), }; const u8 row_b[] = { - /* - * FIXME: RM mentions the following fields as being - * present, but looking at the code generated by DDR - * tool it doesn't look like those registers are - * really implemented/used. - * - * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), - * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), - */ + FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), + FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]), @@ -470,22 +501,105 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) }; const bool reduced_adress_space = FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]); + u32 mstr = readl(ddrc + DDRC_MSTR); + + /* Device config is ignored and taken as 32-bit for LPDDR4 */ + if (mstr & DDRC_MSTR_LPDDR4) + imx_ddrc_set_mstr_device_config(&mstr, buswidth); return imx_ddrc_sdram_size(ddrc, addrmap, 12, ARRAY_AND_SIZE(col_b), - 16, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + 18, ARRAY_AND_SIZE(row_b), + reduced_adress_space, mstr); } -static void imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +static int _imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data, + unsigned int buswidth) { - arm_add_mem_device("ram0", data->base0, - imx8m_ddrc_sdram_size(mmdcbase)); + resource_size_t size = imx8m_ddrc_sdram_size(mmdcbase, buswidth); + resource_size_t size0, size1; + int ret; + + /* + * Split the available memory into multiple banks if the device does + * have more RAM than 3G. At the moment this is necessary to prevent + * memory_bank_first_find_space() from finding free space near the end + * of the 4G barrier which is the case in a 6G/8G setup. This is + * important for larger barebox-pbl binaries (e.g. debug enabled) and + * the barebox chainloading mechanism since the pbl init the MMU to 4G. + * In this case a MMU exception will be thrown if the barebox-pbl is + * placed near the 4G barrier. + */ + size0 = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size); + size1 = size - size0; + + ret = arm_add_mem_device("ram0", data->base0, size0); + if (ret || size1 == 0) + return ret; + +#ifdef CONFIG_64BIT + /* + * Albeit this hook is called on 64bit machines only, the driver serves + * 32bit machines as well. Guard the code to avoid compiler warnings. + */ + ret = arm_add_mem_device("ram1", SZ_4G, size1); +#endif + + return ret; +} + +static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + return _imx8m_ddrc_add_mem(mmdcbase, data, 32); +} + +static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + return _imx8m_ddrc_add_mem(mmdcbase, data, 16); +} + +#define IMX9_DDRC_CS_CONFIG(n) (0x80 + (n) * 4) +#define IMX9_DDRC_CS_ROW_BITS GENMASK(10, 8) +#define IMX9_DDRC_CS_COL_BITS GENMASK(2, 0) +#define IMX9_DDRC_CS_EN BIT(31) + +resource_size_t imx9_ddrc_sdram_size(void) +{ + void __iomem *mmdcbase = IOMEM(MX9_DDR_CTL_BASE); + int width = 2; + int banks = 8; + resource_size_t mem = 0; + int i; + + for (i = 0; i < 2; i++) { + int rows, cols; + u32 cs, col_bits; + + cs = readl(mmdcbase + IMX9_DDRC_CS_CONFIG(i)); + if (!(cs & IMX9_DDRC_CS_EN)) + continue; + + rows = FIELD_GET(IMX9_DDRC_CS_ROW_BITS, cs) + 12; + col_bits = FIELD_GET(IMX9_DDRC_CS_COL_BITS, cs); + if (col_bits == 7) + cols = 7; + else + cols = col_bits + 8; + + mem += memory_sdram_size(cols, rows, banks, width); + } + + return mem; +} + +static int imx9_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + return arm_add_mem_device("ram0", data->base0, imx9_ddrc_sdram_size()); } static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) { - const u32 addrmap[] = { + const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { readl(ddrc + DDRC_ADDRMAP(0)), readl(ddrc + DDRC_ADDRMAP(1)), readl(ddrc + DDRC_ADDRMAP(2)), @@ -512,20 +626,24 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) }; const bool reduced_adress_space = FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]); + u32 mstr = readl(ddrc + DDRC_MSTR); + + /* Device config is unused on i.MX7, so rewrite it as 32-bit wide */ + imx_ddrc_set_mstr_device_config(&mstr, 32); return imx_ddrc_sdram_size(ddrc, addrmap, 11, ARRAY_AND_SIZE(col_b), 15, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + reduced_adress_space, mstr); } -static void imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) { - arm_add_mem_device("ram0", data->base0, + return arm_add_mem_device("ram0", data->base0, imx7d_ddrc_sdram_size(mmdcbase)); } -static int imx_esdctl_probe(struct device_d *dev) +static int imx_esdctl_probe(struct device *dev) { struct resource *iores; struct imx_esdctl_data *data; @@ -544,9 +662,7 @@ static int imx_esdctl_probe(struct device_d *dev) if (imx_esdctl_disabled) return 0; - data->add_mem(base, data); - - return 0; + return data->add_mem(base, data); } static __maybe_unused struct imx_esdctl_data imx1_data = { @@ -611,11 +727,21 @@ static __maybe_unused struct imx_esdctl_data vf610_data = { .add_mem = vf610_ddrmc_add_mem, }; -static __maybe_unused struct imx_esdctl_data imx8mq_data = { +static __maybe_unused struct imx_esdctl_data imx8m_data = { .base0 = MX8M_DDR_CSD1_BASE_ADDR, .add_mem = imx8m_ddrc_add_mem, }; +static __maybe_unused struct imx_esdctl_data imx8mn_data = { + .base0 = MX8M_DDR_CSD1_BASE_ADDR, + .add_mem = imx8mn_ddrc_add_mem, +}; + +static __maybe_unused struct imx_esdctl_data imx9_data = { + .base0 = MX9_DDR_CSD1_BASE_ADDR, + .add_mem = imx9_ddrc_add_mem, +}; + static __maybe_unused struct imx_esdctl_data imx7d_data = { .base0 = MX7_DDR_BASE_ADDR, .add_mem = imx7d_ddrc_add_mem, @@ -686,8 +812,14 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { .compatible = "fsl,vf610-ddrmc", .data = &vf610_data }, { - .compatible = "fsl,imx8mq-ddrc", - .data = &imx8mq_data + .compatible = "fsl,imx8m-ddrc", + .data = &imx8m_data + }, { + .compatible = "fsl,imx8mn-ddrc", + .data = &imx8mn_data + }, { + .compatible = "fsl,imx93-ddrc", + .data = &imx9_data }, { .compatible = "fsl,imx7d-ddrc", .data = &imx7d_data @@ -695,20 +827,15 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, imx_esdctl_dt_ids); -static struct driver_d imx_esdctl_driver = { +static struct driver imx_esdctl_driver = { .name = "imx-esdctl", .probe = imx_esdctl_probe, .id_table = imx_esdctl_ids, .of_compatible = DRV_OF_COMPAT(imx_esdctl_dt_ids), }; - -static int imx_esdctl_init(void) -{ - return platform_driver_register(&imx_esdctl_driver); -} - -mem_initcall(imx_esdctl_init); +mem_platform_driver(imx_esdctl_driver); /* * The i.MX SoCs usually have two SDRAM chipselects. The following @@ -866,11 +993,11 @@ void __noreturn vf610_barebox_entry(void *boarddata) boarddata); } -static void __noreturn imx8m_barebox_entry(void *boarddata) +resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth) { resource_size_t size; - size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR)); + size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth); /* * We artificially limit detected memory size to force malloc * pool placement to be within 4GiB address space, so as to @@ -880,18 +1007,35 @@ static void __noreturn imx8m_barebox_entry(void *boarddata) * pool placement. The rest of the system should be able to * detect and utilize full amount of memory. */ - size = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size); - barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, size, boarddata); + return min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size); +} + +static void __noreturn imx8m_barebox_entry(void *boarddata, unsigned buswidth) +{ + imx8m_init_scratch_space(buswidth, false); + optee_set_membase(imx_scratch_get_optee_hdr()); + barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, + imx8m_barebox_earlymem_size(buswidth), boarddata); } void __noreturn imx8mm_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 32); +} + +void __noreturn imx8mn_barebox_entry(void *boarddata) +{ + imx8m_barebox_entry(boarddata, 16); +} + +void __noreturn imx8mp_barebox_entry(void *boarddata) +{ + imx8m_barebox_entry(boarddata, 32); } void __noreturn imx8mq_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 32); } void __noreturn imx7d_barebox_entry(void *boarddata) @@ -901,4 +1045,11 @@ void __noreturn imx7d_barebox_entry(void *boarddata) boarddata); } +void __noreturn imx93_barebox_entry(void *boarddata) +{ + imx93_init_scratch_space(false); + optee_set_membase(imx_scratch_get_optee_hdr()); + barebox_arm_entry(MX9_DDR_CSD1_BASE_ADDR, + imx9_ddrc_sdram_size(), boarddata); +} diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 123589c071..79cedbd68a 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -1,32 +1,22 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> #include <io.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/imx-nand.h> -#include <mach/esdctl.h> -#include <mach/generic.h> -#include <mach/imx21-regs.h> -#include <mach/imx25-regs.h> -#include <mach/imx27-regs.h> -#include <mach/imx31-regs.h> -#include <mach/imx35-regs.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx21-regs.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx31-regs.h> +#include <mach/imx/imx35-regs.h> #define BARE_INIT_FUNCTION(name) \ __section(.text_bare_init_##name) \ diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index 2f9ffbd271..f4581396b1 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -1,19 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2010 Baruch Siach <baruch@tkos.co.il>, Orex Computed Radiography + /* * iim.c - i.MX IIM fusebox driver * * Provide an interface for programming and sensing the information that are * stored in on-chip fuse elements. This functionality is part of the IC * Identification Module (IIM), which is present on some i.MX CPUs. - * - * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, - * Orex Computed Radiography - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> @@ -26,15 +19,16 @@ #include <malloc.h> #include <of.h> #include <io.h> -#include <regmap.h> +#include <linux/regmap.h> #include <regulator.h> #include <linux/err.h> +#include <machine_id.h> -#include <mach/iim.h> -#include <mach/imx51-regs.h> -#include <mach/imx53-regs.h> -#include <mach/clock-imx51_53.h> -#include <mach/imx25-fusemap.h> +#include <mach/imx/iim.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/imx25-fusemap.h> #define DRIVERNAME "imx_iim" #define IIM_NUM_BANKS 8 @@ -50,7 +44,7 @@ struct iim_bank { }; struct iim_priv { - struct device_d dev; + struct device dev; void __iomem *base; void __iomem *bankbase; struct iim_bank *bank[IIM_NUM_BANKS]; @@ -298,7 +292,7 @@ err_out: return ret; } -static ssize_t imx_iim_reg_write(void *ctx, unsigned int reg, unsigned int val) +static int imx_iim_reg_write(void *ctx, unsigned int reg, unsigned int val) { struct iim_bank *bank = ctx; @@ -411,11 +405,11 @@ static void imx_iim_add_mac_param(struct iim_priv *iim, int macnum, int bank, in */ #define MAC_ADDRESS_PROPLEN (3 * sizeof(__be32)) -static void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim) +static void imx_iim_init_dt(struct device *dev, struct iim_priv *iim) { char mac[6]; const __be32 *prop; - struct device_node *node = dev->device_node; + struct device_node *node = dev->of_node; int len, ret, macnum = 0; if (!node) @@ -449,12 +443,12 @@ static void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim) } } #else -static inline void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim) +static inline void imx_iim_init_dt(struct device *dev, struct iim_priv *iim) { } #endif -static int imx_iim_probe(struct device_d *dev) +static int imx_iim_probe(struct device *dev) { struct resource *iores; struct iim_priv *iim; @@ -511,6 +505,25 @@ static int imx_iim_probe(struct device_d *dev) dev_add_param_bool(&iim->dev, "explicit_sense_enable", NULL, NULL, &iim->sense_enable, NULL); + /* Maybe this is too strict? This might also work on i.MX31 and i.MX35 */ + if (IS_ENABLED(CONFIG_MACHINE_ID) && + of_device_is_compatible(dev->of_node, "fsl,imx25-iim")) { + char uid[8]; + + for (i = 0; i < 8; ++i) { + unsigned int value; + + ret = imx_iim_read_field(IMX25_IIM_UID(i), &value); + if (ret) + break; + + uid[i] = value; + } + + if (!ret) + machine_id_set_hashable(uid, 8); + } + return 0; } @@ -579,17 +592,12 @@ static __maybe_unused struct of_device_id imx_iim_dt_ids[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, imx_iim_dt_ids); -static struct driver_d imx_iim_driver = { +static struct driver imx_iim_driver = { .name = DRIVERNAME, .probe = imx_iim_probe, .of_compatible = DRV_OF_COMPAT(imx_iim_dt_ids), }; -static int imx_iim_init(void) -{ - platform_driver_register(&imx_iim_driver); - - return 0; -} -coredevice_initcall(imx_iim_init); +coredevice_platform_driver(imx_iim_driver); diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c index 8aa4f152a1..7523008cdb 100644 --- a/arch/arm/mach-imx/imx-bbu-external-nand.c +++ b/arch/arm/mach-imx/imx-bbu-external-nand.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + /* * imx-bbu-external-nand.c - i.MX specific update functions for external * nand boot - * - * Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -25,8 +17,8 @@ #include <linux/mtd/mtd-abi.h> #include <linux/stat.h> #include <ioctl.h> -#include <mach/bbu.h> -#include <mach/imx-nand.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx-nand.h> #include <asm/barebox-arm-head.h> static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_data *data) @@ -37,9 +29,9 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ int size_available, size_need; int ret; uint32_t num_bb = 0, bbt = 0; - loff_t offset = 0; + loff_t nand_offset = 0, image_offset = 0; int block = 0, len, now, blocksize; - void *image = data->image; + void *image = NULL; ret = stat(data->devicefile, &s); if (ret) @@ -55,6 +47,12 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ if (ret) goto out; + image = memdup(data->image, data->len); + if (!image) { + ret = -ENOMEM; + goto out; + } + blocksize = meminfo.erasesize; size_need = data->len; @@ -63,27 +61,27 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ * Collect bad blocks and construct BBT */ while (size_need > 0) { - ret = ioctl(fd, MEMGETBADBLOCK, &offset); + ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset); if (ret < 0) goto out; if (ret) { - if (!offset) { + if (!nand_offset) { printf("1st block is bad. This is not supported\n"); ret = -EINVAL; goto out; } - debug("bad block at 0x%08llx\n", offset); + debug("bad block at 0x%08llx\n", nand_offset); num_bb++; bbt |= (1 << block); - offset += blocksize; + nand_offset += blocksize; block++; continue; } size_need -= blocksize; size_available -= blocksize; - offset += blocksize; + nand_offset += blocksize; block++; if (size_available < 0) { @@ -126,7 +124,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ } len = data->len; - offset = 0; + nand_offset = 0; /* last chance before erasing the flash */ ret = bbu_confirm(data); @@ -139,13 +137,13 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ while (len > 0) { now = min(len, blocksize); - ret = ioctl(fd, MEMGETBADBLOCK, &offset); + ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset); if (ret < 0) goto out; if (ret) { - offset += blocksize; - if (lseek(fd, offset, SEEK_SET) != offset) { + nand_offset += blocksize; + if (lseek(fd, nand_offset, SEEK_SET) != nand_offset) { ret = -errno; goto out; } @@ -153,25 +151,26 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ continue; } - debug("writing %d bytes at 0x%08llx\n", now, offset); + debug("writing %d bytes at 0x%08llx\n", now, nand_offset); - ret = erase(fd, blocksize, offset); + ret = erase(fd, blocksize, nand_offset); if (ret) goto out; - ret = write(fd, image, now); + ret = write(fd, image + image_offset, now); if (ret < 0) goto out; len -= now; - image += now; - offset += now; + image_offset += now; + nand_offset += now; } ret = 0; out: close(fd); + free(image); return ret; } diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index a922470988..8cdaab5c16 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + /* * imx-bbu-internal.c - i.MX specific update functions for internal boot - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -25,17 +17,17 @@ #include <linux/stat.h> #include <ioctl.h> #include <environment.h> -#include <mach/bbu.h> -#include <mach/generic.h> +#include <mach/imx/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx-header.h> #include <libfile.h> -#define IMX_INTERNAL_FLAG_ERASE BIT(30) - struct imx_internal_bbu_handler { struct bbu_handler handler; int (*write_device)(struct imx_internal_bbu_handler *, struct bbu_data *); unsigned long flash_header_offset; + unsigned long filetype_offset; size_t device_size; enum filetype expected_type; }; @@ -43,7 +35,7 @@ struct imx_internal_bbu_handler { static bool imx_bbu_erase_required(struct imx_internal_bbu_handler *imx_handler) { - return imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE; + return imx_handler->handler.flags & IMX_BBU_FLAG_ERASE; } static int imx_bbu_protect(int fd, struct imx_internal_bbu_handler *imx_handler, @@ -171,8 +163,8 @@ static int imx_bbu_check_prereq(struct imx_internal_bbu_handler *imx_handler, if (expected_type == filetype_unknown) break; - blob = data->image + imx_handler->flash_header_offset; - len = data->len - imx_handler->flash_header_offset; + blob = data->image + imx_handler->filetype_offset; + len = data->len - imx_handler->filetype_offset; type = file_detect_type(blob, len); if (type != expected_type) { @@ -384,16 +376,33 @@ static enum filetype imx_bbu_expected_filetype(void) static unsigned long imx_bbu_flash_header_offset_mmc(void) { - unsigned long offset = SZ_1K; + /* + * i.MX8MQ moved the header by 32K to accomodate for GPT partition + * tables. The offset to the IVT is 1KiB. + */ + if (cpu_is_mx8mm() || cpu_is_mx8mq()) + return SZ_32K + SZ_1K; /* - * i.MX8MQ moved the header by 32K to accomodate for GPT - * partition tables + * i.MX8MN/P moved the header by 32K to accomodate for GPT partition + * tables, but the IVT is right at the beginning of the image. */ - if (cpu_is_mx8m()) - offset += SZ_32K; + if (cpu_is_mx8mn() || cpu_is_mx8mp()) + return SZ_32K; - return offset; + return SZ_1K; +} + +static unsigned long imx_bbu_flash_header_offset_mmcboot(unsigned long *flags) +{ + /* + * i.MX8MN/P places IVT directly at start of eMMC boot partition. IVT + * in eMMC user partition and SD is at 32K offset. + */ + if (cpu_is_mx8mn() || cpu_is_mx8mp()) + *flags |= IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER; + + return imx_bbu_flash_header_offset_mmc(); } static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) @@ -413,54 +422,12 @@ static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) static int imx_bbu_internal_mmcboot_update(struct bbu_handler *handler, struct bbu_data *data) { - struct bbu_data _data = *data; int ret; - char *bootpartvar; - const char *bootpart; - char *devicefile; - const char *devname = devpath_to_name(data->devicefile); - - ret = device_detect_by_name(devname); - if (ret) { - pr_err("Couldn't detect device '%s'\n", devname); - return ret; - } - - ret = asprintf(&bootpartvar, "%s.boot", devname); - if (ret < 0) - return ret; - - bootpart = getenv(bootpartvar); - if (!bootpart) { - pr_err("Couldn't read the value of '%s'\n", bootpartvar); - ret = -ENOENT; - goto free_bootpartvar; - } - - if (!strcmp(bootpart, "boot0")) { - bootpart = "boot1"; - } else { - bootpart = "boot0"; - } - ret = asprintf(&devicefile, "/dev/%s.%s", devname, bootpart); - if (ret < 0) - goto free_bootpartvar; + ret = bbu_mmcboot_handler(handler, data, imx_bbu_update); - _data.devicefile = devicefile; - - ret = imx_bbu_update(handler, &_data); - if (ret) - goto free_devicefile; - - /* on success switch boot source */ - ret = setenv(bootpartvar, bootpart); - -free_devicefile: - free(devicefile); - -free_bootpartvar: - free(bootpartvar); + if (ret == -ENOENT) + pr_err("Couldn't read the value of .boot parameter\n"); return ret; } @@ -505,6 +472,7 @@ imx_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, imx_handler = __init_handler(name, devicefile, flags | IMX_BBU_FLAG_KEEP_HEAD); imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); + imx_handler->filetype_offset = imx_handler->flash_header_offset; return __register_handler(imx_handler); } @@ -517,8 +485,9 @@ imx_bbu_internal_spi_i2c_register_handler(const char *name, struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags | - IMX_INTERNAL_FLAG_ERASE); + IMX_BBU_FLAG_ERASE); imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); + imx_handler->filetype_offset = imx_handler->flash_header_offset; return __register_handler(imx_handler); } @@ -564,6 +533,7 @@ int imx53_bbu_internal_nand_register_handler(const char *name, imx_handler = __init_handler(name, "/dev/nand0", flags); imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); + imx_handler->filetype_offset = imx_handler->flash_header_offset; imx_handler->device_size = partition_size; imx_handler->write_device = imx_bbu_internal_v2_write_nand_dbbt; @@ -588,9 +558,9 @@ int vf610_bbu_internal_mmc_register_handler(const char *name, __alias(imx6_bbu_internal_mmc_register_handler); /* - * Register an i.MX8MQ internal boot update handler for MMC/SD + * Register an i.MX8M* internal boot update handler for MMC/SD */ -int imx8mq_bbu_internal_mmc_register_handler(const char *name, +int imx8m_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags) __alias(imx6_bbu_internal_mmc_register_handler); @@ -609,9 +579,13 @@ static int imx_bbu_internal_mmcboot_register_handler(const char *name, unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; + unsigned long flash_header_offset; + + flash_header_offset = imx_bbu_flash_header_offset_mmcboot(&flags); imx_handler = __init_handler(name, devicefile, flags); - imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); + imx_handler->flash_header_offset = flash_header_offset; + imx_handler->filetype_offset = flash_header_offset; imx_handler->handler.handler = imx_bbu_internal_mmcboot_update; @@ -638,7 +612,7 @@ int imx7_bbu_internal_mmcboot_register_handler(const char *name, unsigned long flags) __alias(imx_bbu_internal_mmcboot_register_handler); -int imx8mq_bbu_internal_mmcboot_register_handler(const char *name, +int imx8m_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, unsigned long flags) __alias(imx_bbu_internal_mmcboot_register_handler); @@ -676,9 +650,40 @@ int imx_bbu_external_nor_register_handler(const char *name, struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags | - IMX_INTERNAL_FLAG_ERASE); + IMX_BBU_FLAG_ERASE); imx_handler->expected_type = filetype_unknown; return __register_handler(imx_handler); } + +static unsigned long imx_bbu_filetype_offset_flexspi(void) +{ + unsigned int sd_flash_header_gap = SZ_32K; + + if (cpu_is_mx8mm()) + return sd_flash_header_gap; + + return sd_flash_header_gap + SZ_1K; +} + +static int +imx_bbu_internal_flexspi_nor_register_handler(const char *name, + const char *devicefile, + unsigned long flags) +{ + struct imx_internal_bbu_handler *imx_handler; + + flags |= IMX_BBU_FLAG_ERASE | IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER; + imx_handler = __init_handler(name, devicefile, flags); + imx_handler->flash_header_offset = SZ_32K; + imx_handler->expected_type = filetype_nxp_fspi_image; + imx_handler->filetype_offset = imx_bbu_filetype_offset_flexspi(); + + return __register_handler(imx_handler); +} + +int imx8m_bbu_internal_flexspi_nor_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_flexspi_nor_register_handler); diff --git a/arch/arm/mach-imx/imx-udc.c b/arch/arm/mach-imx/imx-udc.c new file mode 100644 index 0000000000..a5364decb1 --- /dev/null +++ b/arch/arm/mach-imx/imx-udc.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/usb/ch9.h> +#include <soc/fsl/fsl_udc.h> +#include <mach/imx/imx8mm-regs.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx7-regs.h> + +static void fsl_queue_td(struct usb_dr_device *dr, struct ep_td_struct *dtd, + int ep_is_in) +{ + int ep_index = 0; + int i = ep_index * 2 + ep_is_in; + u32 bitmask; + volatile struct ep_queue_head *dQH = + (void *)(unsigned long)readl(&dr->endpointlistaddr); + unsigned long td_dma = (unsigned long)dtd; + + dQH = &dQH[i]; + + bitmask = ep_is_in ? (1 << (ep_index + 16)) : (1 << (ep_index)); + + dQH->next_dtd_ptr = cpu_to_le32(td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK); + + dQH->size_ioc_int_sts &= cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE + | EP_QUEUE_HEAD_STATUS_HALT)); + + writel(bitmask, &dr->endpointprime); +} + +static struct ep_td_struct dtd_data __attribute__((aligned(64))); +static struct ep_td_struct dtd_status __attribute__((aligned(64))); + +static int fsl_ep_queue(struct usb_dr_device *dr, struct ep_td_struct *dtd, + void *buf, int len) +{ + u32 swap_temp; + + memset(dtd, 0, sizeof(*dtd)); + + /* Clear reserved field */ + swap_temp = cpu_to_le32(dtd->size_ioc_sts); + swap_temp &= ~DTD_RESERVED_FIELDS; + dtd->size_ioc_sts = cpu_to_le32(swap_temp); + + swap_temp = (unsigned long)buf; + dtd->buff_ptr0 = cpu_to_le32(swap_temp); + dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000); + dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000); + dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000); + dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000); + + /* Fill in the transfer size; set active bit */ + swap_temp = ((len << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE) | DTD_IOC; + + writel(cpu_to_le32(swap_temp), &dtd->size_ioc_sts); + + dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE); + + fsl_queue_td(dr, dtd, len ? 0 : 1); + + return 0; +} + +enum state { + state_init = 0, + state_expect_command, + state_transfer_data, + state_complete, +}; + +#define MAX_TRANSFER_SIZE 2048 + +static enum state state; +static uint8_t databuf[MAX_TRANSFER_SIZE] __attribute__((aligned(64))); +static int actual; +static int to_transfer; +static void *image; + +static void tripwire_handler(struct usb_dr_device *dr, u8 ep_num) +{ + uint32_t val; + struct ep_queue_head *qh; + struct ep_queue_head *dQH = (void *)(unsigned long)readl(&dr->endpointlistaddr); + struct usb_ctrlrequest *ctrl; + + qh = &dQH[ep_num * 2]; + + val = readl(&dr->endptsetupstat); + val |= 1 << ep_num; + writel(val, &dr->endptsetupstat); + + do { + val = readl(&dr->usbcmd); + val |= USB_CMD_SUTW; + writel(val, &dr->usbcmd); + + ctrl = (void *)qh->setup_buffer; + if ((ctrl->wValue & 0xff) == 1) + state = state_expect_command; + + } while (!(readl(&dr->usbcmd) & USB_CMD_SUTW)); + + val = readl(&dr->usbcmd); + val &= ~USB_CMD_SUTW; + writel(val, &dr->usbcmd); + + fsl_ep_queue(dr, &dtd_data, databuf, MAX_TRANSFER_SIZE); +} + +static void dtd_complete_irq(struct usb_dr_device *dr) +{ + struct ep_td_struct *dtd = &dtd_data; + u32 bit_pos; + int len; + + /* Clear the bits in the register */ + bit_pos = readl(&dr->endptcomplete); + writel(bit_pos, &dr->endptcomplete); + + if (!(bit_pos & 1)) + return; + + len = MAX_TRANSFER_SIZE - + (le32_to_cpu(dtd->size_ioc_sts) >> DTD_LENGTH_BIT_POS); + + if (state == state_expect_command) { + state = state_transfer_data; + to_transfer = databuf[8] << 24 | + databuf[9] << 16 | + databuf[10] << 8 | + databuf[11]; + } else { + memcpy(image + actual, &databuf[1], len - 1); + actual += len - 1; + to_transfer -= len - 1; + + if (to_transfer <= 0) + state = state_complete; + } + + fsl_ep_queue(dr, &dtd_status, NULL, 0); +} + +static int usb_irq(struct usb_dr_device *dr) +{ + uint32_t irq_src = readl(&dr->usbsts); + + irq_src &= ~0x80; + + if (!irq_src) + return -EAGAIN; + + /* Clear notification bits */ + writel(irq_src, &dr->usbsts); + + /* USB Interrupt */ + if (irq_src & USB_STS_INT) { + /* Setup package, we only support ep0 as control ep */ + if (readl(&dr->endptsetupstat) & EP_SETUP_STATUS_EP0) + tripwire_handler(dr, 0); + + /* completion of dtd */ + if (readl(&dr->endptcomplete)) + dtd_complete_irq(dr); + } + + if (state == state_complete) + return 0; + else + return -EAGAIN; +} + +int imx_barebox_load_usb(void __iomem *dr, void *dest) +{ + int ret; + + image = dest; + + while (1) { + ret = usb_irq(dr); + if (!ret) + break; + } + + return 0; +} + +int imx_barebox_start_usb(void __iomem *dr, void *dest) +{ + void __noreturn (*bb)(void); + int ret; + + ret = imx_barebox_load_usb(dr, dest); + if (ret) + return ret; + + printf("Downloading complete, start barebox\n"); + bb = dest; + bb(); +} + +int imx6_barebox_load_usb(void *dest) +{ + return imx_barebox_load_usb(IOMEM(MX6_OTG_BASE_ADDR), dest); +} + +int imx6_barebox_start_usb(void *dest) +{ + return imx_barebox_start_usb(IOMEM(MX6_OTG_BASE_ADDR), dest); +} + +int imx7_barebox_load_usb(void *dest) +{ + return imx_barebox_load_usb(IOMEM(MX7_OTG1_BASE_ADDR), dest); +} + +int imx7_barebox_start_usb(void *dest) +{ + return imx_barebox_start_usb(IOMEM(MX7_OTG1_BASE_ADDR), dest); +} + +int imx8mm_barebox_load_usb(void *dest) +{ + return imx_barebox_load_usb(IOMEM(MX8MM_USB1_BASE_ADDR), dest); +} + +int imx8mm_barebox_start_usb(void *dest) +{ + return imx_barebox_start_usb(IOMEM(MX8MM_USB1_BASE_ADDR), dest); +} diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 0bbe44e4dd..f3491c6df7 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <of.h> #include <init.h> #include <io.h> -#include <mach/revision.h> -#include <mach/generic.h> -#include <mach/reset-reason.h> +#include <mach/imx/revision.h> +#include <mach/imx/generic.h> +#include <mach/imx/reset-reason.h> static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN; @@ -82,6 +71,12 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX8MQ; if (of_machine_is_compatible("fsl,imx8mm")) return IMX_CPU_IMX8MM; + if (of_machine_is_compatible("fsl,imx8mn")) + return IMX_CPU_IMX8MN; + if (of_machine_is_compatible("fsl,imx8mp")) + return IMX_CPU_IMX8MP; + if (of_machine_is_compatible("fsl,imx93")) + return IMX_CPU_IMX93; if (of_machine_is_compatible("fsl,vf610")) return IMX_CPU_VF610; @@ -100,6 +95,10 @@ static int imx_init(void) return 0; } + /* + * Don't add new SoCs to this list, instead use the new + * soc framework (see soc-imx8m.c). + */ if (cpu_is_mx1()) ret = imx1_init(); else if (cpu_is_mx21()) @@ -123,9 +122,15 @@ static int imx_init(void) else if (cpu_is_mx7()) ret = imx7_init(); else if (cpu_is_mx8mm()) - ret = imx8mm_init(); + ret = 0; + else if (cpu_is_mx8mn()) + ret = 0; + else if (cpu_is_mx8mp()) + ret = 0; else if (cpu_is_mx8mq()) - ret = imx8mq_init(); + ret = 0; + else if (cpu_is_mx93()) + ret = imx93_init(); else if (cpu_is_vf610()) ret = vf610_init(); else @@ -205,6 +210,6 @@ void imx_set_reset_reason(void __iomem *srsr, reset_source_set_prinst(type, RESET_SOURCE_DEFAULT_PRIORITY, instance); - pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n", - reset_source_to_string(type), reg); + pr_debug("i.MX reset reason %s (SRSR: 0x%08x)\n", + reset_source_to_string(type), reg); } diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c index 6a09b276c8..817095da82 100644 --- a/arch/arm/mach-imx/imx1.c +++ b/arch/arm/mach-imx/imx1.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> #include <io.h> -#include <mach/imx1-regs.h> -#include <mach/weim.h> -#include <mach/iomux-v1.h> -#include <mach/generic.h> +#include <mach/imx/imx1-regs.h> +#include <mach/imx/weim.h> +#include <mach/imx/iomux-v1.h> +#include <mach/imx/generic.h> #include <reset_source.h> #define MX1_RSR MX1_SCM_BASE_ADDR @@ -50,7 +39,7 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower) writel(lower, MX1_EIM_BASE_ADDR + 4 + cs * 8); } -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> int imx1_init(void) { diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index 7a19ed3986..4271fb92d7 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> #include <io.h> -#include <mach/imx21-regs.h> -#include <mach/weim.h> -#include <mach/iomux-v1.h> -#include <mach/generic.h> +#include <mach/imx/imx21-regs.h> +#include <mach/imx/weim.h> +#include <mach/imx/iomux-v1.h> +#include <mach/imx/generic.h> void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower) { diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index d27680e428..2f6d6f0523 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> -#include <mach/imx25-regs.h> -#include <mach/iim.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/iim.h> #include <io.h> -#include <mach/weim.h> -#include <mach/generic.h> +#include <mach/imx/weim.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #define MX25_BOOTROM_HAB_MAGIC 0x3c95cac6 diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index d4949babeb..4dcc2e028e 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> -#include <mach/imx27-regs.h> -#include <mach/weim.h> -#include <mach/iomux-v1.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/weim.h> +#include <mach/imx/iomux-v1.h> #include <linux/sizes.h> -#include <mach/revision.h> -#include <mach/generic.h> +#include <mach/imx/revision.h> +#include <mach/imx/generic.h> #include <init.h> #include <io.h> diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 137c77a923..20ca9299f1 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> #include <linux/sizes.h> #include <io.h> -#include <mach/imx31-regs.h> -#include <mach/weim.h> -#include <mach/generic.h> +#include <mach/imx/imx31-regs.h> +#include <mach/imx/weim.h> +#include <mach/imx/generic.h> void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional) diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index d37bdfda7b..29b77b42c2 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -1,25 +1,14 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <linux/sizes.h> #include <init.h> #include <io.h> -#include <mach/weim.h> -#include <mach/imx35-regs.h> -#include <mach/iim.h> -#include <mach/revision.h> -#include <mach/generic.h> +#include <mach/imx/weim.h> +#include <mach/imx/imx35-regs.h> +#include <mach/imx/iim.h> +#include <mach/imx/revision.h> +#include <mach/imx/generic.h> void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional) diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c index 96288f99e0..10a3ae7bca 100644 --- a/arch/arm/mach-imx/imx5.c +++ b/arch/arm/mach-imx/imx5.c @@ -1,8 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <io.h> #include <linux/sizes.h> -#include <mach/imx5.h> -#include <mach/clock-imx51_53.h> +#include <mach/imx/imx5.h> +#include <mach/imx/clock-imx51_53.h> void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn) { @@ -37,10 +39,13 @@ void imx5_init_lowlevel(void) { u32 r; - /* ARM errata ID #468414 */ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r)); + + if (r & (1 << 1)) + return; + + /* ARM errata ID #468414 */ r |= (1 << 5); /* enable L1NEON bit */ - r &= ~(1 << 1); /* explicitly disable L2 cache */ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r)); /* reconfigure L2 cache aux control reg */ diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c index b76e3794e3..de82ce2ae7 100644 --- a/arch/arm/mach-imx/imx50.c +++ b/arch/arm/mach-imx/imx50.c @@ -1,28 +1,17 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> #include <io.h> #include <notifier.h> #include <linux/sizes.h> -#include <mach/imx5.h> -#include <mach/imx50-regs.h> -#include <mach/revision.h> -#include <mach/clock-imx51_53.h> -#include <mach/generic.h> -#include <mach/reset-reason.h> -#include <mach/usb.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx50-regs.h> +#include <mach/imx/revision.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/generic.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/usb.h> #define SI_REV 0x48 @@ -32,6 +21,8 @@ static int imx50_silicon_revision(void) u32 rev; u32 mx50_silicon_revision; + OPTIMIZER_HIDE_VAR(rom); + rev = readl(rom + SI_REV); switch (rev) { case 0x10: diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 7404254bee..69b892b01a 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -1,28 +1,17 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> #include <linux/sizes.h> #include <environment.h> #include <io.h> -#include <mach/imx5.h> -#include <mach/imx51-regs.h> -#include <mach/revision.h> -#include <mach/clock-imx51_53.h> -#include <mach/generic.h> -#include <mach/reset-reason.h> -#include <mach/usb.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/revision.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/generic.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/usb.h> #define IIM_SREV 0x24 diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index f8e34a39da..e7eb3ea796 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -1,28 +1,17 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> #include <io.h> #include <notifier.h> #include <linux/sizes.h> -#include <mach/imx5.h> -#include <mach/imx53-regs.h> -#include <mach/revision.h> -#include <mach/clock-imx51_53.h> -#include <mach/generic.h> -#include <mach/reset-reason.h> -#include <mach/usb.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/revision.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/generic.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/usb.h> #define SI_REV 0x48 @@ -32,6 +21,8 @@ static int imx53_silicon_revision(void) u32 rev; u32 mx53_silicon_revision; + OPTIMIZER_HIDE_VAR(rom); + rev = readl(rom + SI_REV); switch (rev) { case 0x10: diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c index 8f661e3dfe..134a41bad5 100644 --- a/arch/arm/mach-imx/imx6-mmdc.c +++ b/arch/arm/mach-imx/imx6-mmdc.c @@ -1,33 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de + /* * i.MX6 DDR controller calibration functions * Based on Freescale code - * - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> -#include <mach/imx6-mmdc.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> + +static bool wlcalib_failed(void __iomem *ips) +{ + /* + * The i.MX 6 reference manual specifies that an MMDC flags reports + * write calibration errors in the MPWLGCR register's HW_WL_ERR field. + * + * ERR050070 specifies that this doesn't work and we should check + * the MPWLHWERR register instead which reports which write leveling + * steps succeeded or failed on a per-byte basis. + * + * Check each byte to see which steps succeeded. If no steps succeeded + * then declare the calibration a failure. + */ + + int i; + + for (i = 0; i < 4; ++i) { + if (readb(ips + MPWLHWERR + i) == 0) + return true; + } + + return false; +} int mmdc_do_write_level_calibration(void) { + u32 ldectrl[4]; u32 esdmisc_val, zq_val; int errorcount = 0; u32 val; u32 ddr_mr1 = 0x4; + /* Store current calibration data in case of failure */ + ldectrl[0] = readl(P0_IPS + MPWLDECTRL0); + ldectrl[1] = readl(P0_IPS + MPWLDECTRL1); + ldectrl[2] = readl(P1_IPS + MPWLDECTRL0); + ldectrl[3] = readl(P1_IPS + MPWLDECTRL1); + /* disable DDR logic power down timer */ val = readl((P0_IPS + MDPDC)); val &= 0xffff00ff; @@ -66,9 +87,13 @@ int mmdc_do_write_level_calibration(void) /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */ while (readl(P0_IPS + MPWLGCR) & 0x00000001); - /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */ - if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) || - (readl(P1_IPS + MPWLGCR) & 0x00000F00)) { + /* check for any errors on both PHYs */ + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) { + pr_debug("Calibration failed, rolling back calibration data\n"); + writel(ldectrl[0], P0_IPS + MPWLDECTRL0); + writel(ldectrl[1], P0_IPS + MPWLDECTRL1); + writel(ldectrl[2], P1_IPS + MPWLDECTRL0); + writel(ldectrl[3], P1_IPS + MPWLDECTRL1); errorcount++; } diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 6a9ea23c71..b0d3d8ef2f 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <abort.h> #include <init.h> @@ -17,15 +6,15 @@ #include <io.h> #include <linux/sizes.h> #include <mfd/imx6q-iomuxc-gpr.h> -#include <mach/clock-imx6.h> -#include <mach/imx6.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/reset-reason.h> -#include <mach/imx6-anadig.h> -#include <mach/imx6-regs.h> -#include <mach/imx6-fusemap.h> -#include <mach/usb.h> +#include <mach/imx/clock-imx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/revision.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/imx6-anadig.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6-fusemap.h> +#include <mach/imx/usb.h> #include <asm/mmu.h> #include <asm/cache-l2x0.h> #include <mfd/pfuze.h> @@ -42,76 +31,44 @@ #define MX6_OCOTP_CFG0 0x410 #define MX6_OCOTP_CFG1 0x420 -static void imx6_init_lowlevel(void) +static void imx6_configure_aips(void __iomem *aips) { - void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; - void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; - bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; - bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D; - uint32_t val_480; - uint32_t val_528; - uint32_t periph_sel_1; - uint32_t periph_sel_2; - uint32_t reg; - - if ((readl(MXC_CCM_CCGR6) & 0x3)) - imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR)); - /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, aips1); - writel(0x77777777, aips1 + 0x4); - writel(0, aips1 + 0x40); - writel(0, aips1 + 0x44); - writel(0, aips1 + 0x48); - writel(0, aips1 + 0x4c); - writel(0, aips1 + 0x50); - - writel(0x77777777, aips2); - writel(0x77777777, aips2 + 0x4); - writel(0, aips2 + 0x40); - writel(0, aips2 + 0x44); - writel(0, aips2 + 0x48); - writel(0, aips2 + 0x4c); - writel(0, aips2 + 0x50); - - /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs - * to make sure PFD is working right, otherwise, PFDs may - * not output clock after reset, MX6DL and MX6SL have added 396M pfd - * workaround in ROM code, as bus clock need it. - * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk. - */ - if (is_imx6q || is_imx6d) { - val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE | - BM_ANADIG_PFD_480_PFD2_CLKGATE | - BM_ANADIG_PFD_480_PFD1_CLKGATE | - BM_ANADIG_PFD_480_PFD0_CLKGATE; + writel(0x77777777, aips); + writel(0x77777777, aips + 0x4); - val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE | - BM_ANADIG_PFD_528_PFD1_CLKGATE; - - reg = readl(MXC_CCM_CBCMR); - periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) - >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; - - periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) - >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET; - - if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2)) - val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE; + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0, aips + 0x40); + writel(0, aips + 0x44); + writel(0, aips + 0x48); + writel(0, aips + 0x4c); + writel(0, aips + 0x50); +} - if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1) - && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3)) - val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE; +static void imx6_init_lowlevel(void) +{ + bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL; + bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX; - writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); - writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); + /* + * Before reset the controller imx6_boot_save_loc() must be called to + * detect serial-downloader fall back boots. For further information + * check the comment in imx6_get_boot_source(). + */ + if ((readl(MXC_CCM_CCGR6) & 0x3)) + imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR)); - writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); - writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); - } + imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR)); + imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR)); + if (is_imx6ull || is_imx6sx) + imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR)); } static bool imx6_has_ipu(void) @@ -216,10 +173,10 @@ int imx6_init(void) void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR); u64 mx6_uid; - imx6_init_lowlevel(); - imx6_boot_save_loc(); + imx6_init_lowlevel(); + mx6_silicon_revision = imx6_cpu_revision(); mx6_uid = imx6_uid(); @@ -369,7 +326,7 @@ static int imx6_fixup_cpus(struct device_node *root, void *context) unsigned long scu_phys_base; unsigned int max_core_index; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c index d875bf44f1..fbbed423c0 100644 --- a/arch/arm/mach-imx/imx7.c +++ b/arch/arm/mach-imx/imx7.c @@ -1,26 +1,16 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> #include <io.h> +#include <pm_domain.h> #include <linux/sizes.h> #include <asm/psci.h> -#include <mach/imx7.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/reset-reason.h> -#include <mach/imx7-regs.h> +#include <mach/imx/imx7.h> +#include <mach/imx/generic.h> +#include <mach/imx/revision.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/imx7-regs.h> void imx7_init_lowlevel(void) { @@ -172,5 +162,7 @@ int imx7_init(void) imx_set_silicon_revision(cputypestr, imx7_cpu_revision()); imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); + genpd_activate(); + return 0; } diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d2ed7d52a9..52e42ee9ef 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -1,47 +1,31 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> +#include <linux/sizes.h> #include <io.h> #include <asm/syscounter.h> #include <asm/system.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/imx8mq.h> -#include <mach/imx8m-ccm-regs.h> -#include <mach/reset-reason.h> -#include <mach/ocotp.h> -#include <mach/imx8mq-regs.h> -#include <mach/imx8m-ccm-regs.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> +#include <linux/bitfield.h> #include <linux/iopoll.h> -#include <linux/arm-smccc.h> -#define FSL_SIP_BUILDINFO 0xC2000003 -#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +#define IMX_SIP_BUILDINFO 0xC2000003 +#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 void imx8m_clock_set_target_val(int clock_id, u32 val) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(val, ccm + IMX8M_CCM_TARGET_ROOTn(clock_id)); } void imx8m_ccgr_clock_enable(int index) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), ccm + IMX8M_CCM_CCGRn_SET(index)); @@ -49,85 +33,12 @@ void imx8m_ccgr_clock_enable(int index) void imx8m_ccgr_clock_disable(int index) { - void *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), ccm + IMX8M_CCM_CCGRn_CLR(index)); } -u64 imx8m_uid(void) -{ - return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR)); -} - -static int imx8m_init(const char *cputypestr) -{ - void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR); - struct arm_smccc_res res; - - /* - * Reset reasons seem to be identical to that of i.MX7 - */ - imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); - pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid()); - - if (IS_ENABLED(CONFIG_ARM_SMCCC) && - IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) { - arm_smccc_smc(FSL_SIP_BUILDINFO, - FSL_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0, 0, 0, 0, 0, &res); - pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0); - } - - return 0; -} - -int imx8mm_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MM_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mm_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MM: - cputypestr = "i.MX8MM"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision()); - - return imx8m_init(cputypestr); -} - -int imx8mq_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MQ_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mq_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MQ: - cputypestr = "i.MX8MQ"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision()); - - return imx8m_init(cputypestr); -} - #define INTPLL_DIV20_CLKE_MASK BIT(27) #define INTPLL_DIV10_CLKE_MASK BIT(25) #define INTPLL_DIV8_CLKE_MASK BIT(23) @@ -145,7 +56,7 @@ int imx8mq_init(void) #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114 -void imx8mm_early_clock_init(void) +static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */ { void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); @@ -188,9 +99,9 @@ void imx8mm_early_clock_init(void) IMX8M_CCM_TARGET_ROOTn_MUX(3)); imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); - /* Configure SYS_PLL3 to 750MHz */ + /* Configure SYS_PLL3 */ clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, - 750000000UL, 25000000UL); + pll3_freq, 25000000UL); clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), IMX8M_CCM_TARGET_ROOTn_MUX(7), @@ -213,6 +124,22 @@ void imx8mm_early_clock_init(void) FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0)); } +void imx8mm_early_clock_init(void) +{ + __imx8m_early_clock_init(750000000UL); +} + +void imx8mn_early_clock_init(void) +{ + __imx8m_early_clock_init(600000000UL); +} + +void imx8mp_early_clock_init(void) +{ + __imx8m_early_clock_init(750000000UL); +} + + #define KEEP_ALIVE 0x18 #define VER_L 0x1c #define VER_H 0x20 diff --git a/arch/arm/mach-imx/imx9.c b/arch/arm/mach-imx/imx9.c new file mode 100644 index 0000000000..220951fd19 --- /dev/null +++ b/arch/arm/mach-imx/imx9.c @@ -0,0 +1,189 @@ +#define pr_fmt(fmt) "imx9: " fmt + +#include <init.h> +#include <common.h> +#include <linux/clk.h> +#include <mach/imx/generic.h> +#include <mach/imx/ele.h> +#include <linux/bitfield.h> +#include <mach/imx/imx9-regs.h> +#include <tee/optee.h> +#include <asm-generic/memory_layout.h> +#include <asm/optee.h> +#include <mach/imx/scratch.h> + +#define SPEED_GRADING_MASK GENMASK(11, 6) +#define MARKETING_GRADING_MASK GENMASK(5, 4) + +static u32 imx9_read_shadow_fuse(int fuse) +{ + void *ocotp = IOMEM(MX9_OCOTP_BASE_ADDR); + + return readl(ocotp + 0x8000 + (fuse << 2)); +} + +static u32 imx9_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + u32 val; + + val = imx9_read_shadow_fuse(19); + + val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xf; + + speed = 2300000000 - val * 100000000; + + if (cpu_is_mx93()) + max_speed = 1700000000; + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + + return speed; +} + +static void imx93_set_arm_clock(void) +{ + struct clk *pll = clk_lookup("arm_pll"); + struct clk *sel = clk_lookup("a55_sel"); + struct clk *alt = clk_lookup("a55_alt"); + u32 speed; + + if (IS_ERR(pll) || IS_ERR(sel) || IS_ERR(alt)) { + pr_err("Failed to get clocks\n"); + return; + } + + speed = imx9_cpu_speed_grade_hz(); + if (!speed) + return; + + pr_debug("Setting CPU clock to %dMHz\n", speed / 1000000); + + clk_set_parent(sel, alt); + clk_set_rate(pll, speed); + clk_set_parent(sel, pll); +} + +static const bool imx93_have_npu(void) +{ + u32 val = imx9_read_shadow_fuse(19); + + if (val & BIT(13)) + return false; + else + return true; +} + +static const int imx93_ncores(void) +{ + u32 val = imx9_read_shadow_fuse(19); + + if (val & BIT(15)) + return 1; + else + return 2; +} + +static const int imx93_is_9x9(void) +{ + u32 val = imx9_read_shadow_fuse(20); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val & pack_9x9_fused) == pack_9x9_fused) + return true; + else + return false; +} + +#define TEMP_COMMERCIAL 0 +#define TEMP_EXTCOMMERCIAL 1 +#define TEMP_INDUSTRIAL 2 +#define TEMP_AUTOMOTIVE 3 + +static void imx93_cpu_temp_grade(int *minc, int *maxc, char *code) +{ + u32 val = imx9_read_shadow_fuse(19); + int min, max; + char c; + + switch (FIELD_GET(MARKETING_GRADING_MASK, val)) { + case TEMP_AUTOMOTIVE: + min = -40; + max = 125; + c = 'A'; + break; + case TEMP_INDUSTRIAL: + min = -40; + max = 105; + c = 'C'; + break; + case TEMP_EXTCOMMERCIAL: + if (cpu_is_mx93()) { + /* imx93 only has extended industrial*/ + min = -40; + max = 125; + c = 'X'; + } else { + min = -20; + max = 105; + c = '-'; + } + break; + case TEMP_COMMERCIAL: + min = 0; + max = 95; + c = 'D'; + break; + } + + if (minc) + *minc = min; + if (maxc) + *maxc = max; + if (code) + *code = c; +} + +static void imx93_type(void) +{ + int subfamily, min, max; + char code; + + if (imx93_is_9x9()) { + if (imx93_have_npu()) + subfamily = 2; + else + subfamily = 1; + } else { + if (imx93_have_npu()) + subfamily = 5; + else + subfamily = 3; + } + + imx93_cpu_temp_grade(&min, &max, &code); + + pr_info("Detected IMX93%d%d%c (%d - %dC)\n", subfamily, imx93_ncores(), code, min, max); +} + +int imx93_init(void) +{ + imx93_type(); + imx93_set_arm_clock(); + imx93_bootsource(); + + if (IS_ENABLED(CONFIG_PBL_OPTEE)) { + static struct of_optee_fixup_data optee_fixup_data = { + .shm_size = OPTEE_SHM_SIZE, + .method = "smc", + }; + + optee_set_membase(imx_scratch_get_optee_hdr()); + of_optee_fixup(of_get_root_node(), &optee_fixup_data); + of_register_fixup(of_optee_fixup, &optee_fixup_data); + } + + return 0; +} diff --git a/arch/arm/mach-imx/imx93-trdc.c b/arch/arm/mach-imx/imx93-trdc.c new file mode 100644 index 0000000000..e5ef5bc081 --- /dev/null +++ b/arch/arm/mach-imx/imx93-trdc.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ +#define pr_fmt(fmt) "trdc: " fmt + +#include <common.h> +#include <io.h> +#include <mach/imx/ele.h> +#include <mach/imx/trdc.h> +#include <mach/imx/imx9-regs.h> + +#define DID_NUM 16 +#define MBC_MAX_NUM 4 +#define MRC_MAX_NUM 2 +#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF) +#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F) + +struct mbc_mem_dom { + u32 mem_glbcfg[4]; + u32 nse_blk_index; + u32 nse_blk_set; + u32 nse_blk_clr; + u32 nsr_blk_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + u32 mem0_blk_cfg_w[64]; + u32 mem0_blk_nse_w[16]; + u32 mem1_blk_cfg_w[8]; + u32 mem1_blk_nse_w[2]; + u32 mem2_blk_cfg_w[8]; + u32 mem2_blk_nse_w[2]; + u32 mem3_blk_cfg_w[8]; + u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ + u32 reserved[2]; +}; + +struct mrc_rgn_dom { + u32 mrc_glbcfg[4]; + u32 nse_rgn_indirect; + u32 nse_rgn_set; + u32 nse_rgn_clr; + u32 nse_rgn_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + u32 rgn_nse; + u32 reserved2[15]; +}; + +struct mda_inst { + u32 mda_w[8]; +}; + +struct trdc_mgr { + u32 trdc_cr; + u32 res0[59]; + u32 trdc_hwcfg0; + u32 trdc_hwcfg1; + u32 res1[450]; + struct mda_inst mda[8]; + u32 res2[15808]; +}; + +struct trdc_mbc { + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc { + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + +static void *trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + + if (mbc_x >= mbc_num) + return 0; + + return (void *)trdc_reg + 0x10000 + 0x2000 * mbc_x; +} + +static void *trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0); + + if (mrc_x >= mrc_num) + return 0; + + return (void *)trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x; +} + +static int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, + u32 glbac_val) +{ + struct trdc_mbc *mbc_base = trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]); + + return 0; +} + +static int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, + u32 blk_x, bool sec_access, u32 glbac_id) +{ + struct trdc_mbc *mbc_base = trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w, *nse_w; + u32 index, offset, val; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = readl((void __iomem *)cfg_w); + + val &= ~(0xFU << offset); + + /* MBC0-3 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MBC0_MEMN_GLBAC0 + */ + if (sec_access) { + val |= ((0x0 | (glbac_id & 0x7)) << offset); + writel(val, (void __iomem *)cfg_w); + } else { + val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */ + writel(val, (void __iomem *)cfg_w); + } + + return 0; +} + +static int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val) +{ + struct trdc_mrc *mrc_base = trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + pr_vdebug("mrc_dom 0x%lx\n", (ulong)mrc_dom); + + writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]); + + return 0; +} + +static int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, + u32 addr_end, bool sec_access, u32 glbac_id) +{ + struct trdc_mrc *mrc_base = trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + u32 *desc_w; + u32 start, end; + u32 i, free = 8; + bool vld, hit = false; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mrc_dom = &mrc_base->mrc_dom[dom_x]; + + addr_start &= ~0x3fff; + addr_end &= ~0x3fff; + + for (i = 0; i < 8; i++) { + desc_w = &mrc_dom->rgn_desc_words[i][0]; + + start = readl((void __iomem *)desc_w) & (~0x3fff); + end = readl((void __iomem *)(desc_w + 1)); + vld = end & 0x1; + end = end & (~0x3fff); + + if (start == 0 && end == 0 && !vld && free >= 8) + free = i; + + /* Check all the region descriptors, even overlap */ + if (addr_start >= end || addr_end <= start || !vld) + continue; + + /* MRC0,1 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MRCx_MEMN_GLBAC0 + */ + if (sec_access) { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1)); + } + + if (addr_start >= start && addr_end <= end) + hit = true; + } + + if (!hit) { + if (free >= 8) + return -EFAULT; + + desc_w = &mrc_dom->rgn_desc_words[free][0]; + + if (sec_access) { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(addr_end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1)); + } + } + + return 0; +} + +static bool trdc_mrc_enabled(ulong trdc_base) +{ + return (!!(readl((void __iomem *)trdc_base) & 0x8000)); +} + +#define CORE_ID_A55 0x2 + +void imx9_trdc_init(void) +{ + unsigned long base = MX9_TRDC_NICMIX_BASE_ADDR; + int ret = 0, i; + + ret |= ele_release_rdc(CORE_ID_A55, 0, NULL); + ret |= ele_release_rdc(CORE_ID_A55, 2, NULL); + ret |= ele_release_rdc(CORE_ID_A55, 1, NULL); + ret |= ele_release_rdc(CORE_ID_A55, 3, NULL); + + if (ret) + return; + + /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */ + trdc_mbc_set_control(base, 3, 0, 0x7700); + + for (i = 0; i < 40; i++) + trdc_mbc_blk_config(base, 3, 3, 0, i, true, 0); + + for (i = 0; i < 40; i++) + trdc_mbc_blk_config(base, 3, 3, 1, i, true, 0); + + for (i = 0; i < 40; i++) + trdc_mbc_blk_config(base, 3, 0, 0, i, true, 0); + + for (i = 0; i < 40; i++) + trdc_mbc_blk_config(base, 3, 0, 1, i, true, 0); + + /* TRDC mega */ + if (!trdc_mrc_enabled(base)) + return; + + /* DDR */ + trdc_mrc_set_control(base, 0, 0, 0x7777); + /* S400*/ + trdc_mrc_region_config(base, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0); + /* MTR */ + trdc_mrc_region_config(base, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0); + /* M33 */ + trdc_mrc_region_config(base, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0); + /* A55*/ + trdc_mrc_region_config(base, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0); + /* For USDHC1 to DDR, USDHC1 is default force to non-secure */ + trdc_mrc_region_config(base, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0); + /* For USDHC2 to DDR, USDHC2 is default force to non-secure */ + trdc_mrc_region_config(base, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0); + /* eDMA */ + trdc_mrc_region_config(base, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0); + /* CoreSight, TestPort */ + trdc_mrc_region_config(base, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0); + /* DAP */ + trdc_mrc_region_config(base, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0); + /* SoC masters */ + trdc_mrc_region_config(base, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0); + /* USB */ + trdc_mrc_region_config(base, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0); +} diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h deleted file mode 100644 index f64a9dd2ba..0000000000 --- a/arch/arm/mach-imx/include/mach/atf.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __IMX_ATF_H__ -#define __IMX_ATF_H__ - -#include <linux/sizes.h> -#include <asm/system.h> - -#define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K - -#define MX8MM_ATF_BL31_BASE_ADDR 0x00920000 -#define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000 -#define MX8M_ATF_BL33_BASE_ADDR 0x40200000 -#define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR -#define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR - -void imx8mm_atf_load_bl31(const void *fw, size_t fw_size); -void imx8mq_atf_load_bl31(const void *fw, size_t fw_size); - -#endif
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h deleted file mode 100644 index 10638a7fc7..0000000000 --- a/arch/arm/mach-imx/include/mach/bbu.h +++ /dev/null @@ -1,210 +0,0 @@ -#ifndef __MACH_BBU_H -#define __MACH_BBU_H - -#include <bbu.h> -#include <errno.h> - -struct imx_dcd_entry; -struct imx_dcd_v2_entry; - -/* - * The ROM code reads images from a certain offset of the boot device - * (usually 0x400), whereas the update images start from offset 0x0. - * Set this flag to skip the offset on both the update image and the - * device so that the initial boot device portion is preserved. This - * is useful if a partition table or other data is in this area. - */ -#define IMX_BBU_FLAG_KEEP_HEAD BIT(16) - -/* - * Set this flag when the partition the update image is written to - * actually starts at the offset where the i.MX flash header is expected - * (usually 0x400). This means for the update code that it has to skip - * the first 0x400 bytes of the image. - */ -#define IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER (1 << 17) - -/* - * The upper 16 bit of the flags passes to the below functions are reserved - * for i.MX specific flags - */ -#define IMX_BBU_FLAG_MASK 0xffff0000 - -#ifdef CONFIG_BAREBOX_UPDATE - -int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx51_bbu_internal_spi_i2c_register_handler(const char *name, - const char *devicefile, unsigned long flags); - -int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx53_bbu_internal_nand_register_handler(const char *name, - unsigned long flags, int partition_size); - -int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx6_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx51_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int vf610_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx7_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx7_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags); -int imx8mq_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile, - unsigned long flags); - -#else - -static inline int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx51_bbu_internal_spi_i2c_register_handler(const char *name, - const char *devicefile, unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx53_bbu_internal_nand_register_handler(const char *name, - unsigned long flags, int partition_size) -{ - return -ENOSYS; -} - -static inline int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx6_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx51_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - - -static inline int vf610_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx7_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx8mq_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int -vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -static inline int -imx7_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} - -#endif - -#if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) -int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile, - unsigned long flags); -#else -static inline int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile, - unsigned long flags) -{ - return -ENOSYS; -} -#endif - -#endif diff --git a/arch/arm/mach-imx/include/mach/ccm.h b/arch/arm/mach-imx/include/mach/ccm.h deleted file mode 100644 index 32254a85b4..0000000000 --- a/arch/arm/mach-imx/include/mach/ccm.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __IMX_CCM_H__ - -/* 0 <= n <= 190 */ -#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) - -/* 0 <= n <= 120 */ -#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define CCM_TARGET_ROOTn_ENABLE BIT(28) - - -#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00) -#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01) -#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10) -#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11) - -#endif
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h deleted file mode 100644 index 06ea2e2a3c..0000000000 --- a/arch/arm/mach-imx/include/mach/clock-imx51_53.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -/* PLL Register Offsets */ -#define MX5_PLL_DP_CTL 0x00 -#define MX5_PLL_DP_CONFIG 0x04 -#define MX5_PLL_DP_OP 0x08 -#define MX5_PLL_DP_MFD 0x0C -#define MX5_PLL_DP_MFN 0x10 -#define MX5_PLL_DP_MFNMINUS 0x14 -#define MX5_PLL_DP_MFNPLUS 0x18 -#define MX5_PLL_DP_HFS_OP 0x1C -#define MX5_PLL_DP_HFS_MFD 0x20 -#define MX5_PLL_DP_HFS_MFN 0x24 -#define MX5_PLL_DP_MFN_TOGC 0x28 -#define MX5_PLL_DP_DESTAT 0x2c - -/* PLL Register Bit definitions */ -#define MX5_PLL_DP_CTL_MUL_CTRL 0x2000 -#define MX5_PLL_DP_CTL_DPDCK0_2_EN 0x1000 -#define MX5_PLL_DP_CTL_DPDCK0_2_OFFSET 12 -#define MX5_PLL_DP_CTL_ADE 0x800 -#define MX5_PLL_DP_CTL_REF_CLK_DIV 0x400 -#define MX5_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) -#define MX5_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 -#define MX5_PLL_DP_CTL_HFSM 0x80 -#define MX5_PLL_DP_CTL_PRE 0x40 -#define MX5_PLL_DP_CTL_UPEN 0x20 -#define MX5_PLL_DP_CTL_RST 0x10 -#define MX5_PLL_DP_CTL_RCP 0x8 -#define MX5_PLL_DP_CTL_PLM 0x4 -#define MX5_PLL_DP_CTL_BRM0 0x2 -#define MX5_PLL_DP_CTL_LRF 0x1 - -#define MX5_PLL_DP_CONFIG_BIST 0x8 -#define MX5_PLL_DP_CONFIG_SJC_CE 0x4 -#define MX5_PLL_DP_CONFIG_AREN 0x2 -#define MX5_PLL_DP_CONFIG_LDREQ 0x1 - -#define MX5_PLL_DP_OP_MFI_OFFSET 4 -#define MX5_PLL_DP_OP_MFI_MASK (0xF << 4) -#define MX5_PLL_DP_OP_PDF_OFFSET 0 -#define MX5_PLL_DP_OP_PDF_MASK 0xF - -#define MX5_PLL_DP_MFD_OFFSET 0 -#define MX5_PLL_DP_MFD_MASK 0x07FFFFFF - -#define MX5_PLL_DP_MFN_OFFSET 0x0 -#define MX5_PLL_DP_MFN_MASK 0x07FFFFFF - -#define MX5_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) -#define MX5_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) -#define MX5_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 -#define MX5_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF - -#define MX5_PLL_DxP_DESTAT_TOG_SEL (1 << 31) -#define MX5_PLL_DP_DESTAT_MFN 0x07FFFFFF - -/* Register addresses of CCM */ -#define MX5_CCM_CCR 0x00 -#define MX5_CCM_CCDR 0x04 -#define MX5_CCM_CSR 0x08 -#define MX5_CCM_CCSR 0x0C -#define MX5_CCM_CACRR 0x10 -#define MX5_CCM_CBCDR 0x14 -#define MX5_CCM_CBCMR 0x18 -#define MX5_CCM_CSCMR1 0x1C -#define MX5_CCM_CSCMR2 0x20 -#define MX5_CCM_CSCDR1 0x24 -#define MX5_CCM_CS1CDR 0x28 -#define MX5_CCM_CS2CDR 0x2C -#define MX5_CCM_CDCDR 0x30 -#define MX5_CCM_CHSCDR 0x34 -#define MX5_CCM_CSCDR2 0x38 -#define MX5_CCM_CSCDR3 0x3C -#define MX5_CCM_CSCDR4 0x40 -#define MX5_CCM_CWDR 0x44 -#define MX5_CCM_CDHIPR 0x48 -#define MX5_CCM_CDCR 0x4C -#define MX5_CCM_CTOR 0x50 -#define MX5_CCM_CLPCR 0x54 -#define MX5_CCM_CISR 0x58 -#define MX5_CCM_CIMR 0x5C -#define MX5_CCM_CCOSR 0x60 -#define MX5_CCM_CGPR 0x64 -#define MX5_CCM_CCGR0 0x68 -#define MX5_CCM_CCGR1 0x6C -#define MX5_CCM_CCGR2 0x70 -#define MX5_CCM_CCGR3 0x74 -#define MX5_CCM_CCGR4 0x78 -#define MX5_CCM_CCGR5 0x7C -#define MX5_CCM_CCGR6 0x80 -#define MX50_CCM_CCGR7 0x84 -#define MX53_CCM_CCGR7 0x84 -#define MX51_CCM_CMEOR 0x84 - -/* Define the bits in register CCR */ -#define MX5_CCM_CCR_COSC_EN (1 << 12) -#define MX5_CCM_CCR_FPM_MULT_MASK (1 << 11) -#define MX5_CCM_CCR_CAMP2_EN (1 << 10) -#define MX5_CCM_CCR_CAMP1_EN (1 << 9) -#define MX5_CCM_CCR_FPM_EN (1 << 8) -#define MX5_CCM_CCR_OSCNT_OFFSET (0) -#define MX5_CCM_CCR_OSCNT_MASK (0xFF) - -/* Define the bits in register CCDR */ -#define MX5_CCM_CCDR_HSC_HS_MASK (0x1 << 18) -#define MX5_CCM_CCDR_IPU_HS_MASK (0x1 << 17) -#define MX5_CCM_CCDR_EMI_HS_MASK (0x1 << 16) - -/* Define the bits in register CSR */ -#define MX5_CCM_CSR_COSR_READY (1 << 5) -#define MX5_CCM_CSR_LVS_VALUE (1 << 4) -#define MX5_CCM_CSR_CAMP2_READY (1 << 3) -#define MX5_CCM_CSR_CAMP1_READY (1 << 2) -#define MX5_CCM_CSR_FPM_READY (1 << 1) -#define MX5_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MX5_CCM_CCSR_LP_APM_SEL (0x1 << 9) -#define MX5_CCM_CCSR_STEP_SEL_OFFSET (7) -#define MX5_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) -#define MX5_CCM_CCSR_STEP_SEL_LP_APM 0 -#define MX5_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ -#define MX5_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 -#define MX5_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 -#define MX5_CCM_CCSR_PLL2_PODF_OFFSET (5) -#define MX5_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) -#define MX5_CCM_CCSR_PLL3_PODF_OFFSET (3) -#define MX5_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) -#define MX5_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, - 1: step_clk */ -#define MX5_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MX5_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MX5_CCM_CACRR_ARM_PODF_OFFSET (0) -#define MX5_CCM_CACRR_ARM_PODF_MASK (0x7) - -/* Define the bits in register CBCDR */ -#define MX5_CCM_CBCDR_RESET_VALUE (0x19239145) -#define MX5_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MX5_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MX5_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) -#define MX5_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) -#define MX5_CCM_CBCDR_DDR_PODF_OFFSET (27) -#define MX5_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MX5_CCM_CBCDR_EMI_PODF_OFFSET (22) -#define MX5_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MX5_CCM_CBCDR_AXI_B_PODF_OFFSET (19) -#define MX5_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MX5_CCM_CBCDR_AXI_A_PODF_OFFSET (16) -#define MX5_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MX5_CCM_CBCDR_NFC_PODF_OFFSET (13) -#define MX5_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MX5_CCM_CBCDR_AHB_PODF_OFFSET (10) -#define MX5_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MX5_CCM_CBCDR_IPG_PODF_OFFSET (8) -#define MX5_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MX5_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) -#define MX5_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MX5_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) -#define MX5_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MX5_CCM_CBCDR_PERCLK_PODF_OFFSET (0) -#define MX5_CCM_CBCDR_PERCLK_PODF_MASK (0x7) - -/* Define the bits in register CBCMR */ -#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) -#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) -#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MX5_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) -#define MX5_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) -#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) -#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MX5_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) -#define MX5_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) -#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) -#define MX5_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MX5_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCMR1 */ -#define MX5_CCM_CSCMR1_RESET_VALUE (0xa6a2a020) -#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) -#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) -#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) -#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) -#define MX5_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) -#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) -#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MX5_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) -#define MX5_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) -#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) -#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) -#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) -#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) -#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MX5_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MX5_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) -#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MX5_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MX5_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) -#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) -#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MX5_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MX5_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) - -/* Define the bits in register CSCMR2 */ -#define MX5_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) -#define MX5_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) -#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) -#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) -#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) -#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) -#define MX5_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) -#define MX5_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) -#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) -#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) -#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) -#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) -#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) -#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) -#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) -#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) -#define MX5_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) -#define MX5_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) -#define MX5_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) -#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) -#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) -#define MX5_CCM_CSCMR2_SPDIF1_COM (1 << 5) -#define MX5_CCM_CSCMR2_SPDIF0_COM (1 << 4) -#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) -#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) -#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) -#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) - -/* Define the bits in register CSCDR1 */ -#define MX5_CCM_CSCDR1_RESET_VALUE (0x00c30318) -#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) -#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) -#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) -#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) -#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) -#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) -#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) -#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MX5_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) -#define MX5_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) -#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) -#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) -#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) -#define MX5_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) -#define MX5_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) - -/* Define the bits in register CS1CDR and CS2CDR */ -#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) -#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) -#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) -#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) -#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) -#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) -#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) - -#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) -#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) -#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) -#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) -#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) -#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) -#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDCDR */ -#define MX5_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) -#define MX5_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) -#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) -#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) -#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) -#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) -#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) -#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) -#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) -#define MX5_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) -#define MX5_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) -#define MX5_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) -#define MX5_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) -#define MX5_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) -#define MX5_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) - -/* Define the bits in register CHSCCDR */ -#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) -#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) -#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) -#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) -#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) -#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) -#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) -#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) - -/* Define the bits in register CSCDR2 */ -#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) -#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) -#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MX5_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) -#define MX5_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MX5_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) -#define MX5_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MX5_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) -#define MX5_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MX5_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) -#define MX5_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR3 */ -#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) -#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) -#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) -#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) -#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) -#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) -#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) -#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR4 */ -#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) -#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) -#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) -#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) -#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) -#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) -#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) -#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDHIPR */ -#define MX5_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MX5_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) -#define MX5_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) -#define MX5_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) -#define MX5_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#define MX5_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) -#define MX5_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) -#define MX5_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) -#define MX5_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) -#define MX5_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) - -/* Define the bits in register CDCR */ -#define MX5_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) -#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) -#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) - -/* Define the bits in register CLPCR */ -#define MX5_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) -#define MX5_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) -#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) -#define MX5_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) -#define MX5_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) -#define MX5_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -#define MX5_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) -#define MX5_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) -#define MX5_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define MX5_CCM_CLPCR_STBY_COUNT_OFFSET (9) -#define MX5_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MX5_CCM_CLPCR_VSTBY (0x1 << 8) -#define MX5_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define MX5_CCM_CLPCR_SBYOS (0x1 << 6) -#define MX5_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define MX5_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) -#define MX5_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MX5_CCM_CLPCR_LPM_OFFSET (0) -#define MX5_CCM_CLPCR_LPM_MASK (0x3) - -/* Define the bits in register CISR */ -#define MX5_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) -#define MX5_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MX5_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) -#define MX5_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) -#define MX5_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) -#define MX5_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) -#define MX5_CCM_CISR_DIVIDER_LOADED (0x1 << 16) -#define MX5_CCM_CISR_COSC_READY (0x1 << 6) -#define MX5_CCM_CISR_CKIH2_READY (0x1 << 5) -#define MX5_CCM_CISR_CKIH_READY (0x1 << 4) -#define MX5_CCM_CISR_FPM_READY (0x1 << 3) -#define MX5_CCM_CISR_LRF_PLL3 (0x1 << 2) -#define MX5_CCM_CISR_LRF_PLL2 (0x1 << 1) -#define MX5_CCM_CISR_LRF_PLL1 (0x1) - -/* Define the bits in register CIMR */ -#define MX5_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) -#define MX5_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MX5_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) -#define MX5_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) -#define MX5_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) -#define MX5_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) -#define MX5_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) -#define MX5_CCM_CIMR_MASK_COSC_READY (0x1 << 5) -#define MX5_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) -#define MX5_CCM_CIMR_MASK_FPM_READY (0x1 << 3) -#define MX5_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) -#define MX5_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) -#define MX5_CCM_CIMR_MASK_LRF_PLL1 (0x1) - -/* Define the bits in register CCOSR */ -#define MX5_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) -#define MX5_CCM_CCOSR_CKO2_DIV_OFFSET (21) -#define MX5_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MX5_CCM_CCOSR_CKO2_SEL_OFFSET (16) -#define MX5_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MX5_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MX5_CCM_CCOSR_CKOL_DIV_OFFSET (4) -#define MX5_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MX5_CCM_CCOSR_CKOL_SEL_OFFSET (0) -#define MX5_CCM_CCOSR_CKOL_SEL_MASK (0xF) - -/* Define the bits in registers CGPR */ -#define MX5_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) -#define MX5_CCM_CGPR_FPM_SEL (0x1 << 3) -#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) -#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) - -/* Define the bits in registers CCGRx */ -#define MX5_CCM_CCGRx_CG_MASK 0x3 -#define MX5_CCM_CCGRx_MOD_OFF 0x0 -#define MX5_CCM_CCGRx_MOD_ON 0x3 -#define MX5_CCM_CCGRx_MOD_IDLE 0x1 - -#define MX5_CCM_CCGRx_CG15_MASK (0x3 << 30) -#define MX5_CCM_CCGRx_CG14_MASK (0x3 << 28) -#define MX5_CCM_CCGRx_CG13_MASK (0x3 << 26) -#define MX5_CCM_CCGRx_CG12_MASK (0x3 << 24) -#define MX5_CCM_CCGRx_CG11_MASK (0x3 << 22) -#define MX5_CCM_CCGRx_CG10_MASK (0x3 << 20) -#define MX5_CCM_CCGRx_CG9_MASK (0x3 << 18) -#define MX5_CCM_CCGRx_CG8_MASK (0x3 << 16) -#define MX5_CCM_CCGRx_CG5_MASK (0x3 << 10) -#define MX5_CCM_CCGRx_CG4_MASK (0x3 << 8) -#define MX5_CCM_CCGRx_CG3_MASK (0x3 << 6) -#define MX5_CCM_CCGRx_CG2_MASK (0x3 << 4) -#define MX5_CCM_CCGRx_CG1_MASK (0x3 << 2) -#define MX5_CCM_CCGRx_CG0_MASK (0x3 << 0) - -#define MX5_CCM_CCGRx_CG15_OFFSET 30 -#define MX5_CCM_CCGRx_CG14_OFFSET 28 -#define MX5_CCM_CCGRx_CG13_OFFSET 26 -#define MX5_CCM_CCGRx_CG12_OFFSET 24 -#define MX5_CCM_CCGRx_CG11_OFFSET 22 -#define MX5_CCM_CCGRx_CG10_OFFSET 20 -#define MX5_CCM_CCGRx_CG9_OFFSET 18 -#define MX5_CCM_CCGRx_CG8_OFFSET 16 -#define MX5_CCM_CCGRx_CG7_OFFSET 14 -#define MX5_CCM_CCGRx_CG6_OFFSET 12 -#define MX5_CCM_CCGRx_CG5_OFFSET 10 -#define MX5_CCM_CCGRx_CG4_OFFSET 8 -#define MX5_CCM_CCGRx_CG3_OFFSET 6 -#define MX5_CCM_CCGRx_CG2_OFFSET 4 -#define MX5_CCM_CCGRx_CG1_OFFSET 2 -#define MX5_CCM_CCGRx_CG0_OFFSET 0 - -#define MX5_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MX5_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MX5_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MX5_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MX5_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MX5_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MX5_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MX5_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MX5_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MX5_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MX5_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MX5_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MX5_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) - -/* CORTEXA8 platform */ -#define MX5_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MX5_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MX5_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MX5_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MX5_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MX5_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MX5_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MX5_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MX5_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) - -/* DVFS CORE */ -#define MX5_DVFSTHRS (MX5_DVFS_CORE_BASE + 0x00) -#define MX5_DVFSCOUN (MX5_DVFS_CORE_BASE + 0x04) -#define MX5_DVFSSIG1 (MX5_DVFS_CORE_BASE + 0x08) -#define MX5_DVFSSIG0 (MX5_DVFS_CORE_BASE + 0x0C) -#define MX5_DVFSGPC0 (MX5_DVFS_CORE_BASE + 0x10) -#define MX5_DVFSGPC1 (MX5_DVFS_CORE_BASE + 0x14) -#define MX5_DVFSGPBT (MX5_DVFS_CORE_BASE + 0x18) -#define MX5_DVFSEMAC (MX5_DVFS_CORE_BASE + 0x1C) -#define MX5_DVFSCNTR (MX5_DVFS_CORE_BASE + 0x20) -#define MX5_DVFSLTR0_0 (MX5_DVFS_CORE_BASE + 0x24) -#define MX5_DVFSLTR0_1 (MX5_DVFS_CORE_BASE + 0x28) -#define MX5_DVFSLTR1_0 (MX5_DVFS_CORE_BASE + 0x2C) -#define MX5_DVFSLTR1_1 (MX5_DVFS_CORE_BASE + 0x30) -#define MX5_DVFSPT0 (MX5_DVFS_CORE_BASE + 0x34) -#define MX5_DVFSPT1 (MX5_DVFS_CORE_BASE + 0x38) -#define MX5_DVFSPT2 (MX5_DVFS_CORE_BASE + 0x3C) -#define MX5_DVFSPT3 (MX5_DVFS_CORE_BASE + 0x40) - -/* GPC */ -#define MX5_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MX5_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MX5_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MX5_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MX5_GPC_NEON (MX51_GPC_BASE + 0x10) -#define MX5_GPC_PGR_ARMPG_OFFSET 8 -#define MX5_GPC_PGR_ARMPG_MASK (3 << 8) - -/* PGC */ -#define MX5_PGC_IPU_PGCR (MX5_PGC_IPU_BASE + 0x0) -#define MX5_PGC_IPU_PGSR (MX5_PGC_IPU_BASE + 0xC) -#define MX5_PGC_VPU_PGCR (MX5_PGC_VPU_BASE + 0x0) -#define MX5_PGC_VPU_PGSR (MX5_PGC_VPU_BASE + 0xC) -#define MX5_PGC_GPU_PGCR (MX5_PGC_GPU_BASE + 0x0) -#define MX5_PGC_GPU_PGSR (MX5_PGC_GPU_BASE + 0xC) - -#define MX5_PGCR_PCR 1 -#define MX5_SRPGCR_PCR 1 -#define MX5_EMPGCR_PCR 1 -#define MX5_PGSR_PSR 1 - - -#define MX5_CORTEXA8_PLAT_LPC_DSM (1 << 0) -#define MX5_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) - -/* SRPG */ -#define MX5_SRPG_NEON_SRPGCR (MX5_SRPG_NEON_BASE + 0x0) -#define MX5_SRPG_NEON_PUPSCR (MX5_SRPG_NEON_BASE + 0x4) -#define MX5_SRPG_NEON_PDNSCR (MX5_SRPG_NEON_BASE + 0x8) - -#define MX5_SRPG_ARM_SRPGCR (MX5_SRPG_ARM_BASE + 0x0) -#define MX5_SRPG_ARM_PUPSCR (MX5_SRPG_ARM_BASE + 0x4) -#define MX5_SRPG_ARM_PDNSCR (MX5_SRPG_ARM_BASE + 0x8) - -#define MX5_SRPG_EMPGC0_SRPGCR (MX5_SRPG_EMPGC0_BASE + 0x0) -#define MX5_SRPG_EMPGC0_PUPSCR (MX5_SRPG_EMPGC0_BASE + 0x4) -#define MX5_SRPG_EMPGC0_PDNSCR (MX5_SRPG_EMPGC0_BASE + 0x8) - -#define MX5_SRPG_EMPGC1_SRPGCR (MX5_SRPG_EMPGC1_BASE + 0x0) -#define MX5_SRPG_EMPGC1_PUPSCR (MX5_SRPG_EMPGC1_BASE + 0x4) -#define MX5_SRPG_EMPGC1_PDNSCR (MX5_SRPG_EMPGC1_BASE + 0x8) - -#define MX5_SRPG_MEGAMIX_SRPGCR (MX5_SRPG_MEGAMIX_BASE + 0x0) -#define MX5_SRPG_MEGAMIX_PUPSCR (MX5_SRPG_MEGAMIX_BASE + 0x4) -#define MX5_SRPG_MEGAMIX_PDNSCR (MX5_SRPG_MEGAMIX_BASE + 0x8) - -#define MX5_SRPGC_EMI_SRPGCR (MX5_SRPGC_EMI_BASE + 0x0) -#define MX5_SRPGC_EMI_PUPSCR (MX5_SRPGC_EMI_BASE + 0x4) -#define MX5_SRPGC_EMI_PDNSCR (MX5_SRPGC_EMI_BASE + 0x8) - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h deleted file mode 100644 index 8e5e9d92b0..0000000000 --- a/arch/arm/mach-imx/include/mach/clock-imx6.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__ - -#define MXC_CCM_BASE MX6_CCM_BASE_ADDR - -/* Register addresses of CCM*/ -#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) -#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80) -#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_RBC_EN (1 << 27) -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) -#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET (21) -#define MXC_CCM_CCR_WB_COUNT_MASK (0x7) -#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) -#define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_OSCNT_MASK (0xFF) -#define MXC_CCM_CCR_OSCNT_OFFSET (0) - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) -#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) - -/* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSC_READY (1 << 5) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) -#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) -#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) -#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) -#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) -#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) -#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) -#define MXC_CCM_CCSR_STEP_SEL (1 << 8) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) -#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET (27) -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET (19) -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_AXI_PODF_OFFSET (16) -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) -#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) -#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET (3) -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET (0) - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET (29) -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET (26) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET (23) -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET (21) -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET (18) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET (12) -#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) -#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET (8) -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET (4) -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET (29) -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) -#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET (27) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET (23) -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET (20) -#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) -#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) -#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) -#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (10) -#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F) - -/* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19) -#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) -#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET (25) -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET (22) -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET (16) -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET (11) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) - -/* Define the bits in register CS1CDR */ -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25) -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) - -/* Define the bits in register CS2CDR */ -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET (21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET (18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET (16) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET (12) -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET (9) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) - -/* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) -#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET (29) -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET (20) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (12) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET (7) - -/* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET (15) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET (12) -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET (9) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET (6) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET (3) -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (0) - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET (15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET (12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET (9) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET (6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET (3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK (0x7) -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET (0) - -/* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET (16) -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET (11) -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET (9) - -/* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) -#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1) - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) -#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) -#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) -#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) -#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) -#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) -#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) -#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) -#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) -#define MXC_CCM_CLPCR_VSTBY (1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) -#define MXC_CCM_CLPCR_SBYOS (1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) -#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) -#define MXC_CCM_CLPCR_LPM_MASK (0x3) -#define MXC_CCM_CLPCR_LPM_OFFSET (0) - -/* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) -#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) -#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CISR_COSC_READY (1 << 6) -#define MXC_CCM_CISR_LRF_PLL (1) - -/* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) -#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) -#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) -#define MXC_CCM_CIMR_MASK_LRF_PLL (1) - -/* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) -#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) - -/* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) -#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1) - -#endif /* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/clock-vf610.h b/arch/arm/mach-imx/include/mach/clock-vf610.h deleted file mode 100644 index 0fa70a4385..0000000000 --- a/arch/arm/mach-imx/include/mach/clock-vf610.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_CLOCK_VF610_H__ -#define __MACH_CLOCK_VF610_H__ - -#define VF610_CCM_CCR (VF610_CCM_BASE_ADDR + 0x00) -#define VF610_CCM_CSR (VF610_CCM_BASE_ADDR + 0x04) -#define VF610_CCM_CCSR (VF610_CCM_BASE_ADDR + 0x08) -#define VF610_CCM_CACRR (VF610_CCM_BASE_ADDR + 0x0c) -#define VF610_CCM_CSCMR1 (VF610_CCM_BASE_ADDR + 0x10) -#define VF610_CCM_CSCDR1 (VF610_CCM_BASE_ADDR + 0x14) -#define VF610_CCM_CSCDR2 (VF610_CCM_BASE_ADDR + 0x18) -#define VF610_CCM_CSCDR3 (VF610_CCM_BASE_ADDR + 0x1c) -#define VF610_CCM_CSCMR2 (VF610_CCM_BASE_ADDR + 0x20) -#define VF610_CCM_CTOR (VF610_CCM_BASE_ADDR + 0x28) -#define VF610_CCM_CLPCR (VF610_CCM_BASE_ADDR + 0x80) -#define VF610_CCM_CMEOR5 (VF610_CCM_BASE_ADDR + 0x84) -#define VF610_CCM_CPPDSR (VF610_CCM_BASE_ADDR + 0x88) -#define VF610_CCM_CCOWR (VF610_CCM_BASE_ADDR + 0x8c) -#define VF610_CCM_CCPGR0 (VF610_CCM_BASE_ADDR + 0x90) -#define VF610_CCM_CCPGR1 (VF610_CCM_BASE_ADDR + 0x94) -#define VF610_CCM_CCPGR2 (VF610_CCM_BASE_ADDR + 0x98) -#define VF610_CCM_CCPGR3 (VF610_CCM_BASE_ADDR + 0x9c) - -#define VF610_CCM_CCGRx_CGn(n) ((n) * 2) - -#define VF610_ANADIG_PLL1_CTRL (VF610_ANADIG_BASE_ADDR + 0x270) -#define VF610_ANADIG_PLL1_NUM (VF610_ANADIG_BASE_ADDR + 0x290) -#define VF610_ANADIG_PLL1_DENOM (VF610_ANADIG_BASE_ADDR + 0x2A0) -#define VF610_ANADIG_PLL2_CTRL (VF610_ANADIG_BASE_ADDR + 0x30) -#define VF610_ANADIG_PLL2_NUM (VF610_ANADIG_BASE_ADDR + 0x50) -#define VF610_ANADIG_PLL3_CTRL (VF610_ANADIG_BASE_ADDR + 0x10) -#define VF610_ANADIG_PLL4_CTRL (VF610_ANADIG_BASE_ADDR + 0x70) -#define VF610_ANADIG_PLL5_CTRL (VF610_ANADIG_BASE_ADDR + 0xe0) -#define VF610_ANADIG_PLL6_CTRL (VF610_ANADIG_BASE_ADDR + 0xa0) -#define VF610_ANADIG_PLL7_CTRL (VF610_ANADIG_BASE_ADDR + 0x20) -#define VF610_ANADIG_ANA_MISC1 (VF610_ANADIG_BASE_ADDR + 0x160) -#define VF610_ANADIG_LOCK (VF610_ANADIG_BASE_ADDR + 0x2C0) - -#define CCM_CCR_FIRC_EN (1 << 16) -#define CCM_CCR_OSCNT_MASK 0xff -#define CCM_CCR_OSCNT(v) ((v) & 0xff) - -#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 -#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) -#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) - -#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 -#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) -#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) - -#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) -#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) - -#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) -#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) - -#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 -#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 -#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) - -#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 -#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) -#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) -#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 -#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) -#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) -#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 -#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 -#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) - -#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 -#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) -#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) -#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 -#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) -#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) -#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 -#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) -#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) - -#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) - -#define CCM_CSCDR2_NFC_EN (1 << 9) -#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) -#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) -#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 -#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) -#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) - -#define CCM_CSCDR2_ESDHC1_EN (1 << 29) -#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 -#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) -#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) - -#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 -#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) -#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) -#define CCM_CSCDR3_QSPI0_EN (1 << 4) -#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) -#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) -#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) - -#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 -#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) -#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) - -#define CCM_REG_CTRL_MASK 0xffffffff -#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) -#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) -#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) -#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) -#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) -#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) -#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) -#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) -#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) -#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) -#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) -#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) -#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 -#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) -#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) -#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) -#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) -#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) -#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14) -#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) -#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) -#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) -#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) -#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) -#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) -#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 -#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) -#define CCM_CCGR10_NFC_CTRL_MASK 0x3 -#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12) -#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14) - -#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL5_CTRL_DIV_SELECT 1 -#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL2_CTRL_DIV_SELECT 1 -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL1_CTRL_DIV_SELECT 1 - -#endif diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h deleted file mode 100644 index 304a7c885c..0000000000 --- a/arch/arm/mach-imx/include/mach/clock.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing, but some drivers need this include */ diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h deleted file mode 100644 index 5eed01631c..0000000000 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifndef __MACH_DEBUG_LL_H__ -#define __MACH_DEBUG_LL_H__ - -#include <io.h> -#include <config.h> -#include <common.h> -#include <mach/imx1-regs.h> -#include <mach/imx21-regs.h> -#include <mach/imx25-regs.h> -#include <mach/imx27-regs.h> -#include <mach/imx31-regs.h> -#include <mach/imx35-regs.h> -#include <mach/imx50-regs.h> -#include <mach/imx51-regs.h> -#include <mach/imx53-regs.h> -#include <mach/imx6-regs.h> -#include <mach/imx7-regs.h> -#include <mach/imx8mq-regs.h> -#include <mach/vf610-regs.h> - -#include <serial/imx-uart.h> -#include <serial/lpuart.h> - -#ifdef CONFIG_DEBUG_LL - -#define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR -#define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num) - -#ifdef CONFIG_DEBUG_IMX1_UART -#define IMX_DEBUG_SOC MX1 -#elif defined CONFIG_DEBUG_IMX21_UART -#define IMX_DEBUG_SOC MX21 -#elif defined CONFIG_DEBUG_IMX25_UART -#define IMX_DEBUG_SOC MX25 -#elif defined CONFIG_DEBUG_IMX27_UART -#define IMX_DEBUG_SOC MX27 -#elif defined CONFIG_DEBUG_IMX31_UART -#define IMX_DEBUG_SOC MX31 -#elif defined CONFIG_DEBUG_IMX35_UART -#define IMX_DEBUG_SOC MX35 -#elif defined CONFIG_DEBUG_IMX50_UART -#define IMX_DEBUG_SOC MX50 -#elif defined CONFIG_DEBUG_IMX51_UART -#define IMX_DEBUG_SOC MX51 -#elif defined CONFIG_DEBUG_IMX53_UART -#define IMX_DEBUG_SOC MX53 -#elif defined CONFIG_DEBUG_IMX6Q_UART -#define IMX_DEBUG_SOC MX6 -#elif defined CONFIG_DEBUG_IMX7D_UART -#define IMX_DEBUG_SOC MX7 -#elif defined CONFIG_DEBUG_IMX8MQ_UART -#define IMX_DEBUG_SOC MX8MQ -#elif defined CONFIG_DEBUG_VF610_UART -#define IMX_DEBUG_SOC VF610 -#else -#error "unknown i.MX debug uart soc type" -#endif - -static inline void imx50_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - imx50_uart_setup(base); -} - -static inline void imx51_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - imx51_uart_setup(base); -} - -static inline void imx53_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - imx53_uart_setup(base); -} - -static inline void imx6_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - imx6_uart_setup(base); -} - -static inline void imx7_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - imx7_uart_setup(base); -} - -static inline void vf610_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - - lpuart_setup(base, 66000000); -} - -static inline void imx8m_uart_setup_ll(void) -{ - void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, - CONFIG_DEBUG_IMX_UART_PORT)); - imx8mq_uart_setup(base); -} - -static inline void PUTC_LL(int c) -{ - void __iomem *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, - CONFIG_DEBUG_IMX_UART_PORT)); - - if (!base) - return; - - if (IS_ENABLED(CONFIG_DEBUG_VF610_UART)) - lpuart_putc(base, c); - else - imx_uart_putc(base, c); -} - -#else - -static inline void imx50_uart_setup_ll(void) {} -static inline void imx51_uart_setup_ll(void) {} -static inline void imx53_uart_setup_ll(void) {} -static inline void imx6_uart_setup_ll(void) {} -static inline void imx7_uart_setup_ll(void) {} -static inline void vf610_uart_setup_ll(void) {} -static inline void imx8m_uart_setup_ll(void) {} - -#endif /* CONFIG_DEBUG_LL */ - -static inline void imx_ungate_all_peripherals(void __iomem *ccmbase) -{ - int i; - for (i = 0x68; i <= 0x80; i += 4) - writel(0xffffffff, ccmbase + i); -} - -static inline void imx6_ungate_all_peripherals(void) -{ - imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR)); -} - -static inline void imx51_ungate_all_peripherals(void) -{ - imx_ungate_all_peripherals(IOMEM(MX51_CCM_BASE_ADDR)); -} - -static inline void imx53_ungate_all_peripherals(void) -{ - imx_ungate_all_peripherals(IOMEM(MX53_CCM_BASE_ADDR)); -} - -static inline void vf610_ungate_all_peripherals(void) -{ - void __iomem *ccmbase = IOMEM(VF610_CCM_BASE_ADDR); - int i; - - for (i = 0x40; i <= 0x6c; i += 4) - writel(0xffffffff, ccmbase + i); -} - -#endif /* __MACH_DEBUG_LL_H__ */ diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h deleted file mode 100644 index e4185bc281..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx1.h +++ /dev/null @@ -1,12 +0,0 @@ -#include <mach/devices.h> -#include <mach/imx1-regs.h> - -static inline struct device_d *imx1_add_uart0(void) -{ - return imx_add_uart_imx1((void *)MX1_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx1_add_uart1(void) -{ - return imx_add_uart_imx1((void *)MX1_UART2_BASE_ADDR, 1); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h deleted file mode 100644 index 5b2dfd7505..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx21.h +++ /dev/null @@ -1,34 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx21-regs.h> - -static inline struct device_d *imx21_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX21_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx21_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx21_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 2); -} - -static inline struct device_d *imx21_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 3); -} - -static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata) -{ - return imx_add_nand((void *)0xDF003000, pdata); -} - -static inline struct device_d *imx21_add_fb(struct imx_fb_platform_data *pdata) -{ - return imx_add_fb((void *)0x10021000, pdata); -} - diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h deleted file mode 100644 index 7779a02be1..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx25.h +++ /dev/null @@ -1,83 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx25-regs.h> - -static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX25_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx25_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX25_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx25_add_i2c2(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX25_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX25_CSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx25_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX25_CSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx25_add_spi2(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX25_CSPI3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx25_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX25_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx25_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX25_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx25_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX25_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx25_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX25_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx25_add_uart4(void) -{ - return imx_add_uart_imx21((void *)MX25_UART5_BASE_ADDR, 4); -} - -static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata) -{ - return imx_add_nand((void *)MX25_NFC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata) -{ - return imx_add_fb((void *)MX25_LCDC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX25_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx25((void *)MX25_ESDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx25_add_mmc1(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx25((void *)MX25_ESDHC2_BASE_ADDR, 1, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h deleted file mode 100644 index da2289b191..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx27.h +++ /dev/null @@ -1,88 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx27-regs.h> - -static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx27((void *)MX27_CSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx27_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx27((void *)MX27_CSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX27_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX27_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx27_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX27_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx27_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX27_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx27_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX27_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx27_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX27_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata) -{ - return imx_add_nand((void *)MX27_NFC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata) -{ - return imx_add_fb((void *)MX27_LCDC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX27_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx27_add_mmc0(void *pdata) -{ - return imx_add_mmc((void *)MX27_SDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx27_add_mmc1(void *pdata) -{ - return imx_add_mmc((void *)MX27_SDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx27_add_mmc2(void *pdata) -{ - return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx27_add_usbotg(void *pdata) -{ - return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx27_add_usbh1(void *pdata) -{ - return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x200, 1, pdata); -} - -static inline struct device_d *imx27_add_usbh2(void *pdata) -{ - return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x400, 2, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h deleted file mode 100644 index 51125d1bca..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx31.h +++ /dev/null @@ -1,93 +0,0 @@ - -#include <mach/imx31-regs.h> -#include <mach/devices.h> - -static inline struct device_d *imx31_add_i2c0(void *pdata) -{ - return imx_add_i2c((void *)MX31_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx31_add_i2c1(void *pdata) -{ - return imx_add_i2c((void *)MX31_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx31_add_i2c2(void *pdata) -{ - return imx_add_i2c((void *)MX31_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX31_CSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX31_CSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX31_CSPI3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx31_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX31_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx31_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX31_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx31_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX31_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx31_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX31_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx31_add_uart4(void) -{ - return imx_add_uart_imx21((void *)MX31_UART5_BASE_ADDR, 4); -} - -static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata) -{ - return imx_add_nand((void *)MX31_NFC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata) -{ - return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata); -} - -static inline struct device_d *imx31_add_mmc0(void *pdata) -{ - return imx_add_mmc((void *)MX31_SDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx31_add_mmc1(void *pdata) -{ - return imx_add_mmc((void *)MX31_SDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx31_add_usbotg(void *pdata) -{ - return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx31_add_usbh1(void *pdata) -{ - return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x200, 1, pdata); -} - -static inline struct device_d *imx31_add_usbh2(void *pdata) -{ - return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x400, 2, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h deleted file mode 100644 index 922bb589c6..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx35.h +++ /dev/null @@ -1,73 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx35-regs.h> - -static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX35_CSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX35_CSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx35_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX35_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx35_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX35_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx35_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX35_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata) -{ - return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata) -{ - return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata); -} - -static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX35_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx25((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx25((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx25((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx50.h b/arch/arm/mach-imx/include/mach/devices-imx50.h deleted file mode 100644 index 7e5141a107..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx50.h +++ /dev/null @@ -1,83 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx50-regs.h> - -static inline struct device_d *imx50_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX50_ECSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx50_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX50_ECSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx50_add_cspi(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX50_CSPI_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx50_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX50_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx50_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX50_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx50_add_i2c2(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX50_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx50_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX50_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx50_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX50_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx50_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX50_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx50_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX50_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx50_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX50_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx50_add_mmc0(struct esdhc_platform_data *pdata) -{ - return imx5_add_esdhc((void *)MX50_ESDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx50_add_mmc1(struct esdhc_platform_data *pdata) -{ - return imx5_add_esdhc((void *)MX50_ESDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx50_add_mmc2(struct esdhc_platform_data *pdata) -{ - return imx5_add_esdhc((void *)MX50_ESDHC3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx50_add_mmc3(struct esdhc_platform_data *pdata) -{ - return imx5_add_esdhc((void *)MX50_ESDHC4_BASE_ADDR, 3, pdata); -} - -static inline struct device_d *imx50_add_kpp(struct matrix_keymap_data *pdata) -{ - return imx_add_kpp((void *)MX50_KPP_BASE_ADDR, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h deleted file mode 100644 index 5a968a3000..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx51.h +++ /dev/null @@ -1,116 +0,0 @@ - -#include <linux/sizes.h> -#include <mach/devices.h> -#include <mach/imx51-regs.h> - -static inline struct device_d *imx51_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX51_ECSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx51_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX51_ECSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx51_add_cspi(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX51_CSPI_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx51_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX51_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx51_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX51_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx51_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX51_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx51_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX51_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx51_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX51_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX51_MXC_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx51_add_mmc0(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx51_add_mmc1(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx51_add_mmc2(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX51_NFC_BASE_ADDR, - .end = MX51_NFC_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_NFC_AXI_BASE_ADDR, - .end = MX51_NFC_AXI_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - }; - struct device_d *dev = xzalloc(sizeof(*dev)); - - dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res)); - memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res)); - dev->num_resources = ARRAY_SIZE(res); - dev_set_name(dev, "imx_nand"); - dev->id = DEVICE_ID_DYNAMIC; - dev->platform_data = pdata; - - platform_device_register(dev); - - return dev; -} - -static inline struct device_d *imx51_add_kpp(struct matrix_keymap_data *pdata) -{ - return imx_add_kpp((void *)MX51_KPP_BASE_ADDR, pdata); -} - -static inline struct device_d *imx51_add_pata(void) -{ - return imx_add_pata((void *)MX51_ATA_BASE_ADDR); -} - -static inline struct device_d *imx51_add_usbotg(void *pdata) -{ - return imx_add_usb((void *)MX51_OTG_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx51_add_usbh1(void *pdata) -{ - return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x200, 1, pdata); -} - -static inline struct device_d *imx51_add_usbh2(void *pdata) -{ - return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x400, 2, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h deleted file mode 100644 index e5c257a40b..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx53.h +++ /dev/null @@ -1,115 +0,0 @@ - -#include <mach/devices.h> -#include <mach/imx53-regs.h> - -static inline struct device_d *imx53_add_cspi(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx35((void *)MX53_CSPI_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx53_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX53_ECSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx53_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX53_ECSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx53_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX53_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX53_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx53_add_i2c2(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX53_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx53_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX53_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx53_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX53_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx53_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX53_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx53_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX53_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx27((void *)MX53_FEC_BASE_ADDR, pdata); -} - -static inline struct device_d *imx53_add_mmc0(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx53_add_mmc1(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX53_ESDHC2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx53_add_mmc2(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX53_ESDHC3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx53_add_mmc3(struct esdhc_platform_data *pdata) -{ - return imx_add_esdhc_imx5((void *)MX53_ESDHC4_BASE_ADDR, 3, pdata); -} - -static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX53_NFC_BASE_ADDR, - .end = MX53_NFC_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX53_NFC_AXI_BASE_ADDR, - .end = MX53_NFC_AXI_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - }; - struct device_d *dev = xzalloc(sizeof(*dev)); - - dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res)); - memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res)); - dev->num_resources = ARRAY_SIZE(res); - dev_set_name(dev, "imx_nand"); - dev->id = DEVICE_ID_DYNAMIC; - dev->platform_data = pdata; - - platform_device_register(dev); - - return dev; -} - -static inline struct device_d *imx53_add_kpp(struct matrix_keymap_data *pdata) -{ - return imx_add_kpp((void *)MX53_KPP_BASE_ADDR, pdata); -} - -static inline struct device_d *imx53_add_sata(void) -{ - return add_generic_device("imx53-sata", 0, NULL, MX53_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); -} diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h deleted file mode 100644 index 9471f57909..0000000000 --- a/arch/arm/mach-imx/include/mach/devices-imx6.h +++ /dev/null @@ -1,98 +0,0 @@ -#include <mach/devices.h> -#include <mach/imx6-regs.h> - -static inline struct device_d *imx6_add_uart0(void) -{ - return imx_add_uart_imx21((void *)MX6_UART1_BASE_ADDR, 0); -} - -static inline struct device_d *imx6_add_uart1(void) -{ - return imx_add_uart_imx21((void *)MX6_UART2_BASE_ADDR, 1); -} - -static inline struct device_d *imx6_add_uart2(void) -{ - return imx_add_uart_imx21((void *)MX6_UART3_BASE_ADDR, 2); -} - -static inline struct device_d *imx6_add_uart3(void) -{ - return imx_add_uart_imx21((void *)MX6_UART4_BASE_ADDR, 3); -} - -static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata) -{ - return imx_add_fec_imx6((void *)MX6_ENET_BASE_ADDR, pdata); -} - -static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx6_add_spi1(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX6_ECSPI2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx6_add_spi2(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX6_ECSPI3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx6_add_spi3(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX6_ECSPI4_BASE_ADDR, 3, pdata); -} - -static inline struct device_d *imx6_add_spi4(struct spi_imx_master *pdata) -{ - return imx_add_spi_imx51((void *)MX6_ECSPI5_BASE_ADDR, 4, pdata); -} - -static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx6_add_i2c1(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX6_I2C2_BASE_ADDR, 1, pdata); -} - -static inline struct device_d *imx6_add_i2c2(struct i2c_platform_data *pdata) -{ - return imx_add_i2c((void *)MX6_I2C3_BASE_ADDR, 2, pdata); -} - -static inline struct device_d *imx6_add_sata(void) -{ - return add_generic_device("imx6-sata", 0, NULL, MX6_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); -} - -static inline struct device_d *imx6_add_usbotg(void *pdata) -{ - add_generic_device("imx-usb-phy", 0, NULL, MX6_USBPHY1_BASE_ADDR, 0x1000, - IORESOURCE_MEM, NULL); - - return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR, 0, pdata); -} - -static inline struct device_d *imx6_add_usbh1(void *pdata) -{ - add_generic_device("imx-usb-phy", 1, NULL, MX6_USBPHY2_BASE_ADDR, 0x1000, - IORESOURCE_MEM, NULL); - - return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x200, 1, pdata); -} - -static inline struct device_d *imx6_add_usbh2(void *pdata) -{ - return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x400, 2, pdata); -} - -static inline struct device_d *imx6_add_usbh3(void *pdata) -{ - return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x600, 2, pdata); -} diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h deleted file mode 100644 index 4754b92a6f..0000000000 --- a/arch/arm/mach-imx/include/mach/devices.h +++ /dev/null @@ -1,28 +0,0 @@ - -#include <platform_data/eth-fec.h> -#include <input/matrix_keypad.h> -#include <i2c/i2c.h> -#include <mach/spi.h> -#include <mach/imx-nand.h> -#include <mach/imxfb.h> -#include <mach/imx-ipu-fb.h> -#include <platform_data/mmc-esdhc-imx.h> -#include <usb/chipidea-imx.h> - -struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata); -struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata); -struct device_d *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata); -struct device_d *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata); -struct device_d *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata); -struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata); -struct device_d *imx_add_uart_imx1(void *base, int id); -struct device_d *imx_add_uart_imx21(void *base, int id); -struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata); -struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata); -struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata); -struct device_d *imx_add_mmc(void *base, int id, void *pdata); -struct device_d *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata); -struct device_d *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata); -struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata); -struct device_d *imx_add_pata(void *base); -struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata); diff --git a/arch/arm/mach-imx/include/mach/esdctl-v4.h b/arch/arm/mach-imx/include/mach/esdctl-v4.h deleted file mode 100644 index 2e6741e0d5..0000000000 --- a/arch/arm/mach-imx/include/mach/esdctl-v4.h +++ /dev/null @@ -1,520 +0,0 @@ -#ifndef __MACH_ESDCTL_V4_H -#define __MACH_ESDCTL_V4_H - -#define ESDCTL_V4_ESDCTL0 0x00 -#define ESDCTL_V4_ESDPDC 0x04 -#define ESDCTL_V4_ESDOTC 0x08 -#define ESDCTL_V4_ESDCFG0 0x0c -#define ESDCTL_V4_ESDCFG1 0x10 -#define ESDCTL_V4_ESDCFG2 0x14 -#define ESDCTL_V4_ESDMISC 0x18 -#define ESDCTL_V4_ESDSCR 0x1c -#define ESDCTL_V4_ESDREF 0x20 -#define ESDCTL_V4_ESDWCC 0x24 -#define ESDCTL_V4_ESDRCC 0x28 -#define ESDCTL_V4_ESDRWD 0x2c -#define ESDCTL_V4_ESDOR 0x30 -#define ESDCTL_V4_ESDMRR 0x34 -#define ESDCTL_V4_ESDCFG3_LP 0x38 -#define ESDCTL_V4_ESDMR4 0x3c -#define ESDCTL_V4_ZQHWCTRL 0x40 -#define ESDCTL_V4_ZQSWCTRL 0x44 -#define ESDCTL_V4_WLGCR 0x48 -#define ESDCTL_V4_WLDECTRL0 0x4c -#define ESDCTL_V4_WLDECTRL1 0x50 -#define ESDCTL_V4_WLDLST 0x54 -#define ESDCTL_V4_ODTCTRL 0x58 -#define ESDCTL_V4_RDDQBY0DL 0x5c -#define ESDCTL_V4_RDDQBY1DL 0x60 -#define ESDCTL_V4_RDDQBY2DL 0x64 -#define ESDCTL_V4_RDDQBY3DL 0x68 -#define ESDCTL_V4_WRDQBY0DL 0x6c -#define ESDCTL_V4_WRDQBY1DL 0x70 -#define ESDCTL_V4_WRDQBY2DL 0x74 -#define ESDCTL_V4_WRDQBY3DL 0x78 -#define ESDCTL_V4_DGCTRL0 0x7c -#define ESDCTL_V4_DGCTRL1 0x80 -#define ESDCTL_V4_DGDLST 0x84 -#define ESDCTL_V4_RDDLCTL 0x88 -#define ESDCTL_V4_RDDLST 0x8c -#define ESDCTL_V4_WRDLCTL 0x90 -#define ESDCTL_V4_WRDLST 0x94 -#define ESDCTL_V4_SDCTRL 0x98 -#define ESDCTL_V4_ZQLP2CTL 0x9c -#define ESDCTL_V4_RDDLHWCTL 0xa0 -#define ESDCTL_V4_WRDLHWCTL 0xa4 -#define ESDCTL_V4_RDDLHWST0 0xa8 -#define ESDCTL_V4_RDDLHWST1 0xac -#define ESDCTL_V4_WRDLHWST0 0xb0 -#define ESDCTL_V4_WRDLHWST1 0xb4 -#define ESDCTL_V4_WLHWERR 0xb8 -#define ESDCTL_V4_DGHWST0 0xbc -#define ESDCTL_V4_DGHWST1 0xc0 -#define ESDCTL_V4_DGHWST2 0xc4 -#define ESDCTL_V4_DGHWST3 0xc8 -#define ESDCTL_V4_PDCMPR1 0xcc -#define ESDCTL_V4_PDCMPR2 0xd0 -#define ESDCTL_V4_SWDADR 0xd4 -#define ESDCTL_V4_SWDRDR0 0xd8 -#define ESDCTL_V4_SWDRDR1 0xdc -#define ESDCTL_V4_SWDRDR2 0xe0 -#define ESDCTL_V4_SWDRDR3 0xe4 -#define ESDCTL_V4_SWDRDR4 0xe8 -#define ESDCTL_V4_SWDRDR5 0xec -#define ESDCTL_V4_SWDRDR6 0xf0 -#define ESDCTL_V4_SWDRDR7 0xf4 -#define ESDCTL_V4_MUR 0xf8 -#define ESDCTL_V4_WRCADL 0xfc - -#define ESDCTL_V4_ESDCTLx_SDE0 0x80000000 -#define ESDCTL_V4_ESDCTLx_SDE1 0x40000000 - -#define ESDCTL_V4_ESDCTLx_ROW_MASK 0x07000000 -#define ESDCTL_V4_ESDCTLx_ROW_11 0x00000000 -#define ESDCTL_V4_ESDCTLx_ROW_12 0x01000000 -#define ESDCTL_V4_ESDCTLx_ROW_13 0x02000000 -#define ESDCTL_V4_ESDCTLx_ROW_14 0x03000000 -#define ESDCTL_V4_ESDCTLx_ROW_15 0x04000000 -#define ESDCTL_V4_ESDCTLx_ROW_16 0x05000000 - -#define ESDCTL_V4_ESDCTLx_COL_MASK 0x00700000 -#define ESDCTL_V4_ESDCTLx_COL_9 0x00000000 -#define ESDCTL_V4_ESDCTLx_COL_10 0x00100000 -#define ESDCTL_V4_ESDCTLx_COL_11 0x00200000 -#define ESDCTL_V4_ESDCTLx_COL_8 0x00300000 -#define ESDCTL_V4_ESDCTLx_COL_12 0x00400000 - -#define ESDCTL_V4_ESDCTLx_BL_MASK 0x00080000 -#define ESDCTL_V4_ESDCTLx_BL_4_RES 0x00000000 -#define ESDCTL_V4_ESDCTLx_BL_8_8 0x00080000 - -#define ESDCTL_V4_ESDCTLx_DSIZ_MASK 0x00010000 -#define ESDCTL_V4_ESDCTLx_DSIZ_16B_LOW 0x00000000 -#define ESDCTL_V4_ESDCTLx_DSIZ_32B 0x00010000 - -#define ESDCTL_V4_ESDMISC_CS0_RDY 0x80000000 -#define ESDCTL_V4_ESDMISC_CS1_RDY 0x40000000 -#define ESDCTL_V4_ESDMISC_ONE_CS 0x00100000 -#define ESDCTL_V4_ESDMISC_ADDR_MIRROR 0x00080000 -#define ESDCTL_V4_ESDMISC_LHD 0x00040000 -#define ESDCTL_V4_ESDMISC_WALAT_SHIFT 16 -#define ESDCTL_V4_ESDMISC_WALAT_MASK (0x3 << ESDCTL_V4_ESDMISC_WALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_WALAT_0 (0x0 << ESDCTL_V4_ESDMISC_WALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_WALAT_1 (0x1 << ESDCTL_V4_ESDMISC_WALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_WALAT_2 (0x2 << ESDCTL_V4_ESDMISC_WALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_WALAT_3 (0x3 << ESDCTL_V4_ESDMISC_WALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_BI_ON 0x00001000 -#define ESDCTL_V4_ESDMISC_MIF3_MODE_MASK 0x00000600 -#define ESDCTL_V4_ESDMISC_MIF3_MODE_DIS 0x00000000 -#define ESDCTL_V4_ESDMISC_MIF3_MODE_EF 0x00000200 -#define ESDCTL_V4_ESDMISC_MIF3_MODE_EFA 0x00000400 -#define ESDCTL_V4_ESDMISC_MIF3_MODE_EFAM 0x00000600 -#define ESDCTL_V4_ESDMISC_RALAT_SHIFT 6 -#define ESDCTL_V4_ESDMISC_RALAT_MASK (0x7 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_0 (0x0 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_1 (0x1 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_2 (0x2 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_3 (0x3 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_4 (0x4 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_5 (0x5 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_6 (0x6 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) -#define ESDCTL_V4_ESDMISC_RALAT_7 (0x7 << ESDCTL_V4_ESDMISC_RALAT_SHIFT) - -#define ESDCTL_V4_ESDMISC_DDR_MASK 0x00000818 -#define ESDCTL_V4_ESDMISC_DDR_DDR3 0x00000000 -#define ESDCTL_V4_ESDMISC_DDR_LPDDR2_S4 0x00000008 -#define ESDCTL_V4_ESDMISC_DDR_LPDDR2_S2 0x00000808 -#define ESDCTL_V4_ESDMISC_DDR_DDR2 0x00000010 - -#define ESDCTL_V4_ESDMISC_BANKS_MASK 0x00000020 -#define ESDCTL_V4_ESDMISC_BANKS_4 0x00000020 -#define ESDCTL_V4_ESDMISC_BANKS_8 0x00000000 - -#define ESDCTL_V4_ESDMISC_RST 0x00000002 - - -#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT 24 -#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT 16 -#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT 8 -#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT 0 -#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET_MASK 0xff - -#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET3_SHIFT 24 -#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET2_SHIFT 16 -#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET1_SHIFT 8 -#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET0_SHIFT 0 -#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET_MASK 0xff - - -#define ESDCTL_V4_ESDDGCTRL0_RST_RD_FIFO 0x80000000 -#define ESDCTL_V4_ESDDGCTRL0_DG_CMP_CYC 0x40000000 -#define ESDCTL_V4_ESDDGCTRL0_DG_DIS 0x20000000 -#define ESDCTL_V4_ESDDGCTRL0_HW_DG_EN 0x10000000 -#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL1_MASK 0x0f000000 -#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL1_SHIFT 24 -#define ESDCTL_V4_ESDDGCTRL0_DG_EXT_UP 0x00800000 -#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET1_MASK 0x007f0000 -#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT 16 -#define ESDCTL_V4_ESDDGCTRL0_HW_DG_ERR 0x00001000 -#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL0_MASK 0x00000f00 -#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL0_SHIFT 8 -#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET0_MASK 0x0000007f -#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT 0 - -#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL3_MASK 0x0f000000 -#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL3_SHIFT 24 -#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET3_MASK 0x007f0000 -#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT 16 -#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL2_MASK 0x00000f00 -#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL2_SHIFT 8 -#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET2_MASK 0x0000007f -#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT 0 - - -#define ESDCTL_V4_ESDCFG0_tRFC_SHIFT 24 -#define ESDCTL_V4_ESDCFG0_tRFC_MASK (0xff << ESDCTL_V4_ESDCFG0_tRFC_SHIFT) -#define ESDCTL_V4_ESDCFG0_tXS_SHIFT 16 -#define ESDCTL_V4_ESDCFG0_tXS_MASK (0xff << ESDCTL_V4_ESDCFG0_tXS_SHIFT) -#define ESDCTL_V4_ESDCFG0_tXP_SHIFT 13 -#define ESDCTL_V4_ESDCFG0_tXP_MASK (0x7 << ESDCTL_V4_ESDCFG0_tXP_SHIFT) -#define ESDCTL_V4_ESDCFG0_tXPDLL_SHIFT 9 -#define ESDCTL_V4_ESDCFG0_tXPDLL_MASK (0xf << ESDCTL_V4_ESDCFG0_tXPDLL_SHIFT) -#define ESDCTL_V4_ESDCFG0_tFAW_SHIFT 4 -#define ESDCTL_V4_ESDCFG0_tFAW_MASK (0x1f << ESDCTL_V4_ESDCFG0_tFAW_SHIFT) -#define ESDCTL_V4_ESDCFG0_tCL_SHIFT 0 -#define ESDCTL_V4_ESDCFG0_tCL_MASK (0xf << ESDCTL_V4_ESDCFG0_tCL_SHIFT) - -#define ESDCTL_V4_ESDCFG1_tRCD_SHIFT 29 -#define ESDCTL_V4_ESDCFG1_tRCD_MASK (0x7 << ESDCTL_V4_ESDCFG1_tRCD_SHIFT) -#define ESDCTL_V4_ESDCFG1_tRP_SHIFT 26 -#define ESDCTL_V4_ESDCFG1_tRP_MASK (0x7 << ESDCTL_V4_ESDCFG1_tRP_SHIFT) -#define ESDCTL_V4_ESDCFG1_tRC_SHIFT 21 -#define ESDCTL_V4_ESDCFG1_tRC_MASK (0x1f << ESDCTL_V4_ESDCFG1_tRC_SHIFT) -#define ESDCTL_V4_ESDCFG1_tRAS_SHIFT 16 -#define ESDCTL_V4_ESDCFG1_tRAS_MASK (0x1f << ESDCTL_V4_ESDCFG1_tRAS_SHIFT) -#define ESDCTL_V4_ESDCFG1_tRPA_SHIFT 15 -#define ESDCTL_V4_ESDCFG1_tRPA_MASK (0x1 << ESDCTL_V4_ESDCFG1_tRPA_SHIFT) -#define ESDCTL_V4_ESDCFG1_tWR_SHIFT 9 -#define ESDCTL_V4_ESDCFG1_tWR_MASK (0x7 << ESDCTL_V4_ESDCFG1_tWR_SHIFT) -#define ESDCTL_V4_ESDCFG1_tMRD_SHIFT 5 -#define ESDCTL_V4_ESDCFG1_tMRD_MASK (0xf << ESDCTL_V4_ESDCFG1_tMRD_SHIFT) -#define ESDCTL_V4_ESDCFG1_tCWL_SHIFT 0 -#define ESDCTL_V4_ESDCFG1_tCWL_MASK (0x7 << ESDCTL_V4_ESDCFG1_tCWL_SHIFT) - -#define ESDCTL_V4_ESDCFG2_tDLLK_SHIFT 16 -#define ESDCTL_V4_ESDCFG2_tDLLK_MASK (0x1ff << ESDCTL_V4_ESDCFG2_tDLLK_SHIFT) -#define ESDCTL_V4_ESDCFG2_tRTP_SHIFT 6 -#define ESDCTL_V4_ESDCFG2_tRTP_MASK (0x7 << ESDCTL_V4_ESDCFG2_tRTP_SHIFT) -#define ESDCTL_V4_ESDCFG2_tWTR_SHIFT 3 -#define ESDCTL_V4_ESDCFG2_tWTR_MASK (0x7 << ESDCTL_V4_ESDCFG2_tWTR_SHIFT) -#define ESDCTL_V4_ESDCFG2_tRRD_SHIFT 0 -#define ESDCTL_V4_ESDCFG2_tRRD_MASK (0x7 << ESDCTL_V4_ESDCFG2_tRRD_SHIFT) - -#define ESDCTL_V4_ESDRWD_tDAI_SHIFT 16 -#define ESDCTL_V4_ESDRWD_tDAI_MASK (0x1fff << ESDCTL_V4_ESDRWD_tDAI_SHIFT) -#define ESDCTL_V4_ESDRWD_RTW_SAME_SHIFT 12 -#define ESDCTL_V4_ESDRWD_RTW_SAME_MASK (0x7 << ESDCTL_V4_ESDRWD_RTW_SAME_SHIFT) -#define ESDCTL_V4_ESDRWD_WTR_DIFF_SHIFT 9 -#define ESDCTL_V4_ESDRWD_WTR_DIFF_MASK (0x7 << ESDCTL_V4_ESDRWD_WTR_DIFF_SHIFT) -#define ESDCTL_V4_ESDRWD_WTW_DIFF_SHIFT 6 -#define ESDCTL_V4_ESDRWD_WTW_DIFF_MASK (0x7 << ESDCTL_V4_ESDRWD_WTW_DIFF_SHIFT) -#define ESDCTL_V4_ESDRWD_RTW_DIFF_SHIFT 3 -#define ESDCTL_V4_ESDRWD_RTW_DIFF_MASK (0x7 << ESDCTL_V4_ESDRWD_RTW_DIFF_SHIFT) -#define ESDCTL_V4_ESDRWD_RTR_DIFF_SHIFT 0 -#define ESDCTL_V4_ESDRWD_RTR_DIFF_MASK (0x7 << ESDCTL_V4_ESDRWD_RTR_DIFF_SHIFT) - -#define ESDCTL_V4_ESDOR_tXPR_SHIFT 16 -#define ESDCTL_V4_ESDOR_tXPR_MASK (0xff << ESDCTL_V4_ESDOR_tXPR_SHIFT) -#define ESDCTL_V4_ESDOR_SDE_to_RST_SHIFT 8 -#define ESDCTL_V4_ESDOR_SDE_to_RST_MASK (0x3f << ESDCTL_V4_ESDOR_SDE_to_RST_SHIFT) -#define ESDCTL_V4_ESDOR_RST_to_CKE_SHIFT 0 -#define ESDCTL_V4_ESDOR_RST_to_CKE_MASK (0x3f << ESDCTL_V4_ESDOR_RST_to_CKE_SHIFT) - -#define ESDCTL_V4_ESDOTC_tAOFPD_SHIFT 27 -#define ESDCTL_V4_ESDOTC_tAOFPD_MASK (0x7 << ESDCTL_V4_ESDOTC_tAOFPD_SHIFT) -#define ESDCTL_V4_ESDOTC_tAONPD_SHIFT 24 -#define ESDCTL_V4_ESDOTC_tAONPD_MASK (0x7 << ESDCTL_V4_ESDOTC_tAONPD_SHIFT) -#define ESDCTL_V4_ESDOTC_tANPD_SHIFT 20 -#define ESDCTL_V4_ESDOTC_tANPD_MASK (0xf << ESDCTL_V4_ESDOTC_tANPD_SHIFT) -#define ESDCTL_V4_ESDOTC_tAXPD_SHIFT 16 -#define ESDCTL_V4_ESDOTC_tAXPD_MASK (0xf << ESDCTL_V4_ESDOTC_tAXPD_SHIFT) -#define ESDCTL_V4_ESDOTC_tODTLon_SHIFT 12 -#define ESDCTL_V4_ESDOTC_tODTLon_MASK (0x7 << ESDCTL_V4_ESDOTC_tODTLon_SHIFT) -#define ESDCTL_V4_ESDOTC_tODT_idle_off_SHIFT 4 -#define ESDCTL_V4_ESDOTC_tODT_idle_off_MASK (0x1f << ESDCTL_V4_ESDOTC_tODT_idle_off_SHIFT) - -#define ESDCTL_V4_ESDPDC_PRCT1_SHIFT 28 -#define ESDCTL_V4_ESDPDC_PRCT1_MASK (0x7 << ESDCTL_V4_ESDPDC_PRCT1_SHIFT) -#define ESDCTL_V4_ESDPDC_PRCT0_SHIFT 24 -#define ESDCTL_V4_ESDPDC_PRCT0_MASK (0x7 << ESDCTL_V4_ESDPDC_PRCT0_SHIFT) -#define ESDCTL_V4_ESDPDC_tCKE_SHIFT 16 -#define ESDCTL_V4_ESDPDC_tCKE_MASK (0x7 << ESDCTL_V4_ESDPDC_tCKE_SHIFT) -#define ESDCTL_V4_ESDPDC_PWDT1_SHIFT 12 -#define ESDCTL_V4_ESDPDC_PWDT1_MASK (0xf << ESDCTL_V4_ESDPDC_PWDT1_SHIFT) -#define ESDCTL_V4_ESDPDC_PWDT0_SHIFT 8 -#define ESDCTL_V4_ESDPDC_PWDT0_MASK (0xf << ESDCTL_V4_ESDPDC_PWDT0_SHIFT) -#define ESDCTL_V4_ESDPDC_SLOW_PD 0x00000080 -#define ESDCTL_V4_ESDPDC_BOTH_CS_PD 0x00000040 -#define ESDCTL_V4_ESDPDC_tCKSRX_SHIFT 3 -#define ESDCTL_V4_ESDPDC_tCKSRX_MASK (0x7 << ESDCTL_V4_ESDPDC_tCKSRX_SHIFT) -#define ESDCTL_V4_ESDPDC_tCKSRE_SHIFT 0 -#define ESDCTL_V4_ESDPDC_tCKSRE_MASK (0x7 << ESDCTL_V4_ESDPDC_tCKSRE_SHIFT) - -#define ESDCTL_V4_ESDPDC_PRCT_DISABLE 0x0 -#define ESDCTL_V4_ESDPDC_PRCT_2 0x1 -#define ESDCTL_V4_ESDPDC_PRCT_4 0x2 -#define ESDCTL_V4_ESDPDC_PRCT_8 0x3 -#define ESDCTL_V4_ESDPDC_PRCT_16 0x4 -#define ESDCTL_V4_ESDPDC_PRCT_32 0x5 -#define ESDCTL_V4_ESDPDC_PRCT_64 0x6 -#define ESDCTL_V4_ESDPDC_PRCT_128 0x7 - -#define ESDCTL_V4_ESDPDC_PWDT_DISABLE 0x0 -#define ESDCTL_V4_ESDPDC_PWDT_16 0x1 -#define ESDCTL_V4_ESDPDC_PWDT_32 0x2 -#define ESDCTL_V4_ESDPDC_PWDT_64 0x3 -#define ESDCTL_V4_ESDPDC_PWDT_128 0x4 -#define ESDCTL_V4_ESDPDC_PWDT_256 0x5 -#define ESDCTL_V4_ESDPDC_PWDT_512 0x6 -#define ESDCTL_V4_ESDPDC_PWDT_1024 0x7 -#define ESDCTL_V4_ESDPDC_PWDT_2048 0x8 -#define ESDCTL_V4_ESDPDC_PWDT_4096 0x9 -#define ESDCTL_V4_ESDPDC_PWDT_8192 0xa -#define ESDCTL_V4_ESDPDC_PWDT_16384 0xb -#define ESDCTL_V4_ESDPDC_PWDT_32768 0xc - -#define ESDCTL_V4_ESDREF_REF_CNT_SHIFT 16 -#define ESDCTL_V4_ESDREF_REF_CNT_MASK (0xffff << ESDCTL_V4_ESDREF_REF_CNT_SHIFT) -#define ESDCTL_V4_ESDREF_REF_SEL_MASK 0x0000c000 -#define ESDCTL_V4_ESDREF_REF_SEL_64K 0x00000000 -#define ESDCTL_V4_ESDREF_REF_SEL_32K 0x00001000 -#define ESDCTL_V4_ESDREF_REF_SEL_REFCNT 0x00002000 -#define ESDCTL_V4_ESDREF_REFR_SHIFT 11 -#define ESDCTL_V4_ESDREF_REFR_MASK (0x7 << ESDCTL_V4_ESDREF_REFR_SHIFT) -#define ESDCTL_V4_ESDREF_START_REF 0x00000001 - -#define ESDCTL_V4_ESDZQHWC_ZQ_PARA_EN 0x04000000 -#define ESDCTL_V4_ESDZQHWC_TZQ_CS_SHIFT 23 -#define ESDCTL_V4_ESDZQHWC_TZQ_CS_MASK (0x7 << ESDCTL_V4_ESDZQHWC_TZQ_CS_SHIFT) -#define ESDCTL_V4_ESDZQHWC_TZQ_OPER_SHIFT 20 -#define ESDCTL_V4_ESDZQHWC_TZQ_OPER_MASK (0x7 << ESDCTL_V4_ESDZQHWC_TZQ_OPER_SHIFT) -#define ESDCTL_V4_ESDZQHWC_TZQ_INIT_SHIFT 17 -#define ESDCTL_V4_ESDZQHWC_TZQ_INIT_MASK (0x7 << ESDCTL_V4_ESDZQHWC_TZQ_INIT_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_FOR 0x00010000 -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_SHIFT 11 -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_MASK (0x1f << ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_SHIFT 6 -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_MASK (0x1f << ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_SHIFT 2 -#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_MASK (0xf << ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT 0 -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_MASK (0x3 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT) - -#define ESDCTL_V4_ESDZQHWC_32CYC 0x0 -#define ESDCTL_V4_ESDZQHWC_64CYC 0x1 -#define ESDCTL_V4_ESDZQHWC_128CYC 0x2 -#define ESDCTL_V4_ESDZQHWC_256CYC 0x3 -#define ESDCTL_V4_ESDZQHWC_512CYC 0x4 -#define ESDCTL_V4_ESDZQHWC_1024CYC 0x5 - -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_NO_CAL (0x0 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_BOTH_EXIT (0x1 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_EXTERNAL_PER (0x2 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT) -#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_BOTH_PER (0x3 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT) - -#define ESDCTL_V4_ESDODTC_ODT3_INT_RES_SHIFT 16 -#define ESDCTL_V4_ESDODTC_ODT3_INT_RES_MASK (0x7 << ESDCTL_V4_ESDODTC_ODT3_INT_RES_SHIFT) -#define ESDCTL_V4_ESDODTC_ODT2_INT_RES_SHIFT 12 -#define ESDCTL_V4_ESDODTC_ODT2_INT_RES_MASK (0x7 << ESDCTL_V4_ESDODTC_ODT2_INT_RES_SHIFT) -#define ESDCTL_V4_ESDODTC_ODT1_INT_RES_SHIFT 8 -#define ESDCTL_V4_ESDODTC_ODT1_INT_RES_MASK (0x7 << ESDCTL_V4_ESDODTC_ODT1_INT_RES_SHIFT) -#define ESDCTL_V4_ESDODTC_ODT0_INT_RES_SHIFT 4 -#define ESDCTL_V4_ESDODTC_ODT0_INT_RES_MASK (0x7 << ESDCTL_V4_ESDODTC_ODT0_INT_RES_SHIFT) -#define ESDCTL_V4_ESDODTC_ODT_RD_ACT_EN 0x00000008 -#define ESDCTL_V4_ESDODTC_ODT_RD_PAS_EN 0x00000004 -#define ESDCTL_V4_ESDODTC_ODT_WR_ACT_EN 0x00000002 -#define ESDCTL_V4_ESDODTC_ODT_WR_PAS_EN 0x00000001 - -#define ESDCTL_V4_ESDODTC_RTT_DISABLE 0x0 -#define ESDCTL_V4_ESDODTC_RTT_60 0x1 -#define ESDCTL_V4_ESDODTC_RTT_120 0x2 -#define ESDCTL_V4_ESDODTC_RTT_40 0x3 -#define ESDCTL_V4_ESDODTC_RTT_20 0x4 -#define ESDCTL_V4_ESDODTC_RTT_30 0x5 - -#define ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT 16 -#define ESDCTL_V4_ESDSCR_CMD_ADDR_MASK (0xffff << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_ESDSCR_CON_REQ 0x00008000 -#define ESDCTL_V4_ESDSCR_CON_ACK 0x00004000 -#define ESDCTL_V4_ESDSCR_MRR_DATA_VALID 0x00000400 -#define ESDCTL_V4_ESDSCR_WL_EN 0x00000200 -#define ESDCTL_V4_ESDSCR_DLL_RST1 0x00000100 -#define ESDCTL_V4_ESDSCR_DLL_RST0 0x00000080 -#define ESDCTL_V4_ESDSCR_CMD_SHIFT 4 -#define ESDCTL_V4_ESDSCR_CMD_MASK (0x7 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_NOP (0x0 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_PRE_ALL (0x1 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_AREFRESH (0x2 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_LMR (0x3 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_ZQCALIB_OLD (0x4 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_PRE_ALL_OPEN (0x5 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_MRR (0x6 << ESDCTL_V4_ESDSCR_CMD_SHIFT) -#define ESDCTL_V4_ESDSCR_CMD_CS 0x00000008 -#define ESDCTL_V4_ESDSCR_CMD_CS0 0x00000000 -#define ESDCTL_V4_ESDSCR_CMD_CS1 0x00000008 -#define ESDCTL_V4_ESDSCR_CMD_BA_SHIFT 0 -#define ESDCTL_V4_ESDSCR_CMD_BA_MASK (0x7 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT) - -#define ESDCTL_V4_PDCMPR2_PHY_CA_DL_SHIFT 24 -#define ESDCTL_V4_PDCMPR2_PHY_CA_DL_MASK (0x7f << ESDCTL_V4_PDCMPR2_PHY_CA_DL_SHIFT) -#define ESDCTL_V4_PDCMPR2_CA_DL_ABS_SHIFT 16 -#define ESDCTL_V4_PDCMPR2_CA_DL_ABS_MASK (0x7f << ESDCTL_V4_PDCMPR2_CA_DL_ABS_SHIFT) -#define ESDCTL_V4_PDCMPR2_RLPAT 0x4 -#define ESDCTL_V4_PDCMPR2_RLPAT_0 0x0 -#define ESDCTL_V4_PDCMPR2_RLPAT_1 0x4 -#define ESDCTL_V4_PDCMPR2_MPR_FULL_CMP 0x2 -#define ESDCTL_V4_PDCMPR2_MPR_CMP 0x1 - -#define ESDCTL_V4_WLGCR_WL_HW_ERR3 (1 << 11) -#define ESDCTL_V4_WLGCR_WL_HW_ERR2 (1 << 10) -#define ESDCTL_V4_WLGCR_WL_HW_ERR1 (1 << 9) -#define ESDCTL_V4_WLGCR_WL_HW_ERR0 (1 << 8) -#define ESDCTL_V4_WLGCR_WL_SW_ERR3 (1 << 7) -#define ESDCTL_V4_WLGCR_WL_SW_ERR2 (1 << 6) -#define ESDCTL_V4_WLGCR_WL_SW_ERR1 (1 << 5) -#define ESDCTL_V4_WLGCR_WL_SW_ERR0 (1 << 4) -#define ESDCTL_V4_WLGCR_SW_WL_CNT_EN (1 << 2) -#define ESDCTL_V4_WLGCR_SW_WL_EN (1 << 1) -#define ESDCTL_V4_WLGCR_HW_WL_EN (1 << 1) - -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_CMP_CYC (1 << 5) -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_EN (1 << 4) -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR3 (1 << 3) -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR2 (1 << 2) -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR1 (1 << 1) -#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR0 (1 << 0) - -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_CMP_CYC (1 << 5) -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_EN (1 << 4) -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR3 (1 << 3) -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR2 (1 << 2) -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR1 (1 << 1) -#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR0 (1 << 0) - -#define ESDCTL_V4_DDR3_REG_MR0 (0x0 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT) -#define ESDCTL_V4_DDR3_REG_MR1 (0x1 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT) -#define ESDCTL_V4_DDR3_REG_MR2 (0x2 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT) -#define ESDCTL_V4_DDR3_REG_MR3 (0x3 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT) - -#define ESDCTL_V4_DDR3_MR0_PPD (0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_PPD_SLOW (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_PPD_FAST (0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_SHIFT (9 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_MASK (0x7 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_16 (0x0 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_5 (0x1 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_6 (0x2 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_7 (0x3 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_8 (0x4 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_10 (0x5 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_12 (0x6 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_WR_14 (0x7 << ESDCTL_V4_DDR3_MR0_WR_SHIFT) -#define ESDCTL_V4_DDR3_DLL_RESET (0x0100 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_TM (0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_TM_NORMAL (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_TM_TEST (0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_SHIFT (2 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_MASK (0x74 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_5 (0x10 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_6 (0x20 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_7 (0x30 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_8 (0x40 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_9 (0x50 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_10 (0x60 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_11 (0x70 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_12 (0x04 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_13 (0x14 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_14 (0x24 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_15 (0x34 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_CL_16 (0x44 << ESDCTL_V4_DDR3_MR0_CL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_RBT (0x0008 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_RBT_NIBBLE (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_RBT_INTERL (0x0008 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_BL_SHIFT (0 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR0_BL_MASK (0x3 << ESDCTL_V4_DDR3_MR0_BL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_BL_FIXED8 (0x0 << ESDCTL_V4_DDR3_MR0_BL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_BL_DYNAMIC (0x1 << ESDCTL_V4_DDR3_MR0_BL_SHIFT) -#define ESDCTL_V4_DDR3_MR0_BL_FIXED4 (0x2 << ESDCTL_V4_DDR3_MR0_BL_SHIFT) - -#define ESDCTL_V4_DDR3_MR1_QOFF (0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_TDQS (0x0800 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_WL (0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_AL_SHIFT (3 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_AL_MASK (0x3 << ESDCTL_V4_DDR3_MR1_AL_SHIFT) -#define ESDCTL_V4_DDR3_MR1_AL_DISABLE (0x0 << ESDCTL_V4_DDR3_MR1_AL_SHIFT) -#define ESDCTL_V4_DDR3_MR1_AL_CL1 (0x1 << ESDCTL_V4_DDR3_MR1_AL_SHIFT) -#define ESDCTL_V4_DDR3_MR1_AL_CL2 (0x2 << ESDCTL_V4_DDR3_MR1_AL_SHIFT) -#define ESDCTL_V4_DDR3_MR1_DLL_DISABLE (0x0001 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_MASK (0x0244 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_DIS (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ4 (0x0004 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ2 (0x0040 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ6 (0x0044 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ12 (0x0200 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ8 (0x0204 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_ODIC_MASK (0x0022 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_ODIC_RZQ6 (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR1_ODIC_RZQ7 (0x0002 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) - -#define ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT (9 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_RTTWR_MASK (0x3 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_RTTWR_OFF (0x0 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_RTTWR_RZQ4 (0x1 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_RTTWR_RZQ2 (0x2 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_SRT (0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_SRT_NORMAL (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_SRT_EXTENDED (0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_ASR_ENABLE (0x0040 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_SHIFT (3 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_MASK (0x7 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_5 (0x0 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_6 (0x1 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_7 (0x2 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_8 (0x3 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_9 (0x4 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_10 (0x5 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_11 (0x6 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_CWL_12 (0x7 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_SHIFT (0 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_MASK (0x7 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_1 (0x0 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_2L (0x1 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_4L (0x2 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_8L (0x3 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_3_4L (0x4 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_2H (0x5 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_4H (0x6 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) -#define ESDCTL_V4_DDR3_MR2_PASR_1_8H (0x7 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT) - -#define ESDCTL_V4_DDR3_MR3_MPR_DISABLE (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR3_MPR_ENABLE (0x0004 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR3_MPR_PATTERN (0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR3_MPR_RFU1 (0x0001 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR3_MPR_RFU2 (0x0002 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) -#define ESDCTL_V4_DDR3_MR3_MPR_RFU3 (0x0003 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT) - -#ifndef __ASSEMBLY__ - -void imx_esdctlv4_do_write_leveling(void); -void imx_esdctlv4_do_dqs_gating(void); -void imx_esdctlv4_do_zq_calibration(void); -void imx_esdctlv4_start_ddr3_sdram(int cs); -void imx_esdctlv4_do_read_delay_line_calibration(void); -void imx_esdctlv4_do_write_delay_line_calibration(void); -void imx_esdctlv4_set_tRFC_timing(void); -void imx_esdctlv4_detect_sdrams(void); -void imx_esdctlv4_init(void); - -#endif - -#endif /* __MACH_ESDCTL_V4_H */ diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h deleted file mode 100644 index 41eb9f6729..0000000000 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ /dev/null @@ -1,149 +0,0 @@ -#ifndef __MACH_ESDCTL_V2_H -#define __MACH_ESDCTL_V2_H - -/* SDRAM Controller registers */ -#define IMX_ESDCTL0 0x00 /* Enhanced SDRAM Control Register 0 */ -#define IMX_ESDCFG0 0x04 /* Enhanced SDRAM Configuration Register 0 */ -#define IMX_ESDCTL1 0x08 /* Enhanced SDRAM Control Register 1 */ -#define IMX_ESDCFG1 0x0C /* Enhanced SDRAM Configuration Register 1 */ -#define IMX_ESDMISC 0x10 /* Enhanced SDRAM Miscellanious Register */ - -#define ESDCTL0_SDE (1 << 31) -#define ESDCTL0_SMODE_NORMAL (0 << 28) -#define ESDCTL0_SMODE_PRECHARGE (1 << 28) -#define ESDCTL0_SMODE_AUTO_REFRESH (2 << 28) -#define ESDCTL0_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH (4 << 28) -#define ESDCTL0_SP (1 << 27) -#define ESDCTL0_ROW11 (0 << 24) -#define ESDCTL0_ROW12 (1 << 24) -#define ESDCTL0_ROW13 (2 << 24) -#define ESDCTL0_ROW14 (3 << 24) -#define ESDCTL0_ROW15 (4 << 24) -#define ESDCTL0_ROW_MASK (7 << 24) -#define ESDCTL0_COL8 (0 << 20) -#define ESDCTL0_COL9 (1 << 20) -#define ESDCTL0_COL10 (2 << 20) -#define ESDCTL0_COL_MASK (3 << 20) -#define ESDCTL0_DSIZ_31_16 (0 << 16) -#define ESDCTL0_DSIZ_15_0 (1 << 16) -#define ESDCTL0_DSIZ_31_0 (2 << 16) -#define ESDCTL0_DSIZ_MASK (3 << 16) -#define ESDCTL0_REF1 (1 << 13) -#define ESDCTL0_REF2 (2 << 13) -#define ESDCTL0_REF4 (3 << 13) -#define ESDCTL0_REF8 (4 << 13) -#define ESDCTL0_REF16 (5 << 13) -#define ESDCTL0_PWDT_DISABLED (0 << 10) -#define ESDCTL0_PWDT_PRECHARGE_PWDN (1 << 10) -#define ESDCTL0_PWDT_PWDN_64 (2 << 10) -#define ESDCTL0_PWDT_PWDN_128 (3 << 10) -#define ESDCTL0_FP (1 << 8) -#define ESDCTL0_BL (1 << 7) - -#define ESDMISC_RST 0x00000002 -#define ESDMISC_MDDR_EN 0x00000004 -#define ESDMISC_MDDR_DIS 0x00000000 -#define ESDMISC_MDDR_DL_RST 0x00000008 -#define ESDMISC_MDDR_MDIS 0x00000010 -#define ESDMISC_LHD 0x00000020 -#define ESDMISC_SDRAMRDY 0x80000000 -#define ESDMISC_DDR2_8_BANK BIT(6) - -#define ESDCFGx_tXP_MASK 0x00600000 -#define ESDCFGx_tXP_1 0x00000000 -#define ESDCFGx_tXP_2 0x00200000 -#define ESDCFGx_tXP_3 0x00400000 -#define ESDCFGx_tXP_4 0x00600000 - -#define ESDCFGx_tWTR_MASK 0x00100000 -#define ESDCFGx_tWTR_1 0x00000000 -#define ESDCFGx_tWTR_2 0x00100000 - -#define ESDCFGx_tRP_MASK 0x000c0000 -#define ESDCFGx_tRP_1 0x00000000 -#define ESDCFGx_tRP_2 0x00040000 -#define ESDCFGx_tRP_3 0x00080000 -#define ESDCFGx_tRP_4 0x000c0000 - - -#define ESDCFGx_tMRD_MASK 0x00030000 -#define ESDCFGx_tMRD_1 0x00000000 -#define ESDCFGx_tMRD_2 0x00010000 -#define ESDCFGx_tMRD_3 0x00020000 -#define ESDCFGx_tMRD_4 0x00030000 - - -#define ESDCFGx_tWR_MASK 0x00008000 -#define ESDCFGx_tWR_1_2 0x00000000 -#define ESDCFGx_tWR_2_3 0x00008000 - -#define ESDCFGx_tRAS_MASK 0x00007000 -#define ESDCFGx_tRAS_1 0x00000000 -#define ESDCFGx_tRAS_2 0x00001000 -#define ESDCFGx_tRAS_3 0x00002000 -#define ESDCFGx_tRAS_4 0x00003000 -#define ESDCFGx_tRAS_5 0x00004000 -#define ESDCFGx_tRAS_6 0x00005000 -#define ESDCFGx_tRAS_7 0x00006000 -#define ESDCFGx_tRAS_8 0x00007000 - - -#define ESDCFGx_tRRD_MASK 0x00000c00 -#define ESDCFGx_tRRD_1 0x00000000 -#define ESDCFGx_tRRD_2 0x00000400 -#define ESDCFGx_tRRD_3 0x00000800 -#define ESDCFGx_tRRD_4 0x00000c00 - - -#define ESDCFGx_tCAS_MASK 0x00000300 -#define ESDCFGx_tCAS_2 0x00000200 -#define ESDCFGx_tCAS_3 0x00000300 - -#define ESDCFGx_tRCD_MASK 0x00000070 -#define ESDCFGx_tRCD_1 0x00000000 -#define ESDCFGx_tRCD_2 0x00000010 -#define ESDCFGx_tRCD_3 0x00000020 -#define ESDCFGx_tRCD_4 0x00000030 -#define ESDCFGx_tRCD_5 0x00000040 -#define ESDCFGx_tRCD_6 0x00000050 -#define ESDCFGx_tRCD_7 0x00000060 -#define ESDCFGx_tRCD_8 0x00000070 - -#define ESDCFGx_tRC_MASK 0x0000000f -#define ESDCFGx_tRC_20 0x00000000 -#define ESDCFGx_tRC_2 0x00000001 -#define ESDCFGx_tRC_3 0x00000002 -#define ESDCFGx_tRC_4 0x00000003 -#define ESDCFGx_tRC_5 0x00000004 -#define ESDCFGx_tRC_6 0x00000005 -#define ESDCFGx_tRC_7 0x00000006 -#define ESDCFGx_tRC_8 0x00000007 -#define ESDCFGx_tRC_9 0x00000008 -#define ESDCFGx_tRC_10 0x00000009 -#define ESDCFGx_tRC_11 0x0000000a -#define ESDCFGx_tRC_12 0x0000000b -#define ESDCFGx_tRC_13 0x0000000c -#define ESDCFGx_tRC_14 0x0000000d -//#define ESDCFGx_tRC_14 0x0000000e // 15 seems to not exist -#define ESDCFGx_tRC_16 0x0000000f - -#ifndef __ASSEMBLY__ -void __noreturn imx1_barebox_entry(void *boarddata); -void __noreturn imx25_barebox_entry(void *boarddata); -void __noreturn imx27_barebox_entry(void *boarddata); -void __noreturn imx31_barebox_entry(void *boarddata); -void __noreturn imx35_barebox_entry(void *boarddata); -void __noreturn imx51_barebox_entry(void *boarddata); -void __noreturn imx53_barebox_entry(void *boarddata); -void __noreturn imx6q_barebox_entry(void *boarddata); -void __noreturn imx6ul_barebox_entry(void *boarddata); -void __noreturn vf610_barebox_entry(void *boarddata); -void __noreturn imx8mm_barebox_entry(void *boarddata); -void __noreturn imx8mq_barebox_entry(void *boarddata); -void __noreturn imx7d_barebox_entry(void *boarddata); -#define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata) -void imx_esdctl_disable(void); -#endif - -#endif /* __MACH_ESDCTL_V2_H */ diff --git a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg deleted file mode 100644 index e98f055eea..0000000000 --- a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * SPDX-License-Identifier: GPL-2.0 - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - * - * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit - * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d - */ - -#include <mach/imx7-ddr-regs.h> - -wm 32 0x30340004 0x4F400005 - -wm 32 0x30391000 0x00000002 - -wm 32 MX7_DDRC_MSTR 0x01040001 -wm 32 MX7_DDRC_DFIUPD0 0x80400003 -wm 32 MX7_DDRC_DFIUPD1 0x00100020 -wm 32 MX7_DDRC_DFIUPD2 0x80100004 -wm 32 MX7_DDRC_RFSHTMG 0x00400046 -wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 -wm 32 MX7_DDRC_INIT0 0x00020083 -wm 32 MX7_DDRC_INIT1 0x00690000 -wm 32 MX7_DDRC_INIT3 0x09300004 -wm 32 MX7_DDRC_INIT4 0x04080000 -wm 32 MX7_DDRC_INIT5 0x00100004 -wm 32 MX7_DDRC_RANKCTL 0x0000033f -wm 32 MX7_DDRC_DRAMTMG0 0x09081109 -wm 32 MX7_DDRC_DRAMTMG1 0x0007020d -wm 32 MX7_DDRC_DRAMTMG2 0x03040407 -wm 32 MX7_DDRC_DRAMTMG3 0x00002006 -wm 32 MX7_DDRC_DRAMTMG4 0x04020205 -wm 32 MX7_DDRC_DRAMTMG5 0x03030202 -wm 32 MX7_DDRC_DRAMTMG8 0x00000803 -wm 32 MX7_DDRC_ZQCTL0 0x00800020 -wm 32 MX7_DDRC_ZQCTL1 0x02000100 -wm 32 MX7_DDRC_DFITMG0 0x02098204 -wm 32 MX7_DDRC_DFITMG1 0x00030303 -wm 32 MX7_DDRC_ADDRMAP0 0x00000016 -wm 32 MX7_DDRC_ADDRMAP1 0x00171717 -wm 32 MX7_DDRC_ADDRMAP5 0x04040404 -wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 -wm 32 MX7_DDRC_ODTCFG 0x06000604 -wm 32 MX7_DDRC_ODTMAP 0x00000001 - -wm 32 0x30391000 0x00000000 - -wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 -wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 -wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 -wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e -wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e -wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 -wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 -wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 -wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 - -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 - -check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 - -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 - -wm 32 0x30384130 0x00000000 -wm 32 0x30340020 0x00000178 -wm 32 0x30384130 0x00000002 - -wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f - -check 32 until_any_bit_set MX7_DDRC_STAT 0x1 diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg deleted file mode 100644 index 8c411ddc7e..0000000000 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg +++ /dev/null @@ -1,131 +0,0 @@ -/* - - The following table contains DDR3 memory timing parameters derived - form memory module (Samsung K4B4G1646E) datasheet: - -| CL | 6 | @400Mhz | -| WRLAT | 5 | | -| t_RC | 21 | | -| t_RRD | 4 | [5] | -| t_CCD | 4 | | -| t_FAW | 16(1KB page)/20(2KB page) | | -| t_RP | 6 | | -| t_WTR | 4 | [6] | -| t_RAS(MIN) | 15 | | -| t_MRD | 4 | | -| t_RTP | 4 | [1] | -| t_MOD | 12 | [7] | -| t_RAS(MAX) | 28080 | [8] | -| t_CKESR | 4 | [9] | -| t_CKE | 3 | [10] | -| t_RCD | 6 | | -| t_DAL | 12 | [11] | -| t_DDLK | 512 | | -| t_RP(AB) | 6 | n/a in datasheet | -| t_REFI | 3120 | | -| t_RFC | 44 @ 1Gb, 64@2Gb, 104@4Gb, 140@8Gb | | -| t_XP | 3 | [4] | -| t_XPDLL | 10 | [12] | -| t_XS | 48 @ 1Gb, 68@2Gb, 108@4Gb, 148@8Gb | [2] | -| t_XSDLL | 512 | | -| t_CKSRX | 5 | [3] | -| t_CKSRE | 5 | [3] | -| MR0 | | | -| MR1 | | | -| MR2 | | | -| MR3 | | | -| t_ZQoper | 256 | | -| t_ZQinit | 512 | | -| t_ZQCS | 64 | | -| ODTL_off | 3 | [14] | -| t_WLMRD | 40 | | -| t_WLDQSEN | 25 | | -| t_WR | 6 | | -| t_ODTH8(R) | 6 | n/a in datasheet | -| t_ODTH8(W) | 6 | | - - -[1] t_RTP = max(4nCK, 7.5ns) = max(10ns, 7.5ns)@400Mhz = 4nCK -[2] t_XS = max(5nCK, t_RFC + 10ns) -[3] t_CKSRX = t_CKSRE = max(5nCK, 10ns) = max(12.5ns, 7.5ns)@400Mhz = 5nCK -[4] t_XP = max(3nCK, 7.5ns) = max(7.5ns, 7.5ns)@400Mhz = 3nCK -[5] t_RRD = max(4nCK, 10ns) = max(10ns, 10ns)@400Mhz = 4nCK -[6] t_WTR = max(4nCK, 7.5ns) = 4nCK (see [1] for calculation) -[7] t_MOD = max(12nCK, 15ns) = max(30ns, 15ns)@400Mhz = 12nCK -[8] t_RAS(MAX) = 9 * t_REFI = 9 * 7.8us = 28080nCK -[9] t_CKESR = t_CKE(min) + 1tCK = 4nCK -[10] t_CKE = max(3nCK, 7.5ns) = 3nCK (see [4]) -[11] t_DAL = t_WR + roundup(t_RP/t_CK(AVG)) = 6nCK + 6nCK = 12nCK -[12] t_XPDLL = max(10nCK, 24ns) = max(25ns, 25ns)@400Mhz = 10nCK -[13] WRLAT = AL + CWL = 0 (not supported by controller) + 5nCK = 5nCK -[14] ODTL_off = WRLAT - 2 = 3nCK - -*/ - -wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3 -wm 32 DDRMC_CR02 0x00000005 -wm 32 DDRMC_CR10 0x00013880 -wm 32 DDRMC_CR11 0x00030d40 -wm 32 DDRMC_CR12 0x0000050c -wm 32 DDRMC_CR13 0x15040400 -wm 32 DDRMC_CR14 0x1406040f -wm 32 DDRMC_CR16 0x04040000 -wm 32 DDRMC_CR17 0x006db00c -wm 32 DDRMC_CR18 0x00000403 -wm 32 DDRMC_CR20 0x01000000 -wm 32 DDRMC_CR21 0x00060001 -wm 32 DDRMC_CR22 0x000c0000 -wm 32 DDRMC_CR23 0x03000200 -wm 32 DDRMC_CR24 0x00000006 -wm 32 DDRMC_CR25 0x00010000 -wm 32 DDRMC_CR26 0x0c30002c -wm 32 DDRMC_CR28 0x00000000 -wm 32 DDRMC_CR29 0x00000003 -wm 32 DDRMC_CR30 0x0000000a -wm 32 DDRMC_CR31 0x00300200 -wm 32 DDRMC_CR33 0x00010000 -wm 32 DDRMC_CR34 0x00050500 -wm 32 DDRMC_CR38 0x00000000 -wm 32 DDRMC_CR39 0x04001002 -wm 32 DDRMC_CR41 0x00000001 -wm 32 DDRMC_CR48 0x00460420 -wm 32 DDRMC_CR66 0x01000200 -wm 32 DDRMC_CR67 0x00000040 -wm 32 DDRMC_CR69 0x00000200 -wm 32 DDRMC_CR70 0x00000040 -wm 32 DDRMC_CR72 0x00000000 -wm 32 DDRMC_CR73 0x0a010300 -wm 32 DDRMC_CR74 0x01014040 -wm 32 DDRMC_CR75 0x01010101 -wm 32 DDRMC_CR76 0x03030100 -wm 32 DDRMC_CR77 0x01000101 -wm 32 DDRMC_CR78 0x0700000c -wm 32 DDRMC_CR79 0x00000000 -wm 32 DDRMC_CR82 0x10000000 -wm 32 DDRMC_CR87 0x01000000 -wm 32 DDRMC_CR88 0x00040000 -wm 32 DDRMC_CR89 0x00000002 -wm 32 DDRMC_CR91 0x00020000 -wm 32 DDRMC_CR96 0x00002819 -wm 32 DDRMC_CR117 0x00000000 -wm 32 DDRMC_CR118 0x01010000 -wm 32 DDRMC_CR120 0x02020000 -wm 32 DDRMC_CR121 0x00000202 -wm 32 DDRMC_CR122 0x01010064 -wm 32 DDRMC_CR123 0x00010101 -wm 32 DDRMC_CR124 0x00000064 -wm 32 DDRMC_CR126 0x00000800 -/* - * Despite the RM insisting on setting RDLAT_ADJ to CASLAT_LIN - 1 in - * two places: p 1459 (section 10.1.5.133 "Control Register 132 - * (DDRMC_CR132)") and p. 1587 (section 10.1.6.15.10 "Configure the - * 'output enable' of I/O Control") changing it from current 6 to - * recommended 5 results in non-working DDR. - */ -wm 32 DDRMC_CR132 0x00000506 -wm 32 DDRMC_CR137 0x00020000 -wm 32 DDRMC_CR138 0x01000100 -wm 32 DDRMC_CR154 0x682c4000 -wm 32 DDRMC_CR155 0x00000009 -wm 32 DDRMC_CR158 0x00000006 -wm 32 DDRMC_CR161 0x00010606
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg deleted file mode 100644 index e9d5ab0ca2..0000000000 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * VFxxx shared DDR PHY DCD code. Intended use is to share code - * between all board that copy VF610 Tower Board DDR reference - * layout/design - * - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x00210000 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00002000 -#define DDRMC_PHY_OFF 0x00000000 -#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 -#define DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE 0x00001100 - - -wm 32 DDRMC_PHY00 DDRMC_PHY_DQ_TIMING -wm 32 DDRMC_PHY16 DDRMC_PHY_DQ_TIMING -wm 32 DDRMC_PHY32 DDRMC_PHY_DQ_TIMING - -wm 32 DDRMC_PHY01 DDRMC_PHY_DQS_TIMING -wm 32 DDRMC_PHY17 DDRMC_PHY_DQS_TIMING - -wm 32 DDRMC_PHY02 DDRMC_PHY_CTRL -wm 32 DDRMC_PHY18 DDRMC_PHY_CTRL -wm 32 DDRMC_PHY34 DDRMC_PHY_CTRL - -wm 32 DDRMC_PHY03 DDRMC_PHY_MASTER_CTRL -wm 32 DDRMC_PHY19 DDRMC_PHY_MASTER_CTRL -wm 32 DDRMC_PHY35 DDRMC_PHY_MASTER_CTRL - -wm 32 DDRMC_PHY04 DDRMC_PHY_SLAVE_CTRL -wm 32 DDRMC_PHY20 DDRMC_PHY_SLAVE_CTRL -wm 32 DDRMC_PHY36 DDRMC_PHY_SLAVE_CTRL - -wm 32 DDRMC_PHY49 DDRMC_PHY_OFF -wm 32 DDRMC_PHY50 DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE -wm 32 DDRMC_PHY52 DDRMC_PHY_PROC_PAD_ODT diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg deleted file mode 100644 index 74d119b59e..0000000000 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Ungate all IP block clocks - */ -wm 32 0x4006b040 0xffffffff -wm 32 0x4006b044 0xffffffff -wm 32 0x4006b048 0xffffffff -wm 32 0x4006b04c 0xffffffff -wm 32 0x4006b050 0xffffffff -wm 32 0x4006b058 0xffffffff -wm 32 0x4006b05c 0xffffffff -wm 32 0x4006b060 0xffffffff -wm 32 0x4006b064 0xffffffff -wm 32 0x4006b068 0xffffffff -wm 32 0x4006b06c 0xffffffff - -/* - * We have to options to clock DDR controller: - * - * - Use Core-A5 clock - * - Use PLL2 PFD2 clock - * - - * Using first option without changing PLL settings doesn't seem to be - * possible given that DDRMC requires minimum of 300Mhz and MaskROM - * configures it to be clocked at 264Mhz. Changing PLL1 settings - * proved to be challenging becuase MaskROM code executing this DCD - * will also be fetching the rest of the bootloader via some - * peripheral interface whose clock is derived from Cortex-A5 clock. - * - * As a result this DCD configuration code uses the second option of - * clocking DDR wiht PLL2 PFD2 clock output - * - * Turn PLL2 on - */ -wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */ - -/* - * Wait for PLLs to lock - */ -check 32 until_any_bit_set 0x40050030 0x80000000 - -/* - * Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output - */ -clear_bits 32 0x4006b008 0x00000040 -set_bits 32 0x4006b008 0x00002000 diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg deleted file mode 100644 index 742275b92f..0000000000 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * VFxxx shared DDR IOMUX DCD code. Intended use is to share code - * between all board that copy VF610 Tower Board DDR reference - * layout/design - * - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -#define VF610_DDR_PAD_CTRL 0x00000180 /* 40 Ohm drive strength */ -#define VF610_DDR_PAD_CTRL_1 0x00010180 /* ditto + differential input */ - -wm 32 VF610_PAD_DDR_A15__DDR_A_15 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A14__DDR_A_14 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A13__DDR_A_13 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A12__DDR_A_12 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A11__DDR_A_11 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A10__DDR_A_10 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A9__DDR_A_9 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A8__DDR_A_8 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A7__DDR_A_7 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A6__DDR_A_6 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A5__DDR_A_5 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A4__DDR_A_4 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A3__DDR_A_3 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A2__DDR_A_2 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A1__DDR_A_1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_A0__DDR_A_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_BA2__DDR_BA_2 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_BA1__DDR_BA_1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_BA0__DDR_BA_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_WE__DDR_WE_B VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_RESETB VF610_DDR_PAD_CTRL - -wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h deleted file mode 100644 index 7742a002ce..0000000000 --- a/arch/arm/mach-imx/include/mach/generic.h +++ /dev/null @@ -1,256 +0,0 @@ -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include <linux/compiler.h> -#include <linux/types.h> -#include <bootsource.h> -#include <mach/imx_cpu_types.h> - -u64 imx_uid(void); - -void imx25_boot_save_loc(void); -void imx35_boot_save_loc(void); -void imx27_boot_save_loc(void); -void imx51_boot_save_loc(void); -void imx53_boot_save_loc(void); -void imx6_boot_save_loc(void); -void imx7_boot_save_loc(void); -void vf610_boot_save_loc(void); -void imx8mm_boot_save_loc(void); -void imx8mq_boot_save_loc(void); - -void imx25_get_boot_source(enum bootsource *src, int *instance); -void imx27_get_boot_source(enum bootsource *src, int *instance); -void imx35_get_boot_source(enum bootsource *src, int *instance); -void imx51_get_boot_source(enum bootsource *src, int *instance); -void imx53_get_boot_source(enum bootsource *src, int *instance); -void imx6_get_boot_source(enum bootsource *src, int *instance); -void imx7_get_boot_source(enum bootsource *src, int *instance); -void vf610_get_boot_source(enum bootsource *src, int *instance); -void imx8mm_get_boot_source(enum bootsource *src, int *instance); -void imx8mq_get_boot_source(enum bootsource *src, int *instance); - -int imx1_init(void); -int imx21_init(void); -int imx25_init(void); -int imx27_init(void); -int imx31_init(void); -int imx35_init(void); -int imx50_init(void); -int imx51_init(void); -int imx53_init(void); -int imx6_init(void); -int imx7_init(void); -int vf610_init(void); -int imx8mm_init(void); -int imx8mq_init(void); - -int imx1_devices_init(void); -int imx21_devices_init(void); -int imx25_devices_init(void); -int imx27_devices_init(void); -int imx31_devices_init(void); -int imx35_devices_init(void); -int imx50_devices_init(void); -int imx51_devices_init(void); -int imx53_devices_init(void); -int imx6_devices_init(void); - -void imx5_cpu_lowlevel_init(void); -void imx6_cpu_lowlevel_init(void); -void imx6ul_cpu_lowlevel_init(void); -void imx7_cpu_lowlevel_init(void); -void vf610_cpu_lowlevel_init(void); -void imx8mq_cpu_lowlevel_init(void); -void imx8mm_cpu_lowlevel_init(void); - -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - -extern unsigned int __imx_cpu_type; - -#ifdef CONFIG_ARCH_IMX1 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX1 -# endif -# define cpu_is_mx1() (imx_cpu_type == IMX_CPU_IMX1) -#else -# define cpu_is_mx1() (0) -#endif - -#ifdef CONFIG_ARCH_IMX21 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX21 -# endif -# define cpu_is_mx21() (imx_cpu_type == IMX_CPU_IMX21) -#else -# define cpu_is_mx21() (0) -#endif - -#ifdef CONFIG_ARCH_IMX25 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX25 -# endif -# define cpu_is_mx25() (imx_cpu_type == IMX_CPU_IMX25) -#else -# define cpu_is_mx25() (0) -#endif - -#ifdef CONFIG_ARCH_IMX27 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX27 -# endif -# define cpu_is_mx27() (imx_cpu_type == IMX_CPU_IMX27) -#else -# define cpu_is_mx27() (0) -#endif - -#ifdef CONFIG_ARCH_IMX31 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX31 -# endif -# define cpu_is_mx31() (imx_cpu_type == IMX_CPU_IMX31) -#else -# define cpu_is_mx31() (0) -#endif - -#ifdef CONFIG_ARCH_IMX35 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX35 -# endif -# define cpu_is_mx35() (imx_cpu_type == IMX_CPU_IMX35) -#else -# define cpu_is_mx35() (0) -#endif - -#ifdef CONFIG_ARCH_IMX50 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX50 -# endif -# define cpu_is_mx50() (imx_cpu_type == IMX_CPU_IMX50) -#else -# define cpu_is_mx50() (0) -#endif - - -#ifdef CONFIG_ARCH_IMX51 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX51 -# endif -# define cpu_is_mx51() (imx_cpu_type == IMX_CPU_IMX51) -#else -# define cpu_is_mx51() (0) -#endif - -#ifdef CONFIG_ARCH_IMX53 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX53 -# endif -# define cpu_is_mx53() (imx_cpu_type == IMX_CPU_IMX53) -#else -# define cpu_is_mx53() (0) -#endif - -#ifdef CONFIG_ARCH_IMX6 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX6 -# endif -# define cpu_is_mx6() (imx_cpu_type == IMX_CPU_IMX6) -#else -# define cpu_is_mx6() (0) -#endif - -#ifdef CONFIG_ARCH_IMX7 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX7 -# endif -# define cpu_is_mx7() (imx_cpu_type == IMX_CPU_IMX7) -#else -# define cpu_is_mx7() (0) -#endif - -#ifdef CONFIG_ARCH_IMX8MM -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX8MM -# endif -# define cpu_is_mx8mm() (imx_cpu_type == IMX_CPU_IMX8MM) -#else -# define cpu_is_mx8mm() (0) -#endif - -#ifdef CONFIG_ARCH_IMX8MQ -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_IMX8MQ -# endif -# define cpu_is_mx8mq() (imx_cpu_type == IMX_CPU_IMX8MQ) -#else -# define cpu_is_mx8mq() (0) -#endif - -#ifdef CONFIG_ARCH_VF610 -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type IMX_CPU_VF610 -# endif -# define cpu_is_vf610() (imx_cpu_type == IMX_CPU_VF610) -#else -# define cpu_is_vf610() (0) -#endif - -#ifdef CONFIG_BOARD_ARM_GENERIC_DT -# ifdef imx_cpu_type -# undef imx_cpu_type -# define imx_cpu_type __imx_cpu_type -# else -# define imx_cpu_type 0 -# endif -#endif - -#define cpu_is_mx23() (0) -#define cpu_is_mx28() (0) - -#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm()) - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h deleted file mode 100644 index 60f730f8ec..0000000000 --- a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This snippet can be included from a i.MX flash header configuration - * file for generating signed images. The necessary keys/certificates - * are expected in these config variables: - * - * CONFIG_HABV3_SRK_PEM - * CONFIG_HABV3_CSF_CRT_DER - * CONFIG_HABV3_IMG_CRT_DER - */ -super_root_key CONFIG_HABV3_SRK_PEM - -hab [Header] -hab Version = 3.0 -hab Security Configuration = Production -hab Hash Algorithm = SHA256 -hab Engine = RTIC -hab Certificate Format = WTLS -hab Signature Format = PKCS1 -hab UID = Generic -hab Code = 0x00 - -hab [Install SRK] -hab File = "not-used" - -hab [Install CSFK] -/* target key index in keystore 1 */ -hab File = CONFIG_HABV3_CSF_CRT_DER - -hab [Authenticate CSF] - -/* unlock the access to the DryIce registers */ -hab [Write Data] -hab Width = 4 -hab Address Data = 0x53FFC03C 0xCA693569 - -hab [Install Key] -/* verification key index in key store (1...4) */ -/* in contrast to documentation 0 seems to be valid, too */ -hab Verification index = 1 -/* target key index in key store (1...4) */ -hab Target index = 2 -hab File = CONFIG_HABV3_IMG_CRT_DER - -hab [Authenticate Data] -/* verification key index in key store (2...4) */ -hab Verification index = 2 - -hab_blocks diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h deleted file mode 100644 index 17c4d79567..0000000000 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This snippet can be included from a i.MX flash header configuration - * file for generating signed images. The necessary keys/certificates - * are expected in these config variables: - * - * CONFIG_HABV4_TABLE_BIN - * CONFIG_HABV4_CSF_CRT_PEM - * CONFIG_HABV4_IMG_CRT_PEM - */ - -hab [Header] -hab Version = 4.1 -hab Hash Algorithm = sha256 -hab Engine Configuration = 0 -hab Certificate Format = X509 -hab Signature Format = CMS -hab Engine = CAAM - -hab [Install SRK] -hab File = CONFIG_HABV4_TABLE_BIN -hab # SRK index within SRK-Table 0..3 -hab Source index = CONFIG_HABV4_SRK_INDEX - -hab [Install CSFK] -/* target key index in keystore 1 */ -hab File = CONFIG_HABV4_CSF_CRT_PEM - -hab [Authenticate CSF] - -hab [Unlock] -hab Engine = CAAM -hab Features = RNG, MID - -hab [Install Key] -/* verification key index in key store (0, 2...4) */ -hab Verification index = 0 -/* target key index in key store (2...4) */ -hab Target index = 2 -hab File = CONFIG_HABV4_IMG_CRT_PEM - -hab [Authenticate Data] -/* verification key index in key store (2...4) */ -hab Verification index = 2 - -hab_blocks - -hab_encrypt [Install Secret Key] -hab_encrypt Verification index = 0 -hab_encrypt Target index = 0 -hab_encrypt_key -hab_encrypt_key_length 256 -hab_encrypt_blob_address - -hab_encrypt [Decrypt Data] -hab_encrypt Verification index = 0 -hab_encrypt Mac Bytes = 16 - -hab_encrypt_blocks diff --git a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h deleted file mode 100644 index a3917cc74f..0000000000 --- a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This snippet can be included from a i.MX flash header configuration - * file for generating signed images. The necessary keys/certificates - * are expected in these config variables: - * - * CONFIG_HABV4_TABLE_BIN - * CONFIG_HABV4_CSF_CRT_PEM - * CONFIG_HABV4_IMG_CRT_PEM - */ -#if defined(CONFIG_HABV4) && defined(CONFIG_CPU_64) -hab [Header] -hab Version = 4.3 -hab Hash Algorithm = sha256 -hab Engine Configuration = 0 -hab Certificate Format = X509 -hab Signature Format = CMS -hab Engine = CAAM - -hab [Install SRK] -hab File = CONFIG_HABV4_TABLE_BIN -hab # SRK index within SRK-Table 0..3 -hab Source index = CONFIG_HABV4_SRK_INDEX - -hab [Install CSFK] -/* target key index in keystore 1 */ -hab File = CONFIG_HABV4_CSF_CRT_PEM - -hab [Authenticate CSF] - -hab [Unlock] -hab Engine = CAAM -hab Features = RNG, MID - -hab [Install Key] -/* verification key index in key store (0, 2...4) */ -hab Verification index = 0 -/* target key index in key store (2...4) */ -hab Target index = 2 -hab File = CONFIG_HABV4_IMG_CRT_PEM - -hab [Authenticate Data] -/* verification key index in key store (2...4) */ -hab Verification index = 2 - -hab_blocks - -hab_encrypt [Install Secret Key] -hab_encrypt Verification index = 0 -hab_encrypt Target index = 0 -hab_encrypt_key -hab_encrypt_key_length 256 -hab_encrypt_blob_address - -hab_encrypt [Decrypt Data] -hab_encrypt Verification index = 0 -hab_encrypt Mac Bytes = 16 - -hab_encrypt_blocks -#endif diff --git a/arch/arm/mach-imx/include/mach/iim.h b/arch/arm/mach-imx/include/mach/iim.h deleted file mode 100644 index cc89b0d109..0000000000 --- a/arch/arm/mach-imx/include/mach/iim.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_IMX_IIM_H -#define __MACH_IMX_IIM_H - -#include <errno.h> -#include <net.h> - -#define IIM_STAT 0x0000 -#define IIM_STATM 0x0004 -#define IIM_ERR 0x0008 -#define IIM_EMASK 0x000C -#define IIM_FCTL 0x0010 -#define IIM_UA 0x0014 -#define IIM_LA 0x0018 -#define IIM_SDAT 0x001C -#define IIM_PREV 0x0020 -#define IIM_SREV 0x0024 -#define IIM_PREG_P 0x0028 -#define IIM_SCS0 0x002C -#define IIM_SCS1 0x0030 -#define IIM_SCS2 0x0034 -#define IIM_SCS3 0x0038 - -#ifdef CONFIG_IMX_IIM -int imx_iim_read(unsigned int bank, int offset, void *buf, int count); -#else -static inline int imx_iim_read(unsigned int bank, int offset, void *buf, - int count) -{ - return -EINVAL; -} -#endif /* CONFIG_IMX_IIM */ - -static inline int imx51_iim_register_fec_ethaddr(void) -{ - int ret; - u8 buf[6]; - - ret = imx_iim_read(1, 9, buf, 6); - if (ret != 6) - return -EINVAL; - - eth_register_ethaddr(0, buf); - - return 0; -} - -static inline int imx53_iim_register_fec_ethaddr(void) -{ - return imx51_iim_register_fec_ethaddr(); -} - -static inline int imx25_iim_register_fec_ethaddr(void) -{ - int ret; - u8 buf[6]; - - ret = imx_iim_read(0, 26, buf, 6); - if (ret != 6) - return -EINVAL; - - eth_register_ethaddr(0, buf); - - return 0; -} - -#define IIM_BANK_MASK_WIDTH 3 -#define IIM_BANK_MASK_SHIFT 0 -#define IIM_BANK(n) (((n) & ((1 << IIM_BANK_MASK_WIDTH) - 1)) << IIM_BANK_MASK_SHIFT) - -#define IIM_BYTE_MASK_WIDTH 5 -#define IIM_BYTE_MASK_SHIFT IIM_BANK_MASK_WIDTH -#define IIM_BYTE(n) ((((n) >> 2) & ((1 << IIM_BYTE_MASK_WIDTH) - 1)) << IIM_BYTE_MASK_SHIFT) - -#define IIM_BIT_MASK_WIDTH 3 -#define IIM_BIT_MASK_SHIFT (IIM_BYTE_MASK_SHIFT + IIM_BYTE_MASK_WIDTH) -#define IIM_BIT(n) (((n) & ((1 << IIM_BIT_MASK_WIDTH) - 1)) << IIM_BIT_MASK_SHIFT) - -#define IIM_WIDTH_MASK_WIDTH 3 -#define IIM_WIDTH_MASK_SHIFT (IIM_BIT_MASK_SHIFT + IIM_BIT_MASK_WIDTH) -#define IIM_WIDTH(n) ((((n) - 1) & ((1 << IIM_WIDTH_MASK_WIDTH) - 1)) << IIM_WIDTH_MASK_SHIFT) - -int imx_iim_read_field(uint32_t field, unsigned *value); -int imx_iim_write_field(uint32_t field, unsigned value); -int imx_iim_permanent_write(int enable); - -#endif /* __MACH_IMX_IIM_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h deleted file mode 100644 index 891c33a3f4..0000000000 --- a/arch/arm/mach-imx/include/mach/imx-gpio.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __MACH_IMX_GPIO_H -#define __MACH_IMX_GPIO_H - -#include <io.h> - -/* - * i.MX lowlevel gpio functions. Only for use with lowlevel code. Use - * regular gpio functions outside of lowlevel code! - */ - -static inline void imx_gpio_direction(void __iomem *gdir, void __iomem *dr, - int gpio, int out, int value) -{ - uint32_t val; - - val = readl(gdir); - if (out) - val |= 1 << gpio; - else - val &= ~(1 << gpio); - writel(val, gdir); - - if (!out) - return; - - val = readl(dr); - if (value) - val |= 1 << gpio; - else - val &= ~(1 << gpio); - - writel(val, dr); -} - -static inline void imx1_gpio_direction_output(void *base, int gpio, int value) -{ - imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 1, value); -} - -#define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) -#define imx27_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) - -static inline void imx31_gpio_direction_output(void *base, int gpio, int value) -{ - imx_gpio_direction(base + 0x4, base + 0x0, gpio, 1, value); -} - -#define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) -#define imx35_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) -#define imx51_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) -#define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) -#define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) - -static inline void imx1_gpio_direction_input(void *base, int gpio, int value) -{ - imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 0, 0); -} - -#define imx21_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) -#define imx27_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) - -static inline void imx31_gpio_direction_input(void *base, int gpio) -{ - imx_gpio_direction(base + 0x4, base + 0x0, gpio, 0, 0); -} - -#define imx25_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) -#define imx35_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) -#define imx51_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) -#define imx53_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) -#define imx6_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio) - -#define imx1_gpio_val(base, gpio) readl(base + 0x1c) & (1 << gpio) ? 1 : 0 -#define imx21_gpio_val(base, gpio) imx1_gpio_val(base, gpio) -#define imx27_gpio_val(base, gpio) imx1_gpio_val(base, gpio) - -#define imx31_gpio_val(base, gpio) readl(base) & (1 << gpio) ? 1 : 0 -#define imx25_gpio_val(base, gpio) imx31_gpio_val(base, gpio) -#define imx35_gpio_val(base, gpio) imx31_gpio_val(base, gpio) -#define imx51_gpio_val(base, gpio) imx31_gpio_val(base, gpio) -#define imx53_gpio_val(base, gpio) imx31_gpio_val(base, gpio) -#define imx6_gpio_val(base, gpio) imx31_gpio_val(base, gpio) - -#endif /* __MACH_IMX_GPIO_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h deleted file mode 100644 index dc8e2eee2f..0000000000 --- a/arch/arm/mach-imx/include/mach/imx-header.h +++ /dev/null @@ -1,150 +0,0 @@ -#ifndef __IMX_HEADER_H__ -#define __IMX_HEADER_H__ - -#include <linux/types.h> - -#define HEADER_LEN 0x1000 /* length of the blank area + IVT + DCD */ -#define CSF_LEN 0x2000 /* length of the CSF (needed for HAB) */ - -#define DEK_BLOB_HEADER 8 /* length of DEK blob header */ -#define DEK_BLOB_KEY 32 /* length of DEK blob AES-256 key */ -#define DEK_BLOB_MAC 16 /* length of DEK blob MAC */ - -/* DEK blob length excluding DEK itself */ -#define DEK_BLOB_OVERHEAD (DEK_BLOB_HEADER + DEK_BLOB_KEY + DEK_BLOB_MAC) - -/* - * ============================================================================ - * i.MX flash header v1 handling. Found on i.MX35 and i.MX51 - * ============================================================================ - */ -#define DCD_BARKER 0xb17219e9 - -struct imx_flash_header { - uint32_t app_code_jump_vector; - uint32_t app_code_barker; - uint32_t app_code_csf; - uint32_t dcd_ptr_ptr; - uint32_t super_root_key; - uint32_t dcd; - uint32_t app_dest; - uint32_t dcd_barker; - uint32_t dcd_block_len; -} __attribute__((packed)); - -struct imx_boot_data { - uint32_t start; - uint32_t size; - uint32_t plugin; -} __attribute__((packed)); - -struct imx_dcd_rec_v1 { - uint32_t type; - uint32_t addr; - uint32_t val; -} __attribute__((packed)); - -#define TAG_IVT_HEADER 0xd1 -#define IVT_VERSION 0x40 -#define TAG_DCD_HEADER 0xd2 -#define DCD_VERSION 0x40 -#define TAG_UNLOCK 0xb2 -#define TAG_NOP 0xc0 -#define TAG_WRITE 0xcc -#define TAG_CHECK 0xcf -#define PARAMETER_FLAG_MASK (1 << 3) -#define PARAMETER_FLAG_SET (1 << 4) - -#define PLUGIN_HDMI_IMAGE 0x0002 - -/* - * As per Table 6-22 "eMMC/SD BOOT layout", in Normal Boot layout HDMI - * firmware image starts at LBA# 64 and ends at LBA# 271 - */ -#define PLUGIN_HDMI_SIZE ((271 - 64 + 1) * 512) - -struct imx_ivt_header { - uint8_t tag; - uint16_t length; - uint8_t version; -} __attribute__((packed)); - -struct imx_flash_header_v2 { - struct imx_ivt_header header; - - uint32_t entry; - uint32_t reserved1; - uint32_t dcd_ptr; - uint32_t boot_data_ptr; - uint32_t self; - uint32_t csf; - uint32_t reserved2; - - struct imx_boot_data boot_data; - struct imx_ivt_header dcd_header; -} __attribute__((packed)); - -static inline bool is_imx_flash_header_v2(const void *blob) -{ - const struct imx_flash_header_v2 *hdr = blob; - - return hdr->header.tag == TAG_IVT_HEADER && - hdr->header.version >= IVT_VERSION; -} - -struct config_data { - uint32_t image_load_addr; - uint32_t image_dcd_offset; - uint32_t image_size; - uint32_t max_load_size; - uint32_t load_size; - uint32_t pbl_code_size; - char *outfile; - char *srkfile; - int header_version; - off_t header_gap; - uint32_t first_opcode; - int cpu_type; - int (*check)(const struct config_data *data, uint32_t cmd, - uint32_t addr, uint32_t mask); - int (*write_mem)(const struct config_data *data, uint32_t addr, - uint32_t val, int width, int set_bits, int clear_bits); - int (*nop)(const struct config_data *data); - int csf_space; - char *csf; - int sign_image; - char *signed_hdmi_firmware_file; - int encrypt_image; - size_t dek_size; -}; - -#define MAX_RECORDS_DCD_V2 1024 -struct imx_dcd_v2_write_rec { - uint32_t addr; - uint32_t val; -} __attribute__((packed)); - -struct imx_dcd_v2_write { - uint8_t tag; - uint16_t length; - uint8_t param; - struct imx_dcd_v2_write_rec data[MAX_RECORDS_DCD_V2]; -} __attribute__((packed)); - -struct imx_dcd_v2_check { - uint8_t tag; - uint16_t length; - uint8_t param; - uint32_t addr; - uint32_t mask; - uint32_t count; -} __attribute__((packed)); - -enum imx_dcd_v2_check_cond { - until_all_bits_clear = 0, /* until ((*address & mask) == 0) { ...} */ - until_any_bit_clear = 1, /* until ((*address & mask) != mask) { ...} */ - until_all_bits_set = 2, /* until ((*address & mask) == mask) { ...} */ - until_any_bit_set = 3, /* until ((*address & mask) != 0) { ...} */ -} __attribute__((packed)); - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h deleted file mode 100644 index 73028d26cf..0000000000 --- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2008 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IMX_IPU_FB_H__ -#define __MACH_IMX_IPU_FB_H__ - -#include <fb.h> - -/* Proprietary FB_SYNC_ flags */ -#define FB_SYNC_OE_ACT_HIGH 0x80000000 -#define FB_SYNC_CLK_INVERT 0x40000000 -#define FB_SYNC_DATA_INVERT 0x20000000 -#define FB_SYNC_CLK_IDLE_EN 0x10000000 -#define FB_SYNC_SHARP_MODE 0x08000000 -#define FB_SYNC_SWAP_RGB 0x04000000 -#define FB_SYNC_CLK_SEL_EN 0x02000000 - -/* - * Specify the way your display is connected. The IPU can arbitrarily - * map the internal colors to the external data lines. We only support - * the following mappings at the moment. - */ -enum disp_data_mapping { - /* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */ - IPU_DISP_DATA_MAPPING_RGB666, - /* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */ - IPU_DISP_DATA_MAPPING_RGB565, - /* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */ - IPU_DISP_DATA_MAPPING_RGB888, -}; - -/* - * struct mx3fb_platform_data - mx3fb platform data - */ -struct imx_ipu_fb_platform_data { - struct fb_videomode *mode; - unsigned char bpp; - u_int num_modes; - enum disp_data_mapping disp_data_fmt; - void __iomem *framebuffer; - unsigned long framebuffer_size; - void __iomem *framebuffer_ovl; - unsigned long framebuffer_ovl_size; - /** hook to enable backlight and stuff */ - void (*enable)(int enable); - /* - * Fractional pixelclock divider causes jitter which some displays - * or LVDS transceivers can't handle. Disable it if necessary. - */ - int disable_fractional_divider; -}; - -#endif /* __MACH_IMX_IPU_FB_H__ */ - diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h deleted file mode 100644 index f34799a011..0000000000 --- a/arch/arm/mach-imx/include/mach/imx-nand.h +++ /dev/null @@ -1,137 +0,0 @@ -#ifndef __ASM_ARCH_NAND_H -#define __ASM_ARCH_NAND_H - -#include <linux/mtd/mtd.h> - -void imx25_nand_load_image(void); -void imx27_nand_load_image(void); -void imx31_nand_load_image(void); -void imx35_nand_load_image(void); - -void imx25_nand_relocate_to_sdram(void __noreturn (*fn)(void)); -void imx27_nand_relocate_to_sdram(void __noreturn (*fn)(void)); -void imx31_nand_relocate_to_sdram(void __noreturn (*fn)(void)); -void imx35_nand_relocate_to_sdram(void __noreturn (*fn)(void)); - -void imx25_barebox_boot_nand_external(void); -void imx27_barebox_boot_nand_external(void); -void imx31_barebox_boot_nand_external(void); -void imx35_barebox_boot_nand_external(void); -void imx_nand_set_layout(int writesize, int datawidth); - -struct imx_nand_platform_data { - int width; - unsigned int hw_ecc:1; - unsigned int flash_bbt:1; -}; - -#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) -#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) -#define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53()) -#define nfc_is_v3() nfc_is_v3_2() - -#define NFC_V1_ECC_STATUS_RESULT 0x0c -#define NFC_V1_RSLTMAIN_AREA 0x0e -#define NFC_V1_RSLTSPARE_AREA 0x10 - -#define NFC_V2_ECC_STATUS_RESULT1 0x0c -#define NFC_V2_ECC_STATUS_RESULT2 0x0e -#define NFC_V2_SPAS 0x10 - -#define NFC_V1_V2_BUF_SIZE 0x00 -#define NFC_V1_V2_BUF_ADDR 0x04 -#define NFC_V1_V2_FLASH_ADDR 0x06 -#define NFC_V1_V2_FLASH_CMD 0x08 -#define NFC_V1_V2_CONFIG 0x0a - -#define NFC_V1_V2_WRPROT 0x12 -#define NFC_V1_UNLOCKSTART_BLKADDR 0x14 -#define NFC_V1_UNLOCKEND_BLKADDR 0x16 -#define NFC_V21_UNLOCKSTART_BLKADDR 0x20 -#define NFC_V21_UNLOCKEND_BLKADDR 0x22 -#define NFC_V1_V2_NF_WRPRST 0x18 -#define NFC_V1_V2_CONFIG1 0x1a -#define NFC_V1_V2_CONFIG2 0x1c - -#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) -#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) -#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) -#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) -#define NFC_V1_V2_CONFIG1_BIG (1 << 5) -#define NFC_V1_V2_CONFIG1_RST (1 << 6) -#define NFC_V1_V2_CONFIG1_CE (1 << 7) -#define NFC_V1_V2_CONFIG1_ONE_CYCLE (1 << 8) -#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) -#define NFC_V2_CONFIG1_FP_INT (1 << 11) - -#define NFC_V1_V2_CONFIG2_INT (1 << 15) - -#define NFC_V2_SPAS_SPARESIZE(spas) ((spas) >> 1) - -#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) -#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) - -#define NFC_V3_CONFIG1 (host->regs_axi + 0x34) -#define NFC_V3_CONFIG1_SP_EN (1 << 0) -#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) - -#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) - -#define NFC_V3_LAUNCH (host->regs_axi + 0x40) - -#define NFC_V3_WRPROT (host->regs_ip + 0x0) -#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) -#define NFC_V3_WRPROT_LOCK (1 << 1) -#define NFC_V3_WRPROT_UNLOCK (1 << 2) -#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) - -#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) - -#define NFC_V3_CONFIG2 (host->regs_ip + 0x24) -#define NFC_V3_CONFIG2_PS_512 (0 << 0) -#define NFC_V3_CONFIG2_PS_2048 (1 << 0) -#define NFC_V3_CONFIG2_PS_4096 (2 << 0) -#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) -#define NFC_V3_CONFIG2_ECC_EN (1 << 3) -#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) -#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) -#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) -#define NFC_V3_MX51_CONFIG2_PPB(x) (((x) & 0x3) << 7) -#define NFC_V3_MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8) -#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) -#define NFC_V3_CONFIG2_INT_MSK (1 << 15) -#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) -#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) - -#define NFC_V3_CONFIG3 (host->regs_ip + 0x28) -#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) -#define NFC_V3_CONFIG3_FW8 (1 << 3) -#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) -#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) -#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) -#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) - -#define NFC_V3_IPC (host->regs_ip + 0x2C) -#define NFC_V3_IPC_CREQ (1 << 0) -#define NFC_V3_IPC_INT (1 << 31) - -#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) - -/* - * Operation modes for the NFC. Valid for v1, v2 and v3 - * type controllers. - */ -#define NFC_CMD (1 << 0) -#define NFC_ADDR (1 << 1) -#define NFC_INPUT (1 << 2) -#define NFC_OUTPUT (1 << 3) -#define NFC_ID (1 << 4) -#define NFC_STATUS (1 << 5) - -/* - * For external NAND boot this defines the magic value for the bad block table - * This is found at offset ARM_HEAD_SPARE_OFS in the image on NAND. - */ -#define IMX_NAND_BBT_MAGIC 0xbadb10c0 - -#endif /* __ASM_ARCH_NAND_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-pll.h b/arch/arm/mach-imx/include/mach/imx-pll.h deleted file mode 100644 index 0ccf41bcaa..0000000000 --- a/arch/arm/mach-imx/include/mach/imx-pll.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __INCLUDE_ASM_ARCH_IMX_PLL_H -#define __INCLUDE_ASM_ARCH_IMX_PLL_H - -/* - * This can be used for various PLLs found on - * i.MX SoCs. - * - * mfi + mfn / (mfd + 1) - * fpll = 2 * fref * --------------------- - * pd + 1 - */ -#define IMX_PLL_PD(x) (((x) & 0xf) << 26) -#define IMX_PLL_MFD(x) (((x) & 0x3ff) << 16) -#define IMX_PLL_MFI(x) (((x) & 0xf) << 10) -#define IMX_PLL_MFN(x) (((x) & 0x3ff) << 0) -#define IMX_PLL_BRMO (1 << 31) - -/* Assuming 24MHz input clock */ -#define MPCTL_PARAM_532 ((1 << 31) | \ - IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) -#define MPCTL_PARAM_399 \ - (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) -#define PPCTL_PARAM_300 \ - (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) - -#endif /* __INCLUDE_ASM_ARCH_IMX_PLL_H*/ diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h deleted file mode 100644 index 69e57e3cfd..0000000000 --- a/arch/arm/mach-imx/include/mach/imx1-regs.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _IMX1_REGS_H -#define _IMX1_REGS_H - -#define MX1_IO_BASE_ADDR 0x00200000 -#define MX1_IO_SIZE SZ_1M - -#define MX1_CSD0_BASE_ADDR 0x08000000 -#define MX1_CSD1_BASE_ADDR 0x0c000000 - -#define MX1_CS0_PHYS 0x10000000 -#define MX1_CS0_SIZE 0x02000000 - -#define MX1_CS1_PHYS 0x12000000 -#define MX1_CS1_SIZE 0x01000000 - -#define MX1_CS2_PHYS 0x13000000 -#define MX1_CS2_SIZE 0x01000000 - -#define MX1_CS3_PHYS 0x14000000 -#define MX1_CS3_SIZE 0x01000000 - -#define MX1_CS4_PHYS 0x15000000 -#define MX1_CS4_SIZE 0x01000000 - -#define MX1_CS5_PHYS 0x16000000 -#define MX1_CS5_SIZE 0x01000000 - -/* - * Register BASEs, based on OFFSETs - */ -#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) -#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) -#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) -#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) -#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) -#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) -#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) -#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) -#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) -#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) -#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) -#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) -#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) -#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) -#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) -#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) -#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) -#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) -#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) -#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) -#define MX1_SCM_BASE_ADDR (0x1B800 + MX1_IO_BASE_ADDR) -#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) -#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) -#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) -#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) -#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) -#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) -#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) -#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) - -/* SYSCTRL Registers (base MX1_SCM_BASE_ADDR) */ -#define MX1_SIDR 0x4 /* Silicon ID Register */ -#define MX1_FMCR 0x8 /* Function Multiplex Control Register */ -#define MX1_GPCR 0xC /* Function Multiplex Control Register */ - -/* SDRAM controller registers (base MX1_SDRAMC_BASE_ADDR) */ -#define MX1_SDCTL0 0x0 /* SDRAM 0 Control Register */ -#define MX1_SDCTL1 0x4 /* SDRAM 1 Control Register */ -#define MX1_SDMISC 0x14 /* Miscellaneous Register */ -#define MX1_SDRST 0x18 /* SDRAM Reset Register */ - -/* PLL registers (base MX1_CCM_BASE_ADDR) */ -#define MX1_CSCR 0x0 /* Clock Source Control Register */ -#define MX1_MPCTL0 0x4 /* MCU PLL Control Register 0 */ -#define MX1_MPCTL1 0x8 /* MCU PLL and System Clock Register 1 */ -#define MX1_SPCTL0 0xc /* System PLL Control Register 0 */ -#define MX1_SPCTL1 0x10 /* System PLL Control Register 1 */ -#define MX1_PCDR 0x20 /* Peripheral Clock Divider Register */ - -#define MX1_CSCR_MPLL_RESTART (1<<21) - -#endif /* _IMX1_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h deleted file mode 100644 index 1fa463a256..0000000000 --- a/arch/arm/mach-imx/include/mach/imx21-regs.h +++ /dev/null @@ -1,135 +0,0 @@ -#ifndef _IMX21_REGS_H -#define _IMX21_REGS_H - -#define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_SIZE SZ_1M -#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) -#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) -#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) -#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) -#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) -#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) -#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) -#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) -#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) -#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) -#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) -#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) -#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) -#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) -#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) -#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) -#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) -#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) -#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) -#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) -#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) -#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) -#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) -#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) -#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) -#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) -#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) -#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) -#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) -#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) -#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) -#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) -#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) -#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) -#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) -#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) -#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) -#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) - -#define MX21_AVIC_BASE_ADDR 0x10040000 - -#define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_SIZE SZ_1M -#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) - -/* Memory regions and CS */ -#define MX21_SDRAM_BASE_ADDR 0xc0000000 -#define MX21_CSD1_BASE_ADDR 0xc4000000 - -#define MX21_CS0_BASE_ADDR 0xc8000000 -#define MX21_CS1_BASE_ADDR 0xcc000000 -#define MX21_CS2_BASE_ADDR 0xd0000000 -#define MX21_CS3_BASE_ADDR 0xd1000000 -#define MX21_CS4_BASE_ADDR 0xd2000000 -#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 -#define MX21_CS5_BASE_ADDR 0xdd000000 - -/* NAND, SDRAM, WEIM etc controllers */ -#define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_SIZE SZ_256K - -#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) -#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) -#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) -#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) - -#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IRAM_SIZE 0x00001800 - -/* AIPI (base MX21_AIPI_BASE_ADDR) */ -#define MX21_AIPI1_PSR0 0x00 -#define MX21_AIPI1_PSR1 0x04 -#define MX21_AIPI2_PSR0 (0x20000 + 0x00) -#define MX21_AIPI2_PSR1 (0x20000 + 0x04) - -/* System Control (base: MX21_SYSCTRL_BASE_ADDR) */ -#define MX21_SUID0 0x4 /* Silicon ID Register (12 bytes) */ -#define MX21_SUID1 0x8 /* Silicon ID Register (12 bytes) */ -#define MX21_CID 0xC /* Silicon ID Register (12 bytes) */ -#define MX21_FMCR 0x14 /* Function Multeplexing Control Register */ -#define MX21_GPCR 0x18 /* Global Peripheral Control Register */ -#define MX21_WBCR 0x1C /* Well Bias Control Register */ -#define MX21_DSCR(x) 0x1C + ((x) << 2) /* Driving Strength Control Register 1 - 13 */ - -#define MX21_GPCR_BOOT_SHIFT 16 -#define MX21_GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) -#define MX21_GPCR_BOOT_UART_USB 0 -#define MX21_GPCR_BOOT_8BIT_NAND_2k 2 -#define MX21_GPCR_BOOT_16BIT_NAND_2k 3 -#define MX21_GPCR_BOOT_16BIT_NAND_512 4 -#define MX21_GPCR_BOOT_16BIT_CS0 5 -#define MX21_GPCR_BOOT_32BIT_CS0 6 -#define MX21_GPCR_BOOT_8BIT_NAND_512 7 - -/* SDRAM Controller registers bitfields (base: MX21_X_MEMC_BASE_ADDR) */ -#define MX21_SDCTL0 0x00 /* SDRAM 0 Control Register */ -#define MX21_SDCTL1 0x04 /* SDRAM 0 Control Register */ -#define MX21_SDRST 0x18 /* SDRAM Reset Register */ -#define MX21_SDMISC 0x14 /* SDRAM Miscellaneous Register */ - -/* PLL registers (base: MX21_CCM_BASE_ADDR) */ -#define MX21_CSCR 0x00 /* Clock Source Control Register */ -#define MX21_MPCTL0 0x04 /* MCU PLL Control Register 0 */ -#define MX21_MPCTL1 0x08 /* MCU PLL Control Register 1 */ -#define MX21_SPCTL0 0x0c /* System PLL Control Register 0 */ -#define MX21_SPCTL1 0x10 /* System PLL Control Register 1 */ -#define MX21_OSC26MCTL 0x14 /* Oscillator 26M Register */ -#define MX21_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */ -#define MX21_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */ -#define MX21_PCCR0 0x20 /* Peripheral Clock Control Register 0 */ -#define MX21_PCCR1 0x24 /* Peripheral Clock Control Register 1 */ -#define MX21_CCSR 0x28 /* Clock Control Status Register */ - -#define MX21_CSCR_MPEN (1 << 0) -#define MX21_CSCR_SPEN (1 << 1) -#define MX21_CSCR_FPM_EN (1 << 2) -#define MX21_CSCR_OSC26M_DIS (1 << 3) -#define MX21_CSCR_OSC26M_DIV1P5 (1 << 4) -#define MX21_CSCR_MCU_SEL (1 << 16) -#define MX21_CSCR_SP_SEL (1 << 17) -#define MX21_CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define MX21_CSCR_USB_DIV(d) (((d) & 0x7) << 26) -#define MX21_CSCR_PRESC(d) (((d) & 0x7) << 29) - -#define MX21_MPCTL1_BRMO (1 << 6) -#define MX21_MPCTL1_LF (1 << 15) - -#define MX21_CCSR_32K_SR (1 << 15) - -#endif /* _IMX21_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx25-fusemap.h b/arch/arm/mach-imx/include/mach/imx25-fusemap.h deleted file mode 100644 index 749b0d17b2..0000000000 --- a/arch/arm/mach-imx/include/mach/imx25-fusemap.h +++ /dev/null @@ -1,272 +0,0 @@ -#ifndef __MACH_IMX25_FUSEMAP_H -#define __MACH_IMX25_FUSEMAP_H - -#include <mach/iim.h> - -/* Fuse bank write protect */ -#define IMX25_IIM_FBWP(bank) (IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(7)) -/* Fuse Bank Override Protect */ -#define IMX25_IIM_FBOP(bank) (IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(6)) -/* Fuse Bank Read Protect */ -#define IMX25_IIM_FBRP(bank) (IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(5)) -/* Tester fuses. Burnt on the tester at the end of the wafer sort, locks bank0, rows 001C-003C */ -#define IMX25_IIM_TESTER_LOCK (IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(4)) -/* Fuse Banks Explicit Sense Protect */ -#define IMX25_IIM_FBESP(bank) (IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(3)) -/* Locking row 0068-007C, fusebank0 */ -#define IMX25_IIM_MAC_ADDR_LOCK (IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(2)) -/* Locking rows 0008 0054-0064, fusebank0 */ -#define IMX25_IIM_TRIM_LOCK (IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(1)) -/* Locking rows 0004, 000C-0018, 0040-0044, fusebank0 */ -#define IMX25_IIM_BOOT_LOCK (IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(0)) -/* Disabling the Secure JTAG Controller module clock */ -#define IMX25_IIM_SJC_DISABLE (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(7)) - -/* Controls the security mode of the JTAG debug interface */ -#define IMX25_IIM_JTAG_SMODE (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(5) | IIM_WIDTH(2)) - -/* Disable SCC debug through SJC */ -#define IMX25_IIM_JTAG_SCC (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(4)) - -/* JTAG HAB Enable Override (1 = HAB may not enable JTAG debug access */ -#define IMX25_IIM_JTAG_HEO (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(3)) - -/* Secure JTAG Re-enable. - * 0 Secure JTAG Bypass fuse is not overridden (secure JTAG bypass is allowed) - * 1 Secure JTAG Bypass fuse is overridden (secure JTAG bypass is not allowed) - */ -#define IMX25_IIM_SEC_JTAG_RE (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(1)) - -/* JTAG Debug Security Bypass. - * 0 JTAG Security bypass is not active - * 1 JTAG Security bypass is active - */ -#define IMX25_IIM_JTAG_BP (IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(0)) - -/* High Temperature Detect Configuration. A field in DryIce Analog Configuration Register (DACR) */ -#define IMX25_IIM_HTDC (IIM_BANK(0) | IIM_BYTE(8) | IIM_BIT(3) | IIM_WIDTH(3)) - -/* Low Temperature Detect Configuration. A field in DryIce Analog Configuration Register (DACR) */ -#define IMX25_IIM_LTDC (IIM_BANK(0) | IIM_BYTE(8) | IIM_BIT(0) | IIM_WIDTH(3)) - - /* Choosing the specific eSDHC, CSPI or I2C controller for booting from. */ -#define IMX25_IIM_BT_SRC (IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(6) | IIM_WIDTH(2)) - -/* SLC/MLC NAND device. (Former BT_ECC_SEL fuse) Also used as a fast boot mode indication for eMMC 4.3 protocol. - * If the bootable device is NAND then - * 0 SLC NAND device - * 1 MLC NAND device - * If the bootable device is MMC then - * 0 Do not use eMMC fast boot mode - * 1 Use eMMC fast boot mode - */ -#define IMX25_IIM_BT_MLC_SEL (IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(5)) - -/* Specifies the size of spare bytes for 4KB page size NAND Flash devices. - * If the bootable device is NAND then - * 0 128 bytes spare (Samsung) (4-IIM_BIT ECC) - * 1 218 bytes spare (Micron, Toshiba) (8-IIM_BIT ECC) - * If the bootable device is SD then - * 0 ‘FAST_BOOT’ IIM_BIT 29 in ACMD41 argument is 0 - * 1 ‘FAST_BOOT’ IIM_BIT 29 in ACMD41 argument is 1 - */ -#define IMX25_IIM_BT_SPARE_SIZE (IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(2)) - - /* Bypassing a pullup on D+ line in case of LPB. - * 1 No pullup on D+ line. - */ -#define IMX25_IIM_BT_DPLUS_BYPASS (IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(1)) - -/* USB boot source selection. Has a corresponding GPIO pin. - * 0 USB OTG Internal PHY (UTMI) - * 1 USB OTG External PHY (ULPI) - */ -#define IMX25_IIM_BT_USB_SRC (IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(0)) - -/* NAND Flash Page Size. - * If BT_MEM_CTL = NAND Flash, then - * 00 512 bytes - * 01 2K bytes - * 10 4K bytes - * 11 Reserved - */ -#define IMX25_IIM_BT_PAGE_SIZE (IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(5) | IIM_WIDTH(2)) - -/* Selects whether EEPROM device is used for load of configuration DCD data - * 0 Use EEPROM DCD - * 1 Do not use EEPROM DCD - */ -#define IMX25_IIM_BT_EEPROM_CFG (IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(4)) - -/* GPIO Boot Select. Determines whether certain boot fuse values are controlled from GPIO pins or IIM. - * 0 The fuse values are determined by GPIO pins - * 1 The fuse values are determined by fuses - */ -#define IMX25_IIM_GPIO_BT_SEL (IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(3)) - -/* Security Type. - * 001 Engineering (allows any code to be flashed and executed, even if does not have a valid signature) - * 100 Security Disabled (forinternal/testing use) - * Others Production (Security On) - */ -#define IMX25_IIM_HAB_TYPE (IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(0) | IIM_WIDTH(3)) - -/* Boot Memory Type. - * If BT_MEM_CTL = WEIM, then - * 00 NOR - * 01 Reserved - * 10 OneNand - * 11 Reserved - * If BT_MEM_CTL = NAND Flash - * 00 3 address cycles - * 01 4 address cycles - * 10 5 address cycles - * 11 Reserved - * If BT_MEM_CTL = Expansion Card Device - * 00 SD/MMC/MoviNAND HDD - * 01 Reserved - * 10 Serial ROM via I2C - * 11 Serial ROM via SPI - */ -#define IMX25_IIM_BT_MEM_TYPE (IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(5) | IIM_WIDTH(2)) - -/* Bus IIM_WIDTH and muxed/unmuxed interface. Has a corresponding GPIO pin. - * If BT_MEM_CTL=NAND then - * 00 8 IIM_BIT bus, - * 01 16 IIM_BIT bus - * 1x Reserved - * If BT_MEM_CTL=WEIM then - * 00 16 IIM_BIT addr/data muxed - * 01 16 IIM_BIT addr/data unmuxed - * 1x Reserved - * If BT_MEM_CTL=SPI then - * 00 2-addr word SPI (16-IIM_BIT) - * 01 3-addr word SPI (24-IIM_BIT) - * 1x Reserved - */ -#define IMX25_IIM_BT_BUS_WIDTH (IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(3) | IIM_WIDTH(2)) - -/* Boot Memory Control Type. (memory device) - * 00 WEIM - * 01 NAND Flash - * 10 ATA HDD - * 11 Expansion Device - * (SD/MMC, support high storage, EEPROMs. See BT_MEM_TYPE[1:0] settings for details. - */ -#define IMX25_IIM_BT_MEM_CTL (IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(1) | IIM_WIDTH(2)) - -/* Direct External Memory Boot Disable. - * 0 Direct boot from external memory is allowed - * 1 Direct boot from external memory is not allowed - */ -#define IMX25_IIM_DIR_BT_DIS (IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(0)) - -/* HAB Customer Code. Select customer code as input to HAB. */ -#define IMX25_IIM_HAB_CUS (IIM_BANK(0) | IIM_BYTE(0x18) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Silicon revision number. 0 Rev1.0 1 Rev1.1 */ -#define IMX25_IIM_SI_REV (IIM_BANK(0) | IIM_BYTE(0x1c) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* 64-IIM_BIT Unique ID. 0 <= n <= 7 */ -#define IMX25_IIM_UID(n) (IIM_BANK(0) | IIM_BYTE(0x20 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* LPB ARM core frequency. Has a corresponding GPIO pin. - * 000 133 MHz (Default) - * 001 24MHz - * 010 55.33 MHz - * 011 66 MHz - * 100 83 MHz - * 101 166 MHz - * 110 266 MHz - * 111 Normal boot frequency - */ -#define IMX25_IIM_BT_LPB_FREQ (IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(5) | IIM_WIDTH(3)) - -/* Choosing the specific UART controller for booting from. */ -#define IMX25_IIM_BT_UART_SRC (IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(2) | IIM_WIDTH(3)) - -/* Options for Low Power Boot mode. - * 00 LPB disabled - * 01 Generic PMIC and one GPIO input (Low battery) - * 10 Generic PMIC and two GPIO inputs (Low battery and Charger detect) - * 11 Atlas AP Power Management IC. - */ -#define IMX25_IIM_BT_LPB (IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(0) | IIM_WIDTH(2)) - -/* Application Processor Boot Image Version. */ -#define IMX25_IIM_AP_BI_VER_15_8 (IIM_BANK(0) | IIM_BYTE(0x48) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Application Processor Boot Image Version. */ -#define IMX25_IIM_AP_BI_VER_7_0 (IIM_BANK(0) | IIM_BYTE(0x4c) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Most significant IIM_BYTE of 256-IIM_BIT hash value of AP super root key (SRK0_HASH) */ -#define IMX25_IIM_SRK0_HASH_0 (IIM_BANK(0) | IIM_BYTE(0x50) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* For SPC statistics during production. */ -#define IMX25_IIM_STORE_COUNT (IIM_BANK(0) | IIM_BYTE(0x54) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Use for adjustment the compensator delays on silicon and the system works as a whole at 1.0V and 1.2V (DVFS) */ -#define IMX25_IIM_DVFS_DELAY_ADJUST (IIM_BANK(0) | IIM_BYTE(0x58) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* PTC version control number. */ -#define IMX25_IIM_PTC_VER (IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(5) | IIM_WIDTH(3)) - -#define IMX25_IIM_GDPTCV_VALID (IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(4)) - -/* GP domain DPTC/SPC Test Voltage. */ -#define IMX25_IIM_GDPTCV (IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(0) | IIM_WIDTH(4)) - -/* Voltage Reference Configuration. A field in DryIce Analog Configuration Register (DACR) */ -#define IMX25_IIM_VRC (IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(5) | IIM_WIDTH(3)) - -#define IMX25_IIM_LDPTCV_VALID (IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(4)) - -/* LP domain DPTC Test Voltage. */ -#define IMX25_IIM_LDPTCV (IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(0) | IIM_WIDTH(4)) - -/* Well Bias Charge Pump Frequency Adjust. Adjusting the frequency of the internal free-running oscillator. */ -#define IMX25_IIM_CPFA (IIM_BANK(0) | IIM_BYTE(0x64) | IIM_BIT(4)) - -/* Well Bias Charge Pump Set Point Adjustment. */ -#define IMX25_IIM_CPSPA (IIM_BANK(0) | IIM_BYTE(0x64) | IIM_BIT(0) | IIM_WIDTH(4)) - -/* Ethernet MAC Address, 0 <= n <= 5 */ -#define IMX25_IIM_MAC_ADDR(n) (IIM_BANK(1) | IIM_BYTE(0x68 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Locking row 0058, fusebank 1 */ -#define IMX25_IIM_USR5_LOCK (IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(4)) - -/* Lock for rows 0078–007C of fusebank 1 */ -#define IMX25_IIM_USR6_LOCK (IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(2)) - -/* Locking 0008-0020, fusebank1 */ -#define IMX25_IIM_SJC_RESP_LOCK (IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(1)) - -/* Locking SCC_KEY[255:0] */ -#define IMX25_IIM_SCC_LOCK (IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(0)) - -/* SCC Secret Key, 0 <= n <= 20 */ -#define IMX25_IIM_SCC_KEY(n) (IIM_BANK(1) | IIM_BYTE(0x4 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Fuses available for software/customers */ -#define IMX25_IIM_USR5 (IIM_BANK(1) | IIM_BYTE(0x58) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Response reference value for the secure JTAG controller, 0 <= n <= 7 */ -#define IMX25_IIM_SJC_RESP(n) (IIM_BANK(1) | IIM_BYTE(0x5c + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Fuses available for software/customers. 0 <= n <= 1 */ -#define IMX25_IIM_USR6(n) (IIM_BANK(1) | IIM_BYTE(0x78 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -/* Lock for SRK_HASH[255:160] fuses in row 0x0050, fusebank0 and in rows 0x0004-0x002C, fusebank3 */ -#define IMX25_IIM_SRK0_LOCK96 (IIM_BANK(2) | IIM_BYTE(0) | IIM_BIT(1)) - -/* Lock for SRK0_HASH[159:0] fuses in rows 0x0030-0x007C */ -#define IMX25_IIM_SRK0_LOCK160 (IIM_BANK(2) | IIM_BYTE(0) | IIM_BIT(0)) - -/* AP Super Root Key hash, bits [247:0]. - * Most significant IIM_BYTE SRK_HASH[255:248] is in the fuse bank #0, 0050 - * 1 <= n <= 31 - */ -#define IMX25_IIM_SRK0_HASH_1_31(n) (IIM_BANK(2) | IIM_BYTE(0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8)) - -#endif /* __MACH_IMX25_FUSEMAP_H */ diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h deleted file mode 100644 index a5754c57db..0000000000 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MX25_REGS_H -#define __ASM_ARCH_MX25_REGS_H - -#define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_SIZE SZ_1M -#define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_SIZE SZ_1M -#define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_SIZE SZ_1M - -#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) -#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) -#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) -#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) -#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) -#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) -#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) - -#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) -#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000) -#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000) -#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000) -#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) -#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) -#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) -#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) -#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) -#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) -#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) -#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) -#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) - -#define MX25_UART1_BASE_ADDR 0x43f90000 -#define MX25_UART2_BASE_ADDR 0x43f94000 -#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 -#define MX25_UART3_BASE_ADDR 0x5000c000 -#define MX25_UART4_BASE_ADDR 0x50008000 -#define MX25_UART5_BASE_ADDR 0x5002c000 - -#define MX25_CSPI3_BASE_ADDR 0x50004000 -#define MX25_CSPI2_BASE_ADDR 0x50010000 -#define MX25_FEC_BASE_ADDR 0x50038000 -#define MX25_SSI2_BASE_ADDR 0x50014000 -#define MX25_SSI1_BASE_ADDR 0x50034000 -#define MX25_NFC_BASE_ADDR 0xbb000000 -#define MX25_SCC_BASE_ADDR 0x53fac000 -#define MX25_IIM_BASE_ADDR 0x53ff0000 -#define MX25_DRYICE_BASE_ADDR 0x53ffc000 -#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 -#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 -#define MX25_LCDC_BASE_ADDR 0x53fbc000 -#define MX25_KPP_BASE_ADDR 0x43fa8000 -#define MX25_RNGB_BASE_ADDR 0x53fb0000 -#define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_USB_BASE_ADDR 0x53ff4000 -#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) -/* - * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 - * for the host controller. Early documentation drafts specified 0x400 and - * Freescale internal sources confirm only the latter value to work. - */ -#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) -#define MX25_CSI_BASE_ADDR 0x53ff8000 - -#define MX25_IRAM_BASE_ADDR 0x78000000 /* internal ram */ -#define MX25_IRAM_SIZE SZ_128K - -/* - * Clock Controller Module (CCM) - */ -#define MX25_CCM_MPCTL 0x00 -#define MX25_CCM_UPCTL 0x04 -#define MX25_CCM_CCTL 0x08 -#define MX25_CCM_CGCR0 0x0C -#define MX25_CCM_CGCR1 0x10 -#define MX25_CCM_CGCR2 0x14 -#define MX25_CCM_PCDR0 0x18 -#define MX25_CCM_PCDR1 0x1C -#define MX25_CCM_PCDR2 0x20 -#define MX25_CCM_PCDR3 0x24 -#define MX25_CCM_RCSR 0x28 -#define MX25_CCM_CRDR 0x2C -#define MX25_CCM_DCVR0 0x30 -#define MX25_CCM_DCVR1 0x34 -#define MX25_CCM_DCVR2 0x38 -#define MX25_CCM_DCVR3 0x3c -#define MX25_CCM_LTR0 0x40 -#define MX25_CCM_LTR1 0x44 -#define MX25_CCM_LTR2 0x48 -#define MX25_CCM_LTR3 0x4c - -#define MX25_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define MX25_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define MX25_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define MX25_PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define MX25_PDR0_AUTO_CON (1 << 0) -#define MX25_PDR0_PER_SEL (1 << 26) - -#define MX25_CCM_RCSR_MEM_CTRL_SHIFT 30 -#define MX25_CCM_RCSR_MEM_TYPE_SHIFT 28 - -/* - * Adresses and ranges of the external chip select lines - */ -#define MX25_CS0_BASE_ADDR 0xA0000000 -#define MX25_CS0_SIZE SZ_128M -#define MX25_CS1_BASE_ADDR 0xA8000000 -#define MX25_CS1_SIZE SZ_128M -#define MX25_CS2_BASE_ADDR 0xB0000000 -#define MX25_CS2_SIZE SZ_32M -#define MX25_CS3_BASE_ADDR 0xB2000000 -#define MX25_CS3_SIZE SZ_32M -#define MX25_CS4_BASE_ADDR 0xB4000000 -#define MX25_CS4_SIZE SZ_32M -#define MX25_CS5_BASE_ADDR 0xB6000000 -#define MX25_CS5_SIZE SZ_32M - -#define MX25_CSD0_BASE_ADDR 0x80000000 -#define MX25_CSD1_BASE_ADDR 0x90000000 - -#define MX25_ESDCTL_BASE_ADDR 0xb8001000 -#define MX25_WEIM_BASE_ADDR 0xb8002000 - -#endif /* __ASM_ARCH_MX25_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h deleted file mode 100644 index c45befb57c..0000000000 --- a/arch/arm/mach-imx/include/mach/imx27-regs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef _IMX27_REGS_H -#define _IMX27_REGS_H - -#define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_SIZE SZ_1M -#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) -#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) -#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) -#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) -#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) -#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) -#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) -#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) -#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) -#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) -#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) -#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) -#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) -#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) -#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) -#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) -#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) -#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) -#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) -#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) -#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) -#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) -#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) -#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) -#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) -#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) -#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) -#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) -#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) -#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) -#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) -#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) -#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) -#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) -#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) -#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) -#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) -#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) -#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) -#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) -#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) -#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) -#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) -#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) -#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) -#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) -#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) -#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) -#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) -#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) - -#define MX27_AVIC_BASE_ADDR 0x10040000 - -/* ROM patch */ -#define MX27_ROMP_BASE_ADDR 0x10041000 - -#define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_SIZE SZ_1M -#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) -#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) - -/* Memory regions and CS */ -#define MX27_CSD0_BASE_ADDR 0xa0000000 -#define MX27_CSD1_BASE_ADDR 0xb0000000 - -#define MX27_CS0_BASE_ADDR 0xc0000000 -#define MX27_CS1_BASE_ADDR 0xc8000000 -#define MX27_CS2_BASE_ADDR 0xd0000000 -#define MX27_CS3_BASE_ADDR 0xd2000000 -#define MX27_CS4_BASE_ADDR 0xd4000000 -#define MX27_CS5_BASE_ADDR 0xd6000000 - -/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ -#define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_SIZE SZ_1M -#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) -#define MX27_ESDCTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) -#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) -#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) -#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) - -#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 - -/* IRAM */ -#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IRAM_SIZE 0x0000b400 - -/* PCMCIA (base: MX27_PCMCIA_CTL_BASE_ADDR) */ -#define MX27_PCMCIA_PIPR 0x00 -#define MX27_PCMCIA_PSCR 0x04 -#define MX27_PCMCIA_PER 0x08 -#define MX27_PCMCIA_PBR(x) (0x0c + ((x) << 2)) -#define MX27_PCMCIA_POR(x) (0x28 + ((x) << 2)) -#define MX27_PCMCIA_POFR(x) (0x44 + ((x) << 2)) -#define MX27_PCMCIA_PGCR 0x60 -#define MX27_PCMCIA_PGSR 0x64 - -/* AIPI (base: MX27_AIPI_BASE_ADDR) */ -#define MX27_AIPI1_PSR0 0x00 -#define MX27_AIPI1_PSR1 0x04 -#define MX27_AIPI2_PSR0 (0x20000 + 0x00) -#define MX27_AIPI2_PSR1 (0x20000 + 0x04) - -/* System Control (base: MX27_SYSCTRL_BASE_ADDR) */ -#define MX27_CID 0x0 /* Chip ID Register */ -#define MX27_FMCR 0x14 /* Function Multeplexing Control Register */ -#define MX27_GPCR 0x18 /* Global Peripheral Control Register */ -#define MX27_WBCR 0x1C /* Well Bias Control Register */ -#define MX27_DSCR(x) (0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ - -/* PLL registers (base: MX27_CCM_BASE_ADDR) */ -#define MX27_CSCR 0x00 /* Clock Source Control Register */ -#define MX27_MPCTL0 0x04 /* MCU PLL Control Register 0 */ -#define MX27_MPCTL1 0x08 /* MCU PLL Control Register 1 */ -#define MX27_SPCTL0 0x0c /* System PLL Control Register 0 */ -#define MX27_SPCTL1 0x10 /* System PLL Control Register 1 */ -#define MX27_OSC26MCTL 0x14 /* Oscillator 26M Register */ -#define MX27_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */ -#define MX27_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */ -#define MX27_PCCR0 0x20 /* Peripheral Clock Control Register 0 */ -#define MX27_PCCR1 0x24 /* Peripheral Clock Control Register 1 */ -#define MX27_CCSR 0x28 /* Clock Control Status Register */ - -#define MX27_CSCR_MPEN (1 << 0) -#define MX27_CSCR_SPEN (1 << 1) -#define MX27_CSCR_FPM_EN (1 << 2) -#define MX27_CSCR_OSC26M_DIS (1 << 3) -#define MX27_CSCR_OSC26M_DIV1P5 (1 << 4) -#define MX27_CSCR_AHB_DIV(d) (((d) & 0x3) << 8) -#define MX27_CSCR_ARM_DIV(d) (((d) & 0x3) << 12) -#define MX27_CSCR_ARM_SRC_MPLL (1 << 15) -#define MX27_CSCR_MCU_SEL (1 << 16) -#define MX27_CSCR_SP_SEL (1 << 17) -#define MX27_CSCR_MPLL_RESTART (1 << 18) -#define MX27_CSCR_SPLL_RESTART (1 << 19) -#define MX27_CSCR_MSHC_SEL (1 << 20) -#define MX27_CSCR_H264_SEL (1 << 21) -#define MX27_CSCR_SSI1_SEL (1 << 22) -#define MX27_CSCR_SSI2_SEL (1 << 23) -#define MX27_CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define MX27_CSCR_USB_DIV(d) (((d) & 0x7) << 28) -#define MX27_CSCR_UPDATE_DIS (1 << 31) - -#define MX27_MPCTL1_BRMO (1 << 6) -#define MX27_MPCTL1_LF (1 << 15) - -#endif /* _IMX27_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h deleted file mode 100644 index 3d6c91c503..0000000000 --- a/arch/arm/mach-imx/include/mach/imx31-regs.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MX31_REGS_H -#define __ASM_ARCH_MX31_REGS_H - -#include <linux/sizes.h> - -#define MX31_IRAM_BASE_ADDR 0x1fffc000 -#define MX31_IRAM_SIZE 0x00004000 - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_SIZE SZ_1M -#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) -#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) -#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) -#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) -#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) -#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) -#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) -#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) -#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) -#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) -#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) -#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) -#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) -#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) -#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) -#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) -#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) -#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) -#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) -#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) -#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) -#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) -#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) - -#define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_SIZE SZ_1M -#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) -#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) -#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) -#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) -#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) -#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) -#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) -#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) -#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) - -#define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_SIZE SZ_1M -#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) -#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) -#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) -#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) -#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) -#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) -#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) -#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) -#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) -#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) -#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) -#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) -#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) -#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) -#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) -#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) -#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) -#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) -#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) -#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) -#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) - -#define MX31_ROMP_BASE_ADDR 0x60000000 -#define MX31_ROMP_SIZE SZ_1M - -#define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_SIZE SZ_1M - -#define MX31_IPU_MEM_BASE_ADDR 0x70000000 -#define MX31_CSD0_BASE_ADDR 0x80000000 -#define MX31_CSD1_BASE_ADDR 0x90000000 - -#define MX31_CS0_BASE_ADDR 0xa0000000 -#define MX31_CS0_SIZE SZ_128M - -#define MX31_CS1_BASE_ADDR 0xa8000000 -#define MX31_CS1_SIZE SZ_128M - -#define MX31_CS2_BASE_ADDR 0xb0000000 -#define MX31_CS2_SIZE SZ_32M - -#define MX31_CS3_BASE_ADDR 0xb2000000 -#define MX31_CS3_SIZE SZ_32M - -#define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_SIZE SZ_32M - -#define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_SIZE SZ_32M - -#define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_SIZE SZ_64K -#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) -#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) -#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) -#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) -#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) -#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR - -#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 - -/* - * Clock Controller Module (CCM) - */ -#define MX31_CCM_CCMR 0x00 -#define MX31_CCM_PDR0 0x04 -#define MX31_CCM_PDR1 0x08 -#define MX31_CCM_RCSR 0x0c -#define MX31_CCM_MPCTL 0x10 -#define MX31_CCM_UPCTL 0x14 -#define MX31_CCM_SPCTL 0x18 -#define MX31_CCM_COSR 0x1C - -#define MX31_CCMR_MDS (1 << 7) -#define MX31_CCMR_SBYCS (1 << 4) -#define MX31_CCMR_MPE (1 << 3) -#define MX31_CCMR_PRCS_MASK (3 << 1) -#define MX31_CCMR_FPM (1 << 1) -#define MX31_CCMR_CKIH (2 << 1) - -#define MX31_RCSR_NFMS (1 << 30) - -#define MX31_PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) -#define MX31_PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define MX31_PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define MX31_PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define MX31_PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define MX31_PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define MX31_PDR0_MCU_PODF(x) ((x) & 0x7) - -#define MX31_IOMUXC_GPR (MX31_IOMUXC_BASE_ADDR + 0x8) -#define MX31_IOMUXC_SW_MUX_CTL(x) (MX31_IOMUXC_BASE_ADDR + 0xc + (x) * 4) -#define MX31_IOMUXC_SW_PAD_CTL(x) (MX31_IOMUXC_BASE_ADDR + 0x154 + (x) * 4) - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MX31_MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MX31_MUX_CTL_OUT_FUNC (1 << 4) -#define MX31_MUX_CTL_OUT_ALT1 (2 << 4) -#define MX31_MUX_CTL_OUT_ALT2 (3 << 4) -#define MX31_MUX_CTL_OUT_ALT3 (4 << 4) -#define MX31_MUX_CTL_OUT_ALT4 (5 << 4) -#define MX31_MUX_CTL_OUT_ALT5 (6 << 4) -#define MX31_MUX_CTL_OUT_ALT6 (7 << 4) -#define MX31_MUX_CTL_IN_NONE (0 << 0) -#define MX31_MUX_CTL_IN_GPIO (1 << 0) -#define MX31_MUX_CTL_IN_FUNC (2 << 0) -#define MX31_MUX_CTL_IN_ALT1 (4 << 0) -#define MX31_MUX_CTL_IN_ALT2 (8 << 0) - -#define MX31_MUX_CTL_FUNC (MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC) -#define MX31_MUX_CTL_ALT1 (MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1) -#define MX31_MUX_CTL_ALT2 (MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2) -#define MX31_MUX_CTL_GPIO (MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO) - -#endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h deleted file mode 100644 index 0a3f9273c7..0000000000 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MX35_REGS_H -#define __ASM_ARCH_MX35_REGS_H - -#include <linux/sizes.h> - -#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define MX35_IRAM_SIZE SZ_128K - -#define MX35_L2CC_BASE_ADDR 0x30000000 -#define MX35_L2CC_SIZE SZ_1M - -#define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_SIZE SZ_1M -#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) -#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) -#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) -#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) -#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) -#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) -#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) -#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) -#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) -#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) -#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) -#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) -#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) -#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) -#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) -#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) -#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) - -#define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_SIZE SZ_1M -#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) -#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) -#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) -#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) -#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) -#define MX35_FEC_BASE_ADDR 0x50038000 -#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) - -#define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_SIZE SZ_1M -#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) -#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) -#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) -#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) -#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) -#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) -#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) -#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) -#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) -#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) -#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) -#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) -#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) -#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) -#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) -#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) -#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) -#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) -#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) -#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) -#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) -#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) -#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) - -/* - * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for - * HS. When host support was implemented only a preliminary document was - * available, which told 0x400. This works fine. - */ -#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) - -#define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_SIZE SZ_1M - -#define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_SIZE SZ_1M - -/* - * Memory regions and CS - */ -#define MX35_IPU_MEM_BASE_ADDR 0x70000000 -#define MX35_CSD0_BASE_ADDR 0x80000000 -#define MX35_CSD1_BASE_ADDR 0x90000000 - -#define MX35_CS0_BASE_ADDR 0xa0000000 -#define MX35_CS1_BASE_ADDR 0xa8000000 -#define MX35_CS2_BASE_ADDR 0xb0000000 -#define MX35_CS3_BASE_ADDR 0xb2000000 - -#define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_SIZE SZ_32M - -#define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_SIZE SZ_32M - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_SIZE SZ_64K -#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) -#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) -#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) -#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) -#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR - -#define MX35_NFC_BASE_ADDR 0xbb000000 -#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 - -/* - * Clock Controller Module (CCM) - */ -#define MX35_CCM_CCMR 0x00 -#define MX35_CCM_PDR0 0x04 -#define MX35_CCM_PDR1 0x08 -#define MX35_CCM_PDR2 0x0C -#define MX35_CCM_PDR3 0x10 -#define MX35_CCM_PDR4 0x14 -#define MX35_CCM_RCSR 0x18 -#define MX35_CCM_MPCTL 0x1C -#define MX35_CCM_PPCTL 0x20 -#define MX35_CCM_ACMR 0x24 -#define MX35_CCM_COSR 0x28 -#define MX35_CCM_CGR0 0x2C -#define MX35_CCM_CGR1 0x30 -#define MX35_CCM_CGR2 0x34 -#define MX35_CCM_CGR3 0x38 - -#define MX35_CCM_CGR0_CSPI1_SHIFT 10 -#define MX35_CCM_CGR0_CSPI2_SHIFT 12 -#define MX35_CCM_CGR0_EPIT1_SHIFT 20 -#define MX35_CCM_CGR0_EPIT2_SHIFT 22 -#define MX35_CCM_CGR0_ESDHC1_SHIFT 26 -#define MX35_CCM_CGR0_ESDHC2_SHIFT 28 -#define MX35_CCM_CGR0_ESDHC3_SHIFT 30 -#define MX35_CCM_CGR1_FEC_SHIFT 0 -#define MX35_CCM_CGR1_GPIO1_SHIFT 2 -#define MX35_CCM_CGR1_GPIO2_SHIFT 4 -#define MX35_CCM_CGR1_GPIO3_SHIFT 6 -#define MX35_CCM_CGR1_I2C1_SHIFT 10 -#define MX35_CCM_CGR1_I2C2_SHIFT 12 -#define MX35_CCM_CGR1_I2C3_SHIFT 14 -#define MX35_CCM_CGR1_IOMUX_SHIFT 16 -#define MX35_CCM_CGR1_KPP_SHIFT 20 -#define MX35_CCM_CGR2_UART1_SHIFT 16 -#define MX35_CCM_CGR2_UART2_SHIFT 18 -#define MX35_CCM_CGR2_UART3_SHIFT 20 -#define MX35_CCM_CGR2_USB_SHIFT 22 -#define MX35_CCM_CGR2_WDOG_SHIFT 24 - -#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25 -#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23 - -#define MX35_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define MX35_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define MX35_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define MX35_PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define MX35_PDR0_AUTO_CON (1 << 0) -#define MX35_PDR0_PER_SEL (1 << 26) - -#endif /* __ASM_ARCH_MX35_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h deleted file mode 100644 index dd5cfe99cf..0000000000 --- a/arch/arm/mach-imx/include/mach/imx5.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __MACH_MX5_H -#define __MACH_MX5_H - -void imx50_init_lowlevel(unsigned int cpufreq_mhz); -void imx51_init_lowlevel(unsigned int cpufreq_mhz); -void imx53_init_lowlevel(unsigned int cpufreq_mhz); -void imx53_init_lowlevel_early(unsigned int cpufreq_mhz); -void imx5_init_lowlevel(void); - -void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn); - -#define imx5_setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5) -#define imx5_setup_pll_864(base) imx5_setup_pll((base), 864, (( 8 << 4) + ((1 - 1) << 0)), (180 - 1), 180) -#define imx5_setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), (3 - 1), 1) -#define imx5_setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89) -#define imx5_setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1) -#define imx5_setup_pll_455(base) imx5_setup_pll((base), 455, (( 9 << 4) + ((2 - 1) << 0)), (48 - 1), 23) -#define imx5_setup_pll_400(base) imx5_setup_pll((base), 400, (( 8 << 4) + ((2 - 1) << 0)), (3 - 1), 1) -#define imx5_setup_pll_216(base) imx5_setup_pll((base), 216, (( 6 << 4) + ((3 - 1) << 0)), (4 - 1), 3) - -void imx51_babbage_power_init(void); - -#endif /* __MACH_MX53_H */ diff --git a/arch/arm/mach-imx/include/mach/imx50-regs.h b/arch/arm/mach-imx/include/mach/imx50-regs.h deleted file mode 100644 index 97ac8e2dad..0000000000 --- a/arch/arm/mach-imx/include/mach/imx50-regs.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef __MACH_IMX50_REGS_H -#define __MACH_IMX50_REGS_H - -#include <linux/sizes.h> - -#define MX50_IROM_BASE_ADDR 0x0 - -#define MX50_IRAM_BASE_ADDR 0xF8000000 -#define MX50_IRAM_SIZE SZ_128K - -/* - * SPBA global module enabled #0 - */ -#define MX50_SPBA0_BASE_ADDR 0x50000000 -#define MX50_SPBA0_SIZE SZ_1M - -#define MX50_ESDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) -#define MX50_ESDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) -#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000C000) -#define MX50_ECSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) -#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) -#define MX50_ESDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) -#define MX50_ESDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) -#define MX50_SPBA_CTRL_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define MX50_AIPS1_BASE_ADDR 0x53F00000 -#define MX50_AIPS1_SIZE SZ_512K - -#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) -#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) -#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) -#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008C000) -#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) -#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) -#define MX50_WDOG1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) -#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A0000) -#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A4000) -#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A8000) -#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000AC000) -#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B4000) -#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B8000) -#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000BC000) -#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000C0000) - -#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D0000) -#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D4000) -#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D8000) -#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000DC000) -#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000E0000) -#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000EC000) -#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000F0000) - -/* - * AIPS 2 - */ -#define MX50_AIPS2_BASE_ADDR 0x63F00000 -#define MX50_AIPS2_SIZE SZ_512K - -#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) -#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) -#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) -#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) -#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) -#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A0000) -#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A4000) -#define MX50_ECSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000AC000) -#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B0000) -#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B8000) -#define MX50_CSPI_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C0000) -#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C4000) -#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C8000) -#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000CC000) -#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000D0000) -#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000DA000) -#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000EC000) - -/* - * Memory regions and CS - */ -#define MX50_CSD0_BASE_ADDR 0x70000000 -#define MX50_CSD1_BASE_ADDR 0xB0000000 -#define MX50_CS0_BASE_ADDR 0xF0000000 -#define MX50_CS1_32MB_BASE_ADDR 0xF2000000 -#define MX50_CS1_64MB_BASE_ADDR 0xF4000000 -#define MX50_CS2_64MB_BASE_ADDR 0xF4000000 -#define MX50_CS2_96MB_BASE_ADDR 0xF6000000 -#define MX50_CS3_BASE_ADDR 0xF6000000 - -#endif /* __MACH_IMX50_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h deleted file mode 100644 index b6685ce065..0000000000 --- a/arch/arm/mach-imx/include/mach/imx51-regs.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef __MACH_IMX51_REGS_H -#define __MACH_IMX51_REGS_H - -/* WEIM registers */ -#define WEIM_CSxGCR1(n) (((n) * 0x18) + 0x00) -#define WEIM_CSxGCR2(n) (((n) * 0x18) + 0x04) -#define WEIM_CSxRCR1(n) (((n) * 0x18) + 0x08) -#define WEIM_CSxRCR2(n) (((n) * 0x18) + 0x0c) -#define WEIM_CSxWCR1(n) (((n) * 0x18) + 0x10) -#define WEIM_WCR 0x90 -#define WEIM_WIAR 0x94 -#define WEIM_EAR 0x98 - -#define MX51_IROM_BASE_ADDR 0x0 - -#define MX51_IPU_BASE_ADDR 0x40000000 - -/* - * AIPS 1 - */ -#define MX51_AIPS1_BASE_ADDR 0x73F00000 - -#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) -#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) -#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) -#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) -#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) -#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) -#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) -#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) -#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) -#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) -#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) -#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) -#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) -#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) -#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) -#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) -#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) -#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) -#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) -#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) - -/* - * AIPS 2 - */ -#define MX51_AIPS2_BASE_ADDR 0x83F00000 - -#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) -#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) -#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) -#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) -#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) -#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) -#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) -#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) -#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) -#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) -#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) -#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) -#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) -#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) -#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) -#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) -#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) -#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) -#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) -#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) -#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) -#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) -#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) -#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) -#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) -#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) -#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) -#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) -#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) -#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) -#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) -#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) - -#define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) -#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) -#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) -#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) -#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) -#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) -#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) -#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) -#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) -#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) -#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) -#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) - -#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 - -/* - * Memory regions and CS - */ -#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 -#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 -#define MX51_CSD0_BASE_ADDR 0x90000000 -#define MX51_CSD1_BASE_ADDR 0xA0000000 -#define MX51_CS0_BASE_ADDR 0xB0000000 -#define MX51_CS1_BASE_ADDR 0xB8000000 -#define MX51_CS2_BASE_ADDR 0xC0000000 -#define MX51_CS3_BASE_ADDR 0xC8000000 -#define MX51_CS4_BASE_ADDR 0xCC000000 -#define MX51_CS5_BASE_ADDR 0xCE000000 - -#endif /* __MACH_IMX51_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h deleted file mode 100644 index d45c94370d..0000000000 --- a/arch/arm/mach-imx/include/mach/imx53-regs.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef __MACH_IMX53_REGS_H -#define __MACH_IMX53_REGS_H - -#include <linux/sizes.h> - -#define MX53_IROM_BASE_ADDR 0x0 - -#define MX53_IRAM_BASE_ADDR 0xF8000000 -#define MX53_IRAM_SIZE SZ_128K - -#define MX53_SATA_BASE_ADDR 0x10000000 - -#define MX53_IPU_BASE_ADDR 0x18000000 -/* - * SPBA global module enabled #0 - */ -#define MX53_SPBA0_BASE_ADDR 0x50000000 -#define MX53_SPBA0_SIZE SZ_1M - -#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) -#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) -#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) -#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) -#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) -#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) -#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) -#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) -#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) -#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) -#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) -#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define MX53_AIPS1_BASE_ADDR 0x53F00000 -#define MX53_AIPS1_SIZE SZ_1M - -#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) -#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) -#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) -#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) -#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) -#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) -#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) -#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) -#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) -#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) -#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) -#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) -#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) -#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) -#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) -#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) -#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) -#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) -#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) -#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) -#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) -#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) -#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) -#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) -#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) -#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) - -/* - * AIPS 2 - */ -#define MX53_AIPS2_BASE_ADDR 0x63F00000 -#define MX53_AIPS2_SIZE SZ_1M - -#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) -#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) -#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) -#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) -#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) -#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) -#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) -#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) -#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) -#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) -#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) -#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) -#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) -#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) -#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) -#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) -#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) -#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) -#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) -#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) -#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) -#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) -#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) -#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) -#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) -#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) -#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) -#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) -#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) -#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) -#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) -#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) -#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) - -#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 - -/* - * Memory regions and CS - */ -#define MX53_CSD0_BASE_ADDR 0x70000000 -#define MX53_CSD1_BASE_ADDR 0xB0000000 -#define MX53_CS0_BASE_ADDR 0xF0000000 -#define MX53_CS1_32MB_BASE_ADDR 0xF2000000 -#define MX53_CS1_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_96MB_BASE_ADDR 0xF6000000 -#define MX53_CS3_BASE_ADDR 0xF6000000 - -#endif /* __MACH_IMX53_REGS_H */ - diff --git a/arch/arm/mach-imx/include/mach/imx6-anadig.h b/arch/arm/mach-imx/include/mach/imx6-anadig.h deleted file mode 100644 index 65a7dbda4c..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-anadig.h +++ /dev/null @@ -1,716 +0,0 @@ -/* - * Freescale ANADIG Register Definitions - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM___ANADIG_H -#define __ARCH_ARM___ANADIG_H - -#define HW_ANADIG_PLL_SYS (0x00000000) -#define HW_ANADIG_PLL_SYS_SET (0x00000004) -#define HW_ANADIG_PLL_SYS_CLR (0x00000008) -#define HW_ANADIG_PLL_SYS_TOG (0x0000000c) - -#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 -#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 -#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 -#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 -#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 -#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) - -#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000010) -#define HW_ANADIG_USB1_PLL_480_CTRL_SET (0x00000014) -#define HW_ANADIG_USB1_PLL_480_CTRL_CLR (0x00000018) -#define HW_ANADIG_USB1_PLL_480_CTRL_TOG (0x0000001c) - -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) - -#define HW_ANADIG_USB2_PLL_480_CTRL (0x00000020) -#define HW_ANADIG_USB2_PLL_480_CTRL_SET (0x00000024) -#define HW_ANADIG_USB2_PLL_480_CTRL_CLR (0x00000028) -#define HW_ANADIG_USB2_PLL_480_CTRL_TOG (0x0000002c) - -#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000 -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 -#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 -#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 -#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400 -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200 -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100 -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080 -#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 0x0000001C -#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003 -#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) - -#define HW_ANADIG_PLL_528 (0x00000030) -#define HW_ANADIG_PLL_528_SET (0x00000034) -#define HW_ANADIG_PLL_528_CLR (0x00000038) -#define HW_ANADIG_PLL_528_TOG (0x0000003c) - -#define BM_ANADIG_PLL_528_LOCK 0x80000000 -#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_528_BYPASS 0x00010000 -#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_528_ENABLE 0x00002000 -#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 -#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 - -#define HW_ANADIG_PLL_528_SS (0x00000040) - -#define BP_ANADIG_PLL_528_SS_STOP 16 -#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 -#define BF_ANADIG_PLL_528_SS_STOP(v) (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) -#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 -#define BP_ANADIG_PLL_528_SS_STEP 0 -#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF -#define BF_ANADIG_PLL_528_SS_STEP(v) (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) - -#define HW_ANADIG_PLL_528_NUM (0x00000050) - -#define BP_ANADIG_PLL_528_NUM_A 0 -#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_528_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) - -#define HW_ANADIG_PLL_528_DENOM (0x00000060) - -#define BP_ANADIG_PLL_528_DENOM_B 0 -#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_528_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) - -#define HW_ANADIG_PLL_AUDIO (0x00000070) -#define HW_ANADIG_PLL_AUDIO_SET (0x00000074) -#define HW_ANADIG_PLL_AUDIO_CLR (0x00000078) -#define HW_ANADIG_PLL_AUDIO_TOG (0x0000007c) - -#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 -#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 -#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) - -#define HW_ANADIG_PLL_AUDIO_NUM (0x00000080) - -#define BP_ANADIG_PLL_AUDIO_NUM_A 0 -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) - -#define HW_ANADIG_PLL_AUDIO_DENOM (0x00000090) - -#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) - -#define HW_ANADIG_PLL_VIDEO (0x000000a0) -#define HW_ANADIG_PLL_VIDEO_SET (0x000000a4) -#define HW_ANADIG_PLL_VIDEO_CLR (0x000000a8) -#define HW_ANADIG_PLL_VIDEO_TOG (0x000000ac) - -#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 -#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 -#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) - -#define HW_ANADIG_PLL_VIDEO_NUM (0x000000b0) - -#define BP_ANADIG_PLL_VIDEO_NUM_A 0 -#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) - -#define HW_ANADIG_PLL_VIDEO_DENOM (0x000000c0) - -#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 -#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) - -#define HW_ANADIG_PLL_MLB (0x000000d0) -#define HW_ANADIG_PLL_MLB_SET (0x000000d4) -#define HW_ANADIG_PLL_MLB_CLR (0x000000d8) -#define HW_ANADIG_PLL_MLB_TOG (0x000000dc) - -#define BM_ANADIG_PLL_MLB_LOCK 0x80000000 -#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 26 -#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 0x1C000000 -#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_SEL(v) (((v) << 26) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL) -#define BP_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 23 -#define BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 0x03800000 -#define BF_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG(v) (((v) << 23) & BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG) -#define BP_ANADIG_PLL_MLB_VDDD_DELAY_CFG 20 -#define BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG 0x00700000 -#define BF_ANADIG_PLL_MLB_VDDD_DELAY_CFG(v) (((v) << 20) & BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG) -#define BP_ANADIG_PLL_MLB_VDDA_DELAY_CFG 17 -#define BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG 0x000E0000 -#define BF_ANADIG_PLL_MLB_VDDA_DELAY_CFG(v) (((v) << 17) & BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG) -#define BM_ANADIG_PLL_MLB_BYPASS 0x00010000 -#define BP_ANADIG_PLL_MLB_PHASE_SEL 12 -#define BM_ANADIG_PLL_MLB_PHASE_SEL 0x00003000 -#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) (((v) << 12) & BM_ANADIG_PLL_MLB_PHASE_SEL) -#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_MLB_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_MLB_HALF_CP 0x00000200 - -#define HW_ANADIG_PLL_ENET (0x000000e0) -#define HW_ANADIG_PLL_ENET_SET (0x000000e4) -#define HW_ANADIG_PLL_ENET_CLR (0x000000e8) -#define HW_ANADIG_PLL_ENET_TOG (0x000000ec) - -#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 -#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 -#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 -#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 -#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 -#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 -#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) - -#define HW_ANADIG_PFD_480 (0x000000f0) -#define HW_ANADIG_PFD_480_SET (0x000000f4) -#define HW_ANADIG_PFD_480_CLR (0x000000f8) -#define HW_ANADIG_PFD_480_TOG (0x000000fc) - -#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_480_PFD3_FRAC 24 -#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_480_PFD3_FRAC(v) (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) -#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_480_PFD2_FRAC 16 -#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_480_PFD2_FRAC(v) (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) -#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_480_PFD1_FRAC 8 -#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_480_PFD1_FRAC(v) (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) -#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_480_PFD0_FRAC 0 -#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_480_PFD0_FRAC(v) (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) - -#define HW_ANADIG_PFD_528 (0x00000100) -#define HW_ANADIG_PFD_528_SET (0x00000104) -#define HW_ANADIG_PFD_528_CLR (0x00000108) -#define HW_ANADIG_PFD_528_TOG (0x0000010c) - -#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_528_PFD3_FRAC 24 -#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_528_PFD3_FRAC(v) (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) -#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_528_PFD2_FRAC 16 -#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_528_PFD2_FRAC(v) (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) -#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_528_PFD1_FRAC 8 -#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_528_PFD1_FRAC(v) (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) -#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_528_PFD0_FRAC 0 -#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_528_PFD0_FRAC(v) (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) - -#define HW_ANADIG_REG_1P1 (0x00000110) -#define HW_ANADIG_REG_1P1_SET (0x00000114) -#define HW_ANADIG_REG_1P1_CLR (0x00000118) -#define HW_ANADIG_REG_1P1_TOG (0x0000011c) - -#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 -#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 -#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8 -#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00 -#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG) -#define BP_ANADIG_REG_1P1_BO_OFFSET 4 -#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070 -#define BF_ANADIG_REG_1P1_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET) -#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 -#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 -#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 -#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 - -#define HW_ANADIG_REG_3P0 (0x00000120) -#define HW_ANADIG_REG_3P0_SET (0x00000124) -#define HW_ANADIG_REG_3P0_CLR (0x00000128) -#define HW_ANADIG_REG_3P0_TOG (0x0000012c) - -#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 -#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 -#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8 -#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00 -#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG) -#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 -#define BP_ANADIG_REG_3P0_BO_OFFSET 4 -#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070 -#define BF_ANADIG_REG_3P0_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET) -#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 -#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 -#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 - -#define HW_ANADIG_REG_2P5 (0x00000130) -#define HW_ANADIG_REG_2P5_SET (0x00000134) -#define HW_ANADIG_REG_2P5_CLR (0x00000138) -#define HW_ANADIG_REG_2P5_TOG (0x0000013c) - -#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 -#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 -#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 -#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8 -#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00 -#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG) -#define BP_ANADIG_REG_2P5_BO_OFFSET 4 -#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070 -#define BF_ANADIG_REG_2P5_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET) -#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 -#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 -#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 -#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 - -#define HW_ANADIG_REG_CORE (0x00000140) -#define HW_ANADIG_REG_CORE_SET (0x00000144) -#define HW_ANADIG_REG_CORE_CLR (0x00000148) -#define HW_ANADIG_REG_CORE_TOG (0x0000014c) - -#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000 -#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 -#define BP_ANADIG_REG_CORE_RAMP_RATE 27 -#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000 -#define BF_ANADIG_REG_CORE_RAMP_RATE(v) (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE) -#define BP_ANADIG_REG_CORE_REG2_ADJ 23 -#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000 -#define BF_ANADIG_REG_CORE_REG2_ADJ(v) (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ) -#define BP_ANADIG_REG_CORE_REG2_TRG 18 -#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000 -#define BF_ANADIG_REG_CORE_REG2_TRG(v) (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG) -#define BP_ANADIG_REG_CORE_REG1_ADJ 14 -#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000 -#define BF_ANADIG_REG_CORE_REG1_ADJ(v) (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ) -#define BP_ANADIG_REG_CORE_REG1_TRG 9 -#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00 -#define BF_ANADIG_REG_CORE_REG1_TRG(v) (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG) -#define BP_ANADIG_REG_CORE_REG0_ADJ 5 -#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0 -#define BF_ANADIG_REG_CORE_REG0_ADJ(v) (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ) -#define BP_ANADIG_REG_CORE_REG0_TRG 0 -#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F -#define BF_ANADIG_REG_CORE_REG0_TRG(v) (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG) - -#define HW_ANADIG_ANA_MISC0 (0x00000150) -#define HW_ANADIG_ANA_MISC0_SET (0x00000154) -#define HW_ANADIG_ANA_MISC0_CLR (0x00000158) -#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c) - -#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 -#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 -#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) -#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 -#define BP_ANADIG_ANA_MISC0_ANAMUX 21 -#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 -#define BF_ANADIG_ANA_MISC0_ANAMUX(v) (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) -#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 -#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 -#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 -#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) -#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 -#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 -#define BP_ANADIG_ANA_MISC0_OSC_I 14 -#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 -#define BF_ANADIG_ANA_MISC0_OSC_I(v) (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) -#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000 -#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 -#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 -#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 -#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 -#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070 -#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) -#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 -#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 -#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 -#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 - -#define HW_ANADIG_ANA_MISC1 (0x00000160) -#define HW_ANADIG_ANA_MISC1_SET (0x00000164) -#define HW_ANADIG_ANA_MISC1_CLR (0x00000168) -#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c) - -#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000 -#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 -#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 -#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000 -#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 -#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800 -#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 -#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 -#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 -#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) -#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 -#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F -#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) - -#define HW_ANADIG_ANA_MISC2 (0x00000170) -#define HW_ANADIG_ANA_MISC2_SET (0x00000174) -#define HW_ANADIG_ANA_MISC2_CLR (0x00000178) -#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c) - -#define BP_ANADIG_ANA_MISC2_CONTROL3 30 -#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 -#define BF_ANADIG_ANA_MISC2_CONTROL3(v) (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3) -#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 -#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 -#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) -#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 -#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 -#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) -#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 -#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 -#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) -#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 -#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 -#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000 -#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000 -#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 -#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 -#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) -#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000 -#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000 -#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000 -#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800 -#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 -#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 -#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) -#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080 -#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040 -#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020 -#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008 -#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 -#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007 -#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) - -#define HW_ANADIG_TEMPSENSE0 (0x00000180) -#define HW_ANADIG_TEMPSENSE0_SET (0x00000184) -#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188) -#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c) - -#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 -#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 -#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) -#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 -#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 -#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) -#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 -#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 -#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 -#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) -#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 -#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 -#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 - -#define HW_ANADIG_TEMPSENSE1 (0x00000190) -#define HW_ANADIG_TEMPSENSE1_SET (0x00000194) -#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198) -#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c) - -#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 -#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF -#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) - -#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0) -#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4) -#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8) -#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac) - -#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 -#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 -#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 -#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 -#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 -#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 -#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 -#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 -#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) - -#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) -#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4) -#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8) -#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc) - -#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000 -#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 -#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 -#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 -#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 - -#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0) -#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4) -#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8) -#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc) - -#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 -#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 -#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 -#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 - -#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0) -#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4) -#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8) -#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc) - -#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 -#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 -#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 -#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 - -#define HW_ANADIG_USB1_LOOPBACK (0x000001e0) -#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4) -#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8) -#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec) - -#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 -#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 -#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 -#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 -#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 -#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 -#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 -#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 -#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 - -#define HW_ANADIG_USB1_MISC (0x000001f0) -#define HW_ANADIG_USB1_MISC_SET (0x000001f4) -#define HW_ANADIG_USB1_MISC_CLR (0x000001f8) -#define HW_ANADIG_USB1_MISC_TOG (0x000001fc) - -#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000 -#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000 -#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000 -#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000 -#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000 -#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000 -#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000 -#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 -#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 - -#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) -#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204) -#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208) -#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c) - -#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 -#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 -#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 -#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 -#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 -#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 -#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 -#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 -#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) - -#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) -#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214) -#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218) -#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c) - -#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000 -#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 -#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 -#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 -#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 - -#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) -#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224) -#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228) -#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c) - -#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 -#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 -#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 -#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 - -#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) -#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234) -#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238) -#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c) - -#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 -#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 -#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 -#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 - -#define HW_ANADIG_USB2_LOOPBACK (0x00000240) -#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244) -#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248) -#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c) - -#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 -#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 -#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 -#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 -#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 -#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 -#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 -#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 -#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 - -#define HW_ANADIG_USB2_MISC (0x00000250) -#define HW_ANADIG_USB2_MISC_SET (0x00000254) -#define HW_ANADIG_USB2_MISC_CLR (0x00000258) -#define HW_ANADIG_USB2_MISC_TOG (0x0000025c) - -#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000 -#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000 -#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000 -#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000 -#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000 -#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000 -#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000 -#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 -#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 - -#define HW_ANADIG_DIGPROG (0x00000260) - -#define BP_ANADIG_DIGPROG_MAJOR 8 -#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 -#define BF_ANADIG_DIGPROG_MAJOR(v) (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) -#define BP_ANADIG_DIGPROG_MINOR 0 -#define BM_ANADIG_DIGPROG_MINOR 0x000000FF -#define BF_ANADIG_DIGPROG_MINOR(v) (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) -#endif /* __ARCH_ARM___ANADIG_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h deleted file mode 100644 index 39b3b55bb2..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MX6_MMDC_P0_MDCTL 0x021b0000 -#define MX6_MMDC_P0_MDPDC 0x021b0004 -#define MX6_MMDC_P0_MDOTC 0x021b0008 -#define MX6_MMDC_P0_MDCFG0 0x021b000c -#define MX6_MMDC_P0_MDCFG1 0x021b0010 -#define MX6_MMDC_P0_MDCFG2 0x021b0014 -#define MX6_MMDC_P0_MDMISC 0x021b0018 -#define MX6_MMDC_P0_MDSCR 0x021b001c -#define MX6_MMDC_P0_MDREF 0x021b0020 -#define MX6_MMDC_P0_MDRWD 0x021b002c -#define MX6_MMDC_P0_MDOR 0x021b0030 -#define MX6_MMDC_P0_MDASP 0x021b0040 -#define MX6_MMDC_P0_MAARCR 0x021b0400 -#define MX6_MMDC_P0_MAPSR 0x021b0404 -#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 -#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c -#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 -#define MX6_MMDC_P0_MPODTCTRL 0x021b0818 -#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c -#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 -#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 -#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 -#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c -#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 -#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 -#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 -#define MX6_MMDC_P0_MPRDDLHWCTL 0x021b0860 -#define MX6_MMDC_P0_MPWRDLHWCTL 0x021b0864 -#define MX6_MMDC_P0_MPPDCMPR2 0x021b0890 -#define MX6_MMDC_P0_MPMUR0 0x021b08b8 -#define MX6_MMDC_P0_MPDCCR 0x021b08c0 - -#define MX6_MMDC_P1_MDCTL 0x021b4000 -#define MX6_MMDC_P1_MDPDC 0x021b4004 -#define MX6_MMDC_P1_MDOTC 0x021b4008 -#define MX6_MMDC_P1_MDCFG0 0x021b400c -#define MX6_MMDC_P1_MDCFG1 0x021b4010 -#define MX6_MMDC_P1_MDCFG2 0x021b4014 -#define MX6_MMDC_P1_MDMISC 0x021b4018 -#define MX6_MMDC_P1_MDSCR 0x021b401c -#define MX6_MMDC_P1_MDREF 0x021b4020 -#define MX6_MMDC_P1_MDRWD 0x021b402c -#define MX6_MMDC_P1_MDOR 0x021b4030 -#define MX6_MMDC_P1_MDASP 0x021b4040 -#define MX6_MMDC_P1_MAPSR 0x021b4404 -#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 -#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c -#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 -#define MX6_MMDC_P1_MPODTCTRL 0x021b4818 -#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c -#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 -#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 -#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 -#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c -#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 -#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 -#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 -#define MX6_MMDC_P1_MPRDDLHWCTL 0x021b4860 -#define MX6_MMDC_P1_MPWRDLHWCTL 0x021b4864 -#define MX6_MMDC_P1_MPPDCMPR2 0x021b4890 -#define MX6_MMDC_P1_MPMUR0 0x021b48b8 -#define MX6_MMDC_P1_MPDCCR 0x021b48c0 diff --git a/arch/arm/mach-imx/include/mach/imx6-fusemap.h b/arch/arm/mach-imx/include/mach/imx6-fusemap.h deleted file mode 100644 index e14044e98a..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-fusemap.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __MACH_IMX_IMX6_OCOTP_H -#define __MACH_IMX_IMX6_OCOTP_H - -#include <mach/ocotp-fusemap.h> - -#define IMX6_OCOTP_SI_REV (OCOTP_WORD(0x430) | OCOTP_BIT(16) | OCOTP_WIDTH(4)) -#define IMX6_OCOTP_SATA_RST_SRC (OCOTP_WORD(0x430) | OCOTP_BIT(24) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_VPU_DISABLE (OCOTP_WORD(0x440) | OCOTP_BIT(15) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_SPEED_GRADING (OCOTP_WORD(0x440) | OCOTP_BIT(16) | OCOTP_WIDTH(2)) -#define IMX6_OCOTP_DDR3_CONFIG (OCOTP_WORD(0x460) | OCOTP_BIT(8) | OCOTP_WIDTH(8)) -#define IMX6_OCOTP_HDCP (OCOTP_WORD(0x460) | OCOTP_BIT(16) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_TZASC_ENABLE (OCOTP_WORD(0x460) | OCOTP_BIT(28) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_SDMMC_HYS_EN (OCOTP_WORD(0x460) | OCOTP_BIT(29) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_eMMC_RESET_EN (OCOTP_WORD(0x460) | OCOTP_BIT(30) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_BT_LPB_POLARITY (OCOTP_WORD(0x470) | OCOTP_BIT(20) | OCOTP_WIDTH(1)) -#define IMX6_OCOTP_LPB_BOOT (OCOTP_WORD(0x470) | OCOTP_BIT(21) | OCOTP_WIDTH(2)) -#define IMX6_OCOTP_MMC_DLL_DLY (OCOTP_WORD(0x470) | OCOTP_BIT(24) | OCOTP_WIDTH(7)) -#define IMX6_OCOTP_TEMPERATURE_GRADE (OCOTP_WORD(0x480) | OCOTP_BIT(6) | OCOTP_WIDTH(2)) -#define IMX6_OCOTP_POWER_GATE_CORES (OCOTP_WORD(0x4d0) | OCOTP_BIT(31) | OCOTP_WIDTH(1)) -#define IMX6DQ_OCOTP_TEST_PORT_DISABLE (OCOTP_WORD(0x6e0) | OCOTP_BIT(1) | OCOTP_WIDTH(1)) -#define IMX6SDL_OCOTP_FIELD_RETURN (OCOTP_WORD(0x6e0) | OCOTP_BIT(0) | OCOTP_WIDTH(1)) - -#endif /* __MACH_IMX_IMX6_OCOTP_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h deleted file mode 100644 index 9385b342c2..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h +++ /dev/null @@ -1,331 +0,0 @@ -#ifndef __MACH_MMDC_H -#define __MACH_MMDC_H - -#include <mach/imx6-regs.h> - -#define P0_IPS (void __iomem *)MX6_MMDC_P0_BASE_ADDR -#define P1_IPS (void __iomem *)MX6_MMDC_P1_BASE_ADDR - -#define MDCTL 0x000 -#define MDPDC 0x004 -#define MDSCR 0x01c -#define MDMISC 0x018 -#define MDREF 0x020 -#define MAPSR 0x404 -#define MPZQHWCTRL 0x800 -#define MPWLGCR 0x808 -#define MPWLDECTRL0 0x80c -#define MPWLDECTRL1 0x810 -#define MPPDCMPR1 0x88c -#define MPSWDAR 0x894 -#define MPRDDLCTL 0x848 -#define MPMUR 0x8b8 -#define MPDGCTRL0 0x83c -#define MPDGCTRL1 0x840 -#define MPRDDLCTL 0x848 -#define MPWRDLCTL 0x850 -#define MPRDDLHWCTL 0x860 -#define MPWRDLHWCTL 0x864 -#define MPDGHWST0 0x87c -#define MPDGHWST1 0x880 -#define MPDGHWST2 0x884 -#define MPDGHWST3 0x888 - -#define MMDCx_MDCTL_SDE0 0x80000000 -#define MMDCx_MDCTL_SDE1 0x40000000 - -#define MMDCx_MDCTL_DSIZ_16B 0x00000000 -#define MMDCx_MDCTL_DSIZ_32B 0x00010000 -#define MMDCx_MDCTL_DSIZ_64B 0x00020000 - -#define MMDCx_MDMISC_DDR_4_BANKS 0x00000020 - -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5a8) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b0) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x524) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x51c) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x518) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x50c) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b8) -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5c0) - - -int mmdc_do_write_level_calibration(void); -int mmdc_do_dqs_calibration(void); -void mmdc_print_calibration_results(void); - -/* MMDC P0/P1 Registers */ -struct mmdc_p_regs { - u32 mdctl; - u32 mdpdc; - u32 mdotc; - u32 mdcfg0; - u32 mdcfg1; - u32 mdcfg2; - u32 mdmisc; - u32 mdscr; - u32 mdref; - u32 res1[2]; - u32 mdrwd; - u32 mdor; - u32 res2[3]; - u32 mdasp; - u32 res3[240]; - u32 mapsr; - u32 res4[254]; - u32 mpzqhwctrl; - u32 res5[2]; - u32 mpwldectrl0; - u32 mpwldectrl1; - u32 res6; - u32 mpodtctrl; - u32 mprddqby0dl; - u32 mprddqby1dl; - u32 mprddqby2dl; - u32 mprddqby3dl; - u32 res7[4]; - u32 mpdgctrl0; - u32 mpdgctrl1; - u32 res8; - u32 mprddlctl; - u32 res9; - u32 mpwrdlctl; - u32 res10[25]; - u32 mpmur0; -}; - -#define MX6SX_IOM_DDR_BASE 0x020e0200 -struct mx6sx_iomux_ddr_regs { - u32 res1[59]; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_dqm2; - u32 dram_dqm3; - u32 dram_ras; - u32 dram_cas; - u32 res2[2]; - u32 dram_sdwe_b; - u32 dram_odt0; - u32 dram_odt1; - u32 dram_sdba0; - u32 dram_sdba1; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_sdqs2; - u32 dram_sdqs3; - u32 dram_reset; -}; - -#define MX6SX_IOM_GRP_BASE 0x020e0500 -struct mx6sx_iomux_grp_regs { - u32 res1[61]; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_ddrpke; - u32 grp_ddrpk; - u32 grp_ddrhys; - u32 grp_ddrmode; - u32 grp_b0ds; - u32 grp_b1ds; - u32 grp_ctlds; - u32 grp_ddr_type; - u32 grp_b2ds; - u32 grp_b3ds; -}; - -/* - * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) - */ -#define MX6DQ_IOM_DDR_BASE 0x020e0500 -struct mx6dq_iomux_ddr_regs { - u32 res1[3]; - u32 dram_sdqs5; - u32 dram_dqm5; - u32 dram_dqm4; - u32 dram_sdqs4; - u32 dram_sdqs3; - u32 dram_dqm3; - u32 dram_sdqs2; - u32 dram_dqm2; - u32 res2[16]; - u32 dram_cas; - u32 res3[2]; - u32 dram_ras; - u32 dram_reset; - u32 res4[2]; - u32 dram_sdclk_0; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdclk_1; - u32 dram_sdcke1; - u32 dram_sdodt0; - u32 dram_sdodt1; - u32 res5; - u32 dram_sdqs0; - u32 dram_dqm0; - u32 dram_sdqs1; - u32 dram_dqm1; - u32 dram_sdqs6; - u32 dram_dqm6; - u32 dram_sdqs7; - u32 dram_dqm7; -}; - -#define MX6DQ_IOM_GRP_BASE 0x020e0700 -struct mx6dq_iomux_grp_regs { - u32 res1[18]; - u32 grp_b7ds; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 res2; - u32 grp_ddrpke; - u32 res3[6]; - u32 grp_ddrmode; - u32 res4[3]; - u32 grp_b0ds; - u32 grp_b1ds; - u32 grp_ctlds; - u32 res5; - u32 grp_b2ds; - u32 grp_ddr_type; - u32 grp_b3ds; - u32 grp_b4ds; - u32 grp_b5ds; - u32 grp_b6ds; -}; - -#define MX6SDL_IOM_DDR_BASE 0x020e0400 -struct mx6sdl_iomux_ddr_regs { - u32 res1[25]; - u32 dram_cas; - u32 res2[2]; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_dqm2; - u32 dram_dqm3; - u32 dram_dqm4; - u32 dram_dqm5; - u32 dram_dqm6; - u32 dram_dqm7; - u32 dram_ras; - u32 dram_reset; - u32 res3[2]; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_sdclk_1; - u32 dram_sdodt0; - u32 dram_sdodt1; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_sdqs2; - u32 dram_sdqs3; - u32 dram_sdqs4; - u32 dram_sdqs5; - u32 dram_sdqs6; - u32 dram_sdqs7; -}; - -#define MX6SDL_IOM_GRP_BASE 0x020e0700 -struct mx6sdl_iomux_grp_regs { - u32 res1[18]; - u32 grp_b7ds; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_ddrpke; - u32 res2[2]; - u32 grp_ddrmode; - u32 grp_b0ds; - u32 res3; - u32 grp_ctlds; - u32 grp_b1ds; - u32 grp_ddr_type; - u32 grp_b2ds; - u32 grp_b3ds; - u32 grp_b4ds; - u32 grp_b5ds; - u32 res4; - u32 grp_b6ds; -}; - -/* Device Information: Varies per DDR3 part number and speed grade */ -struct mx6_ddr3_cfg { - u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ - u8 density; /* chip density (Gb) (1,2,4,8) */ - u8 width; /* bus width (bits) (4,8,16) */ - u8 banks; /* number of banks */ - u8 rowaddr; /* row address bits (11-16)*/ - u8 coladdr; /* col address bits (9-12) */ - u8 pagesz; /* page size (K) (1-2) */ - u16 trcd; /* tRCD=tRP=CL (ns*100) */ - u16 trcmin; /* tRC min (ns*100) */ - u16 trasmin; /* tRAS min (ns*100) */ - u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ -}; - -/* System Information: Varies per board design, layout, and term choices */ -struct mx6_ddr_sysinfo { - u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ - u8 cs_density; /* density per chip select (Gb) */ - u8 ncs; /* number chip selects used (1|2) */ - char cs1_mirror;/* enable address mirror (0|1) */ - char bi_on; /* Bank interleaving enable */ - u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ - u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ - u8 ralat; /* Read Additional Latency (0-7) */ - u8 walat; /* Write Additional Latency (0-3) */ - u8 mif3_mode; /* Command prediction working mode */ - u8 rst_to_cke; /* Time from SDE enable to CKE rise */ - u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ - u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ -}; - -/* - * Board specific calibration: - * This includes write leveling calibration values as well as DQS gating - * and read/write delays. These values are board/layout/device specific. - * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 - * (DOC-96412) to determine these values over a range of boards and - * temperatures. - */ -struct mx6_mmdc_calibration { - /* write leveling calibration */ - u32 p0_mpwldectrl0; - u32 p0_mpwldectrl1; - u32 p1_mpwldectrl0; - u32 p1_mpwldectrl1; - /* read DQS gating */ - u32 p0_mpdgctrl0; - u32 p0_mpdgctrl1; - u32 p1_mpdgctrl0; - u32 p1_mpdgctrl1; - /* read delay */ - u32 p0_mprddlctl; - u32 p1_mprddlctl; - /* write delay */ - u32 p0_mpwrdlctl; - u32 p1_mpwrdlctl; -}; - -/* configure iomux (pinctl/padctl) */ -void mx6dq_dram_iocfg(unsigned width, - const struct mx6dq_iomux_ddr_regs *, - const struct mx6dq_iomux_grp_regs *); -void mx6sdl_dram_iocfg(unsigned width, - const struct mx6sdl_iomux_ddr_regs *, - const struct mx6sdl_iomux_grp_regs *); -void mx6sx_dram_iocfg(unsigned width, - const struct mx6sx_iomux_ddr_regs *, - const struct mx6sx_iomux_grp_regs *); - -/* configure mx6 mmdc registers */ -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, - const struct mx6_mmdc_calibration *, - const struct mx6_ddr3_cfg *); - -#endif /* __MACH_MMDC_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h deleted file mode 100644 index 1ba22b5bc6..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef __MACH_IMX6_REGS_H -#define __MACH_IMX6_REGS_H - -#define MX6_GPMI_BASE_ADDR 0x00112000 - -#define MX6_FAST1_BASE_ADDR 0x00c00000 -#define MX6_FAST2_BASE_ADDR 0x00b00000 - -#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000 -#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000 - -/* Defines for Blocks connected via AIPS (SkyBlue) */ -#define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR -#define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR - -/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */ -#define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000) -#define MX6_ECSPI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x08000) -#define MX6_ECSPI2_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x0C000) -#define MX6_ECSPI3_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x10000) -#define MX6_ECSPI4_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x14000) -#define MX6_ECSPI5_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x18000) -#define MX6_UART1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x20000) -#define MX6_ESAI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x24000) -#define MX6_SSI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x28000) -#define MX6_SSI2_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x2C000) -#define MX6_SSI3_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x30000) -#define MX6_ASRC_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x34000) -#define MX6_SPBA_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x3C000) -#define MX6_VPU_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x40000) - -#define MX6_IPU1_BASE_ADDR 0x02400000 -#define MX6_IPU2_BASE_ADDR 0x02800000 - -/* ATZ#1- On Platform */ -#define MX6_AIPS1_ON_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x7C000) - -/* ATZ#1- Off Platform */ -#define MX6_AIPS1_OFF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x80000) - -#define MX6_PWM1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x0000) -#define MX6_PWM2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4000) -#define MX6_PWM3_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x8000) -#define MX6_PWM4_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0xC000) -#define MX6_CAN1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x10000) -#define MX6_CAN2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x14000) -#define MX6_GPT_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x18000) -#define MX6_GPIO1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x1C000) -#define MX6_GPIO2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x20000) -#define MX6_GPIO3_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x24000) -#define MX6_GPIO4_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x28000) -#define MX6_GPIO5_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x2C000) -#define MX6_GPIO6_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x30000) -#define MX6_GPIO7_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x34000) -#define MX6_KPP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x38000) -#define MX6_WDOG1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x3C000) -#define MX6_WDOG2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x40000) -#define MX6_CCM_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x44000) -#define MX6_ANATOP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x48000) -#define MX6_USBPHY1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x49000) -#define MX6_USBPHY2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4a000) -#define MX6_SNVS_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000) -#define MX6_EPIT1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x50000) -#define MX6_EPIT2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x54000) -#define MX6_SRC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x58000) -#define MX6_GPC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x5C000) -#define MX6_IOMUXC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x60000) -#define MX6_DCIC1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x64000) -#define MX6_DCIC2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x68000) -#define MX6_DMA_REQ_PORT_HOST_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x6C000) - -/* ATZ#2- On Platform */ -#define MX6_AIPS2_ON_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x7C000) - -/* ATZ#2- Off Platform */ -#define MX6_AIPS2_OFF_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x80000) - -/* ATZ#2 - Global enable (0) */ -#define MX6_CAAM_BASE_ADDR (MX6_ATZ2_BASE_ADDR) -#define MX6_ARM_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x40000) - -#define MX6_USBOH3_PL301_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x0000) -#define MX6_USBOH3_USB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4000) -#define MX6_OTG_BASE_ADDR MX6_USBOH3_USB_BASE_ADDR -#define MX6_ENET_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x8000) -#define MX6_MLB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0xC000) - -#define MX6_USDHC1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x10000) -#define MX6_USDHC2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x14000) -#define MX6_USDHC3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x18000) -#define MX6_USDHC4_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x1C000) -#define MX6_I2C1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x20000) -#define MX6_I2C2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x24000) -#define MX6_I2C3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x28000) -#define MX6_ROMCP_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MX6_MMDC_P0_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x30000) -#define MX6_MMDC_P1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x34000) -#define MX6_WEIM_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x38000) -#define MX6_OCOTP_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x3C000) -#define MX6_CSU_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x40000) -#define MX6_IP2APB_PERFMON1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x44000) -#define MX6_IP2APB_PERFMON2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x48000) -#define MX6_IP2APB_PERFMON3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4C000) -#define MX6_IP2APB_TZASC1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x50000) -#define MX6_IP2APB_TZASC2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x54000) -#define MX6_AUDMUX_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x58000) -#define MX6_MIPI_CSI2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MX6_MIPI_DSI_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x60000) -#define MX6_VDOA_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x64000) -#define MX6ULL_WDOG3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x64000) -#define MX6_UART2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x68000) -#define MX6_UART3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x6C000) -#define MX6_UART4_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x70000) -#define MX6_UART5_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x74000) -#define MX6_IP2APB_USBPHY1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x78000) -#define MX6_IP2APB_USBPHY2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000) - -#define MX6_SATA_BASE_ADDR 0x02200000 - -#define MX6_MMDC_PORT01_BASE_ADDR 0x10000000 -#define MX6_MMDC_PORT0_BASE_ADDR 0x80000000 - - -#endif /* __MACH_IMX6_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h deleted file mode 100644 index b65cdaaf40..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ /dev/null @@ -1,135 +0,0 @@ -#ifndef __MACH_IMX6_H -#define __MACH_IMX6_H - -#include <io.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/revision.h> - -#include <poweroff.h> - -void __noreturn imx6_pm_stby_poweroff(struct poweroff_handler *handler); - -#define IMX6_ANATOP_SI_REV 0x260 -#define IMX6SL_ANATOP_SI_REV 0x280 - -#define IMX6_CPUTYPE_IMX6SL 0x160 -#define IMX6_CPUTYPE_IMX6S 0x161 -#define IMX6_CPUTYPE_IMX6DL 0x261 -#define IMX6_CPUTYPE_IMX6SX 0x462 -#define IMX6_CPUTYPE_IMX6D 0x263 -#define IMX6_CPUTYPE_IMX6DP 0x1263 -#define IMX6_CPUTYPE_IMX6Q 0x463 -#define IMX6_CPUTYPE_IMX6QP 0x1463 -#define IMX6_CPUTYPE_IMX6UL 0x164 -#define IMX6_CPUTYPE_IMX6ULL 0x165 - -#define SCU_CONFIG 0x04 - -static inline int scu_get_core_count(void) -{ -#if __LINUX_ARM_ARCH__ <= 7 - unsigned long base; - unsigned int ncores; - - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); - - ncores = readl(base + SCU_CONFIG); - return (ncores & 0x03) + 1; -#else - return 0; -#endif -} - -#define SI_REV_CPUTYPE(s) (((s) >> 16) & 0xff) -#define SI_REV_MAJOR(s) (((s) >> 8) & 0xf) -#define SI_REV_MINOR(s) ((s) & 0xf) - -static inline uint32_t __imx6_read_si_rev(void) -{ - uint32_t si_rev; - uint32_t cpu_type; - - si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); - cpu_type = SI_REV_CPUTYPE(si_rev); - - if (cpu_type >= 0x61 && cpu_type <= 0x65) - return si_rev; - - /* try non-MX6-standard SI_REV reg offset for MX6SL */ - si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); - cpu_type = SI_REV_CPUTYPE(si_rev); - - if (si_rev == 0x60) - return si_rev; - - return 0; -} - -static inline int __imx6_cpu_type(void) -{ - uint32_t si_rev = __imx6_read_si_rev(); - uint32_t cpu_type = SI_REV_CPUTYPE(si_rev); - - /* intentionally skip scu_get_core_count() for MX6SL */ - if (cpu_type == IMX6_CPUTYPE_IMX6SL) - return IMX6_CPUTYPE_IMX6SL; - - cpu_type |= scu_get_core_count() << 8; - - if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) && - SI_REV_MAJOR(si_rev) >= 1) - cpu_type |= 0x1000; - - return cpu_type; -} - -int imx6_cpu_type(void); - -#define DEFINE_MX6_CPU_TYPE(str, type) \ - static inline int cpu_mx6_is_##str(void) \ - { \ - return __imx6_cpu_type() == type; \ - } \ - \ - static inline int cpu_is_##str(void) \ - { \ - if (!cpu_is_mx6()) \ - return 0; \ - return cpu_mx6_is_##str(); \ - } - -/* - * Below are defined: - * - * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(), - * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(), - * cpu_is_mx6ull() - */ -DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S); -DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL); -DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q); -DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP); -DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); -DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP); -DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); -DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); -DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); -DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL); - -static inline int __imx6_cpu_revision(void) -{ - uint32_t si_rev = __imx6_read_si_rev(); - u8 major_part, minor_part; - - major_part = (si_rev >> 8) & 0xf; - minor_part = si_rev & 0xf; - - return ((major_part + 1) << 4) | minor_part; -} - -int imx6_cpu_revision(void); - -u64 imx6_uid(void); - -#endif /* __MACH_IMX6_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h deleted file mode 100644 index a312e63a99..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MX6_IOM_DRAM_ADDR00 0x020e0424 -#define MX6_IOM_DRAM_ADDR01 0x020e0428 -#define MX6_IOM_DRAM_ADDR10 0x020e042c -#define MX6_IOM_DRAM_ADDR11 0x020e0430 -#define MX6_IOM_DRAM_ADDR12 0x020e0434 -#define MX6_IOM_DRAM_ADDR13 0x020e0438 -#define MX6_IOM_DRAM_ADDR14 0x020e043c -#define MX6_IOM_DRAM_ADDR15 0x020e0440 -#define MX6_IOM_DRAM_ADDR02 0x020e0444 -#define MX6_IOM_DRAM_ADDR03 0x020e0448 -#define MX6_IOM_DRAM_ADDR04 0x020e044c -#define MX6_IOM_DRAM_ADDR05 0x020e0450 -#define MX6_IOM_DRAM_ADDR06 0x020e0454 -#define MX6_IOM_DRAM_ADDR07 0x020e0458 -#define MX6_IOM_DRAM_ADDR08 0x020e045c -#define MX6_IOM_DRAM_ADDR09 0x020e0460 - -#define MX6_IOM_DRAM_DQM0 0x020e0470 -#define MX6_IOM_DRAM_DQM1 0x020e0474 -#define MX6_IOM_DRAM_DQM2 0x020e0478 -#define MX6_IOM_DRAM_DQM3 0x020e047c -#define MX6_IOM_DRAM_DQM4 0x020e0480 -#define MX6_IOM_DRAM_DQM5 0x020e0484 -#define MX6_IOM_DRAM_DQM6 0x020e0488 -#define MX6_IOM_DRAM_DQM7 0x020e048c - -#define MX6_IOM_DRAM_CAS 0x020e0464 -#define MX6_IOM_DRAM_RAS 0x020e0490 -#define MX6_IOM_DRAM_RESET 0x020e0494 -#define MX6_IOM_DRAM_SDBA0 0x020e0498 -#define MX6_IOM_DRAM_SDBA1 0x020e049c -#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac -#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 -#define MX6_IOM_DRAM_SDBA2 0x020e04a0 -#define MX6_IOM_DRAM_SDCKE0 0x020e04a4 -#define MX6_IOM_DRAM_SDCKE1 0x020e04a8 -#define MX6_IOM_DRAM_SDODT0 0x020e04b4 -#define MX6_IOM_DRAM_SDODT1 0x020e04b8 - -#define MX6_IOM_DRAM_SDQS0 0x020e04bc -#define MX6_IOM_DRAM_SDQS1 0x020e04c0 -#define MX6_IOM_DRAM_SDQS2 0x020e04c4 -#define MX6_IOM_DRAM_SDQS3 0x020e04c8 -#define MX6_IOM_DRAM_SDQS4 0x020e04cc -#define MX6_IOM_DRAM_SDQS5 0x020e04d0 -#define MX6_IOM_DRAM_SDQS6 0x020e04d4 -#define MX6_IOM_DRAM_SDQS7 0x020e04d8 - -#define MX6_IOM_GRP_B0DS 0x020e0764 -#define MX6_IOM_GRP_B1DS 0x020e0770 -#define MX6_IOM_GRP_B2DS 0x020e0778 -#define MX6_IOM_GRP_B3DS 0x020e077c -#define MX6_IOM_GRP_B4DS 0x020e0780 -#define MX6_IOM_GRP_B5DS 0x020e0784 -#define MX6_IOM_GRP_B6DS 0x020e078c -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0754 -#define MX6_IOM_GRP_DDRHYS 0x020e075c -#define MX6_IOM_GRP_DDRMODE 0x020e0760 -#define MX6_IOM_GRP_CTLDS 0x020e076c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0774 diff --git a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h deleted file mode 100644 index f910574370..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MX6_IOM_DRAM_DQM0 0x020e05ac -#define MX6_IOM_DRAM_DQM1 0x020e05b4 -#define MX6_IOM_DRAM_DQM2 0x020e0528 -#define MX6_IOM_DRAM_DQM3 0x020e0520 -#define MX6_IOM_DRAM_DQM4 0x020e0514 -#define MX6_IOM_DRAM_DQM5 0x020e0510 -#define MX6_IOM_DRAM_DQM6 0x020e05bc -#define MX6_IOM_DRAM_DQM7 0x020e05c4 - -#define MX6_IOM_DRAM_CAS 0x020e056c -#define MX6_IOM_DRAM_RAS 0x020e0578 -#define MX6_IOM_DRAM_RESET 0x020e057c -#define MX6_IOM_DRAM_SDCLK_0 0x020e0588 -#define MX6_IOM_DRAM_SDCLK_1 0x020e0594 -#define MX6_IOM_DRAM_SDBA2 0x020e058c -#define MX6_IOM_DRAM_SDCKE0 0x020e0590 -#define MX6_IOM_DRAM_SDCKE1 0x020e0598 -#define MX6_IOM_DRAM_SDODT0 0x020e059c -#define MX6_IOM_DRAM_SDODT1 0x020e05a0 - -#define MX6_IOM_DRAM_SDQS0 0x020e05a8 -#define MX6_IOM_DRAM_SDQS1 0x020e05b0 -#define MX6_IOM_DRAM_SDQS2 0x020e0524 -#define MX6_IOM_DRAM_SDQS3 0x020e051c -#define MX6_IOM_DRAM_SDQS4 0x020e0518 -#define MX6_IOM_DRAM_SDQS5 0x020e050c -#define MX6_IOM_DRAM_SDQS6 0x020e05b8 -#define MX6_IOM_DRAM_SDQS7 0x020e05c0 - -#define MX6_IOM_GRP_B0DS 0x020e0784 -#define MX6_IOM_GRP_B1DS 0x020e0788 -#define MX6_IOM_GRP_B2DS 0x020e0794 -#define MX6_IOM_GRP_B3DS 0x020e079c -#define MX6_IOM_GRP_B4DS 0x020e07a0 -#define MX6_IOM_GRP_B5DS 0x020e07a4 -#define MX6_IOM_GRP_B6DS 0x020e07a8 -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0758 -#define MX6_IOM_GRP_DDRMODE 0x020e0774 -#define MX6_IOM_GRP_CTLDS 0x020e078c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0798 diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h deleted file mode 100644 index de6eb1bbd1..0000000000 --- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef __MACH_IMX7_CCM_REGS_H__ -#define __MACH_IMX7_CCM_REGS_H__ - -#define IMX7_CCM_CCGR_UART1 148 -#define IMX7_CCM_CCGR_UART2 149 - -#define IMX7_CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128) - -/* - * Taken from "Table 5-11. Clock Root Table" from i.MX7 Dual Processor - * Reference Manual - */ -#define IMX7_UART1_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xaf80) -#define IMX7_UART1_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000) - -#define IMX7_UART2_CLK_ROOT IMX7_CLOCK_ROOT_INDEX(0xb000) -#define IMX7_UART2_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000) - -/* 0 <= n <= 190 */ -#define IMX7_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define IMX7_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) - -/* 0 <= n <= 120 */ -#define IMX7_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define IMX7_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define IMX7_CCM_TARGET_ROOTn_ENABLE BIT(28) - - -#define IMX7_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define IMX7_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b00) -#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX7_CCM_CCGR_SETTINGn(n, 0b01) -#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX7_CCM_CCGR_SETTINGn(n, 0b10) -#define IMX7_CCM_CCGR_SETTINGn_NEEDED(n) IMX7_CCM_CCGR_SETTINGn(n, 0b11) - -static inline void imx7_early_setup_uart_clock(void) -{ - void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1)); - writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M, - ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT)); - writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0), - ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1)); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h deleted file mode 100644 index e66b2da11e..0000000000 --- a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (C) 2017 Pengutronix, Fridolin Tux <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MX7_DDRC_MSTR 0x307a0000 -#define MX7_DDRC_STAT 0x307a0004 -#define MX7_DDRC_MRCTRL0 0x307a0010 -#define MX7_DDRC_MRCTRL1 0x307a0014 -#define MX7_DDRC_MRSTAT 0x307a0018 -#define MX7_DDRC_DERATEEN 0x307a0020 -#define MX7_DDRC_DERATEINT 0x307a0024 -#define MX7_DDRC_PWRCTL 0x307a0030 -#define MX7_DDRC_PWRTMG 0x307a0034 -#define MX7_DDRC_HWLPCTL 0x307a0038 -#define MX7_DDRC_RFSHCTL0 0x307a0050 -#define MX7_DDRC_RFSHCTL1 0x307a0054 -#define MX7_DDRC_RFSHCTL3 0x307a0060 -#define MX7_DDRC_RFSHTMG 0x307a0064 -#define MX7_DDRC_INIT0 0x307a00d0 -#define MX7_DDRC_INIT1 0x307a00d4 -#define MX7_DDRC_INIT2 0x307a00d8 -#define MX7_DDRC_INIT3 0x307a00dc -#define MX7_DDRC_INIT4 0x307a00e0 -#define MX7_DDRC_INIT5 0x307a00e4 -#define MX7_DDRC_RANKCTL 0x307a00f4 -#define MX7_DDRC_DRAMTMG0 0x307a0100 -#define MX7_DDRC_DRAMTMG1 0x307a0104 -#define MX7_DDRC_DRAMTMG2 0x307a0108 -#define MX7_DDRC_DRAMTMG3 0x307a010c -#define MX7_DDRC_DRAMTMG4 0x307a0110 -#define MX7_DDRC_DRAMTMG5 0x307a0114 -#define MX7_DDRC_DRAMTMG6 0x307a0118 -#define MX7_DDRC_DRAMTMG7 0x307a011c -#define MX7_DDRC_DRAMTMG8 0x307a0120 -#define MX7_DDRC_ZQCTL0 0x307a0180 -#define MX7_DDRC_ZQCTL1 0x307a0184 -#define MX7_DDRC_ZQCTL2 0x307a0188 -#define MX7_DDRC_ZQSTAT 0x307a018c -#define MX7_DDRC_DFITMG0 0x307a0190 -#define MX7_DDRC_DFITMG1 0x307a0194 -#define MX7_DDRC_DFILPCFG0 0x307a0198 -#define MX7_DDRC_DFIUPD0 0x307a01a0 -#define MX7_DDRC_DFIUPD1 0x307a01a4 -#define MX7_DDRC_DFIUPD2 0x307a01a8 -#define MX7_DDRC_DFIUPD3 0x307a01ac -#define MX7_DDRC_DFIMISC 0x307a01b0 -#define MX7_DDRC_ADDRMAP0 0x307a0200 -#define MX7_DDRC_ADDRMAP1 0x307a0204 -#define MX7_DDRC_ADDRMAP2 0x307a0208 -#define MX7_DDRC_ADDRMAP3 0x307a020c -#define MX7_DDRC_ADDRMAP4 0x307a0210 -#define MX7_DDRC_ADDRMAP5 0x307a0214 -#define MX7_DDRC_ADDRMAP6 0x307a0218 -#define MX7_DDRC_ODTCFG 0x307a0240 -#define MX7_DDRC_ODTMAP 0x307a0244 -#define MX7_DDRC_SCHED 0x307a0250 -#define MX7_DDRC_SCHED1 0x307a0254 -#define MX7_DDRC_PERFHPR1 0x307a025c -#define MX7_DDRC_PERFLPR1 0x307a0264 -#define MX7_DDRC_PERFWR1 0x307a026c -#define MX7_DDRC_PERFVPR1 0x307a0274 -#define MX7_DDRC_PERFVPW1 0x307a0278 -#define MX7_DDRC_DBG0 0x307a0300 -#define MX7_DDRC_DBG1 0x307a0304 -#define MX7_DDRC_DBGCAM 0x307a0308 -#define MX7_DDRC_DBGCMD 0x307a030c -#define MX7_DDRC_DBGSTAT 0x307a0310 -#define MX7_DDRC_SWCTL 0x307a0320 -#define MX7_DDRC_SWSTAT 0x307a0324 - -#define MX7_DDRC_MP_PSTAT 0x307a03fc -#define MX7_DDRC_MP_PCCFG 0x307a0400 -#define MX7_DDRC_MP_PCFGR_0 0x307a0404 -#define MX7_DDRC_MP_PCFGW_0 0x307a0408 -#define MX7_DDRC_MP_PCFGIDMASKCH_00 0x307a0410 -#define MX7_DDRC_MP_PCFGIDVALUECH_00 0x307a0414 -#define MX7_DDRC_MP_PCFGIDMASKCH_10 0x307a0418 -#define MX7_DDRC_MP_PCFGIDVALUECH_10 0x307a041c -#define MX7_DDRC_MP_PCFGIDMASKCH_20 0x307a0420 -#define MX7_DDRC_MP_PCFGIDVALUECH_20 0x307a0424 -#define MX7_DDRC_MP_PCFGIDMASKCH_30 0x307a0428 -#define MX7_DDRC_MP_PCFGIDVALUECH_30 0x307a042c -#define MX7_DDRC_MP_PCFGIDMASKCH_40 0x307a0430 -#define MX7_DDRC_MP_PCFGIDVALUECH_40 0x307a0434 -#define MX7_DDRC_MP_PCFGIDMASKCH_50 0x307a0438 -#define MX7_DDRC_MP_PCFGIDVALUECH_50 0x307a043c -#define MX7_DDRC_MP_PCFGIDMASKCH_60 0x307a0440 -#define MX7_DDRC_MP_PCFGIDVALUECH_60 0x307a0444 -#define MX7_DDRC_MP_PCFGIDMASKCH_70 0x307a0448 -#define MX7_DDRC_MP_PCFGIDVALUECH_70 0x307a044c -#define MX7_DDRC_MP_PCFGIDMASKCH_80 0x307a0450 -#define MX7_DDRC_MP_PCFGIDVALUECH_80 0x307a0454 -#define MX7_DDRC_MP_PCFGIDMASKCH_90 0x307a0458 -#define MX7_DDRC_MP_PCFGIDVALUECH_90 0x307a045c -#define MX7_DDRC_MP_PCFGIDMASKCH_100 0x307a0460 -#define MX7_DDRC_MP_PCFGIDVALUECH_100 0x307a0464 -#define MX7_DDRC_MP_PCFGIDMASKCH_110 0x307a0468 -#define MX7_DDRC_MP_PCFGIDVALUECH_110 0x307a046c -#define MX7_DDRC_MP_PCFGIDMASKCH_120 0x307a0470 -#define MX7_DDRC_MP_PCFGIDVALUECH_120 0x307a0474 -#define MX7_DDRC_MP_PCFGIDMASKCH_130 0x307a0478 -#define MX7_DDRC_MP_PCFGIDVALUECH_130 0x307a047c -#define MX7_DDRC_MP_PCFGIDMASKCH_140 0x307a0480 -#define MX7_DDRC_MP_PCFGIDVALUECH_140 0x307a0484 -#define MX7_DDRC_MP_PCFGIDMASKCH_150 0x307a0488 -#define MX7_DDRC_MP_PCFGIDVALUECH_150 0x307a048c -#define MX7_DDRC_MP_PCTRL_0 0x307a0490 -#define MX7_DDRC_MP_PCFGQOS0_0 0x307a0494 -#define MX7_DDRC_MP_PCFGQOS1_0 0x307a0498 -#define MX7_DDRC_MP_PCFGWQOS0_0 0x307a049c -#define MX7_DDRC_MP_PCFGWQOS1_0 0x307a04a0 -#define MX7_DDRC_MP_SARBASE0 0x307a0f04 -#define MX7_DDRC_MP_SARSIZE0 0x307a0f08 -#define MX7_DDRC_MP_SARBASE1 0x307a0f0c -#define MX7_DDRC_MP_SARSIZE1 0x307a0f10 -#define MX7_DDRC_MP_SARBASE2 0x307a0f14 -#define MX7_DDRC_MP_SARSIZE2 0x307a0f18 -#define MX7_DDRC_MP_SARBASE3 0x307a0f1c -#define MX7_DDRC_MP_SARSIZE3 0x307a0f20 - -#define MX7_DDR_PHY_PHY_CON0 0x30790000 -#define MX7_DDR_PHY_PHY_CON1 0x30790004 -#define MX7_DDR_PHY_PHY_CON2 0x30790008 -#define MX7_DDR_PHY_PHY_CON3 0x3079000c -#define MX7_DDR_PHY_PHY_CON4 0x30790010 -#define MX7_DDR_PHY_PHY_CON5 0x30790014 -#define MX7_DDR_PHY_LP_CON0 0x30790018 -#define MX7_DDR_PHY_RODT_CON0 0x3079001c -#define MX7_DDR_PHY_OFFSET_RD_CON0 0x30790020 -#define MX7_DDR_PHY_OFFSET_WR_CON0 0x30790030 -#define MX7_DDR_PHY_GATE_CODE_CON0 0x30790040 -#define MX7_DDR_PHY_SHIFTC_CON0 0x3079004c -#define MX7_DDR_PHY_CMD_SDLL_CON0 0x30790050 -#define MX7_DDR_PHY_LVL_CON0 0x3079006c -#define MX7_DDR_PHY_LVL_CON3 0x30790078 -#define MX7_DDR_PHY_CMD_DESKEW_CON0 0x3079007c -#define MX7_DDR_PHY_CMD_DESKEW_CON1 0x30790080 -#define MX7_DDR_PHY_CMD_DESKEW_CON2 0x30790084 -#define MX7_DDR_PHY_CMD_DESKEW_CON3 0x30790088 -#define MX7_DDR_PHY_CMD_DESKEW_CON4 0x30790094 -#define MX7_DDR_PHY_DRVDS_CON0 0x3079009c -#define MX7_DDR_PHY_MDLL_CON0 0x307900b0 -#define MX7_DDR_PHY_MDLL_CON1 0x307900b4 -#define MX7_DDR_PHY_ZQ_CON0 0x307900c0 -#define MX7_DDR_PHY_ZQ_CON1 0x307900c4 -#define MX7_DDR_PHY_ZQ_CON2 0x307900c8 -#define MX7_DDR_PHY_RD_DESKEW_CON0 0x30790190 -#define MX7_DDR_PHY_RD_DESKEW_CON3 0x3079019c -#define MX7_DDR_PHY_RD_DESKEW_CON6 0x307901a8 -#define MX7_DDR_PHY_RD_DESKEW_CON9 0x307901b4 -#define MX7_DDR_PHY_RD_DESKEW_CON12 0x307901c0 -#define MX7_DDR_PHY_RD_DESKEW_CON15 0x307901cc -#define MX7_DDR_PHY_RD_DESKEW_CON18 0x307901d8 -#define MX7_DDR_PHY_RD_DESKEW_CON21 0x307901e4 -#define MX7_DDR_PHY_WR_DESKEW_CON0 0x307901f0 -#define MX7_DDR_PHY_WR_DESKEW_CON3 0x307901fc -#define MX7_DDR_PHY_WR_DESKEW_CON6 0x30790208 -#define MX7_DDR_PHY_WR_DESKEW_CON9 0x30790214 -#define MX7_DDR_PHY_WR_DESKEW_CON12 0x30790220 -#define MX7_DDR_PHY_WR_DESKEW_CON15 0x3079022c -#define MX7_DDR_PHY_WR_DESKEW_CON18 0x30790238 -#define MX7_DDR_PHY_WR_DESKEW_CON21 0x30790244 -#define MX7_DDR_PHY_DM_DESKEW_CON 0x30790250 -#define MX7_DDR_PHY_RDATA0 0x307903a0 -#define MX7_DDR_PHY_STAT0 0x307903ac diff --git a/arch/arm/mach-imx/include/mach/imx7-regs.h b/arch/arm/mach-imx/include/mach/imx7-regs.h deleted file mode 100644 index 21e2830b97..0000000000 --- a/arch/arm/mach-imx/include/mach/imx7-regs.h +++ /dev/null @@ -1,121 +0,0 @@ -#ifndef __MACH_IMX7_REGS_H -#define __MACH_IMX7_REGS_H - -/* Defines for Blocks connected via AIPS */ -#define MX7_AIPS1_BASE_ADDR 0x30000000 -#define MX7_AIPS2_BASE_ADDR 0x30400000 -#define MX7_AIPS3_BASE_ADDR 0x30800000 - -/* ATZ#1- On Platform */ -#define MX7_DAP_BASE_ADDR (MX7_AIPS1_BASE_ADDR) -#define MX7_AIPS1_CONFIG_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x1F0000) - -/* ATZ#1- Off Platform */ -#define MX7_GPIO1_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x200000) -#define MX7_GPIO2_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x210000) -#define MX7_GPIO3_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x220000) -#define MX7_GPIO4_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x230000) -#define MX7_GPIO5_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x240000) -#define MX7_GPIO6_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x250000) -#define MX7_GPIO7_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x260000) -#define MX7_IOMUXC_LPSR_GPR_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x270000) -#define MX7_WDOG1_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x280000) -#define MX7_WDOG2_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x290000) -#define MX7_WDOG3_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2A0000) -#define MX7_WDOG4_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2B0000) -#define MX7_IOMUXC_LPSR_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2C0000) -#define MX7_GPT1_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2D0000) -#define MX7_GPT2_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2E0000) -#define MX7_GPT3_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x2F0000) -#define MX7_GPT4_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x300000) -#define MX7_ROMCP_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x310000) -#define MX7_KPP_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x320000) -#define MX7_IOMUXC_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x330000) -#define MX7_IOMUXC_GPR_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x340000) -#define MX7_OCOTP_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x350000) -#define MX7_ANATOP_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x360000) -#define MX7_SNVS_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x370000) -#define MX7_CCM_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x380000) -#define MX7_SRC_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x390000) -#define MX7_GPC_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x3A0000) -#define MX7_SEMAPHORE1_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x3B0000) -#define MX7_SEMAPHORE2_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x3C0000) -#define MX7_RDC_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x3D0000) -#define MX7_CSU_BASE_ADDR (MX7_AIPS1_BASE_ADDR + 0x3E0000) - -/* ATZ#2- On Platform */ -#define MX7_AIPS2_CONFIG_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x1F0000) - -/* ATZ#2- Off Platform */ -#define MX7_ADC1_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x230000) -#define MX7_ADC2_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x230000) -#define MX7_ECSPI4_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x230000) -#define MX7_FTM1_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x240000) -#define MX7_FTM2_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x250000) -#define MX7_PWM1_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x260000) -#define MX7_PWM2_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x270000) -#define MX7_PWM3_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x280000) -#define MX7_PWM4_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x290000) -#define MX7_SYSCNT_RD_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x2A0000) -#define MX7_SYSCNT_CMP_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x2B0000) -#define MX7_SYSCNT_CTRL_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x2C0000) -#define MX7_PCIE_PHY_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x2D0000) -#define MX7_EPDC_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x2F0000) -#define MX7_PXP_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x300000) -#define MX7_CSI_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x310000) -#define MX7_LCDIF_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x330000) -#define MX7_MIPI_CSI_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x350000) -#define MX7_MIPI_DSI_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x360000) -#define MX7_TZASC_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x380000) -#define MX7_DDRPHY_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x390000) -#define MX7_DDRC_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x3A0000) -#define MX7_IP2APB_PERFMON1_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x3C0000) -#define MX7_IP2APB_PERFMON2_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x3D0000) -#define MX7_AXI_DEBUG_MON_BASE_ADDR (MX7_AIPS2_BASE_ADDR + 0x3E0000) - -/* ATZ#3- On Platform */ -#define MX7_ECSPI1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x20000) -#define MX7_ECSPI2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x30000) -#define MX7_ECSPI3_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x40000) -#define MX7_UART1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x60000) -#define MX7_UART2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x90000) -#define MX7_UART3_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x80000) -#define MX7_SAI1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0xA0000) -#define MX7_SAI2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0xB0000) -#define MX7_SAI3_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0xC0000) -#define MX7_SPBA_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x90000) -#define MX7_CAAM_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x100000) -#define MX7_AIPS3_CONFIG_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x1F0000) - -/* ATZ#3- Off Platform */ -#define MX7_CAN1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x200000) -#define MX7_CAN2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x210000) -#define MX7_I2C1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x220000) -#define MX7_I2C2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x230000) -#define MX7_I2C3_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x240000) -#define MX7_I2C4_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x250000) -#define MX7_UART4_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x260000) -#define MX7_UART5_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x270000) -#define MX7_UART6_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x280000) -#define MX7_UART7_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x290000) -#define MX7_MU_A_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x2A0000) -#define MX7_MU_B_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x2B0000) -#define MX7_SEM_HS_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x2C0000) -#define MX7_USBOH2_PL301_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x2D0000) -#define MX7_OTG1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x310000) -#define MX7_OTG2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x320000) -#define MX7_USBOH3_USB_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x330000) -#define MX7_USDHC1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x340000) -#define MX7_USDHC2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x350000) -#define MX7_USDHC3_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x360000) -#define MX7_SIM1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x390000) -#define MX7_SIM2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3A0000) -#define MX7_QSPI_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3B0000) -#define MX7_WEIM_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3C0000) -#define MX7_SDMA_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3D0000) -#define MX7_ENET1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3E0000) -#define MX7_ENET2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3F0000) - -#define MX7_DDR_BASE_ADDR 0x80000000 - -#endif /* __MACH_IMX7_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx7.h b/arch/arm/mach-imx/include/mach/imx7.h deleted file mode 100644 index 8518935468..0000000000 --- a/arch/arm/mach-imx/include/mach/imx7.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef __MACH_IMX7_H -#define __MACH_IMX7_H - -#include <io.h> -#include <mach/generic.h> -#include <mach/imx7-regs.h> -#include <mach/revision.h> - -void imx7_init_lowlevel(void); - -#define ANADIG_DIGPROG_IMX7 0x800 - -#define IMX7_CPUTYPE_IMX7S 0x71 -#define IMX7_CPUTYPE_IMX7D 0x72 - -static inline int __imx7_cpu_type(void) -{ - void __iomem *ocotp = IOMEM(MX7_OCOTP_BASE_ADDR); - - if (readl(ocotp + 0x450) & 1) - return IMX7_CPUTYPE_IMX7S; - else - return IMX7_CPUTYPE_IMX7D; -} - -static inline int imx7_cpu_type(void) -{ - if (!cpu_is_mx7()) - return 0; - - return __imx7_cpu_type(); -} - -static inline int imx7_cpu_revision(void) -{ - if (!cpu_is_mx7()) - return IMX_CHIP_REV_UNKNOWN; - - /* register value has the format of the IMX_CHIP_REV_* macros */ - return readl(MX7_ANATOP_BASE_ADDR + ANADIG_DIGPROG_IMX7) & 0xff; -} - -#define DEFINE_MX7_CPU_TYPE(str, type) \ - static inline int cpu_mx7_is_##str(void) \ - { \ - return __imx7_cpu_type() == type; \ - } \ - \ - static inline int cpu_is_##str(void) \ - { \ - if (!cpu_is_mx7()) \ - return 0; \ - return cpu_mx7_is_##str(); \ - } - -DEFINE_MX7_CPU_TYPE(mx7s, IMX7_CPUTYPE_IMX7S); -DEFINE_MX7_CPU_TYPE(mx7d, IMX7_CPUTYPE_IMX7D); - -#endif /* __MACH_IMX7_H */
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h deleted file mode 100644 index 743ed6cda0..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __MACH_IMX8_CCM_REGS_H__ -#define __MACH_IMX8_CCM_REGS_H__ - -#include <mach/imx8mq-regs.h> - -#define IMX8M_CCM_CCGR_DDR1 5 -#define IMX8M_CCM_CCGR_I2C1 23 -#define IMX8M_CCM_CCGR_I2C2 24 -#define IMX8M_CCM_CCGR_I2C3 25 -#define IMX8M_CCM_CCGR_I2C4 26 -#define IMX8M_CCM_CCGR_SCTR 57 -#define IMX8M_CCM_CCGR_UART1 73 -#define IMX8M_CCM_CCGR_UART2 74 -#define IMX8M_CCM_CCGR_UART3 75 -#define IMX8M_CCM_CCGR_UART4 76 -#define IMX8M_CCM_CCGR_GIC 92 - -/* - * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad - * Applications Processor Reference Manual - */ -#define IMX8M_ARM_A53_CLK_ROOT 0 -#define IMX8M_DRAM_SEL_CFG 48 -#define IMX8M_DRAM_ALT_CLK_ROOT 64 -#define IMX8M_DRAM_APB_CLK_ROOT 65 -#define IMX8M_UART1_CLK_ROOT 94 -#define IMX8M_UART2_CLK_ROOT 95 -#define IMX8M_UART3_CLK_ROOT 96 -#define IMX8M_UART4_CLK_ROOT 97 -#define IMX8M_GIC_CLK_ROOT 100 -#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000) - -/* 0 <= n <= 190 */ -#define IMX8M_CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) -#define IMX8M_CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) - -/* 0 <= n <= 120 */ -#define IMX8M_CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) - -#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n) ((n) & 0x0000003f) -#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n) (((n) << 16) & 0x00070000) -#define IMX8M_CCM_TARGET_ROOTn_MUX(x) ((x) << 24) -#define IMX8M_CCM_TARGET_ROOTn_ENABLE BIT(28) - -#define IMX8M_CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) -#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b00) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b01) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10) -#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11) - -void imx8m_early_setup_uart_clock(void); -void imx8mm_early_clock_init(void); -void imx8m_clock_set_target_val(int clock_id, u32 val); -void imx8m_ccgr_clock_enable(int index); -void imx8m_ccgr_clock_disable(int index); - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h deleted file mode 100644 index e5f466c291..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8m-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __MACH_IMX8M_REGS_H -#define __MACH_IMX8M_REGS_H - -#define MX8M_GPIO1_BASE_ADDR 0X30200000 -#define MX8M_GPIO2_BASE_ADDR 0x30210000 -#define MX8M_GPIO3_BASE_ADDR 0x30220000 -#define MX8M_GPIO4_BASE_ADDR 0x30230000 -#define MX8M_GPIO5_BASE_ADDR 0x30240000 -#define MX8M_WDOG1_BASE_ADDR 0x30280000 -#define MX8M_WDOG2_BASE_ADDR 0x30290000 -#define MX8M_WDOG3_BASE_ADDR 0x302A0000 -#define MX8M_IOMUXC_BASE_ADDR 0x30330000 -#define MX8M_IOMUXC_GPR_BASE_ADDR 0x30340000 -#define MX8M_OCOTP_BASE_ADDR 0x30350000 -#define MX8M_ANATOP_BASE_ADDR 0x30360000 -#define MX8M_CCM_BASE_ADDR 0x30380000 -#define MX8M_SRC_BASE_ADDR 0x30390000 -#define MX8M_SRC_DDRC_RCR_ADDR 0x30391000 -#define MX8M_GPC_BASE_ADDR 0x303A0000 -#define MX8M_SYSCNT_CTRL_BASE_ADDR 0x306C0000 -#define MX8M_UART1_BASE_ADDR 0x30860000 -#define MX8M_UART3_BASE_ADDR 0x30880000 -#define MX8M_UART2_BASE_ADDR 0x30890000 -#define MX8M_I2C1_BASE_ADDR 0x30A20000 -#define MX8M_I2C2_BASE_ADDR 0x30A30000 -#define MX8M_I2C3_BASE_ADDR 0x30A40000 -#define MX8M_I2C4_BASE_ADDR 0x30A50000 -#define MX8M_UART4_BASE_ADDR 0x30A60000 -#define MX8M_USDHC1_BASE_ADDR 0x30B40000 -#define MX8M_USDHC2_BASE_ADDR 0x30B50000 -#define MX8M_DDRC_PHY_BASE_ADDR 0x3c000000 -#define MX8M_DDRC_DDR_SS_GPR0 (MX8M_DDRC_PHY_BASE_ADDR + 0x01000000) -#define MX8M_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) -#define MX8M_DDRC_CTL_BASE_ADDR MX8M_DDRC_IPS_BASE_ADDR(0) -#define MX8M_DDR_CSD1_BASE_ADDR 0x40000000 - -#endif /* __MACH_IMX8M_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h deleted file mode 100644 index 1325c78dbc..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8mm-regs.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __MACH_IMX8MM_REGS_H -#define __MACH_IMX8MM_REGS_H - -#include <mach/imx8m-regs.h> - -#define MX8MM_M4_BOOTROM_BASE_ADDR 0x007e0000 - -#define MX8MM_GPIO1_BASE_ADDR 0x30200000 -#define MX8MM_GPIO2_BASE_ADDR 0x30210000 -#define MX8MM_GPIO3_BASE_ADDR 0x30220000 -#define MX8MM_GPIO4_BASE_ADDR 0x30230000 -#define MX8MM_GPIO5_BASE_ADDR 0x30240000 -#define MX8MM_WDOG1_BASE_ADDR 0x30280000 -#define MX8MM_WDOG2_BASE_ADDR 0x30290000 -#define MX8MM_WDOG3_BASE_ADDR 0x302a0000 -#define MX8MM_IOMUXC_BASE_ADDR 0x30330000 -#define MX8MM_IOMUXC_GPR_BASE_ADDR 0x30340000 -#define MX8MM_OCOTP_BASE_ADDR 0x30350000 -#define MX8MM_ANATOP_BASE_ADDR 0x30360000 -#define MX8MM_CCM_BASE_ADDR 0x30380000 -#define MX8MM_SRC_BASE_ADDR 0x30390000 -#define MX8MM_GPC_BASE_ADDR 0x303a0000 -#define MX8MM_SYSCNT_RD_BASE_ADDR 0x306a0000 -#define MX8MM_SYSCNT_CMP_BASE_ADDR 0x306b0000 -#define MX8MM_SYSCNT_CTRL_BASE_ADDR 0x306c0000 -#define MX8MM_UART1_BASE_ADDR 0x30860000 -#define MX8MM_UART3_BASE_ADDR 0x30880000 -#define MX8MM_UART2_BASE_ADDR 0x30890000 -#define MX8MM_I2C1_BASE_ADDR 0x30a20000 -#define MX8MM_I2C2_BASE_ADDR 0x30a30000 -#define MX8MM_I2C3_BASE_ADDR 0x30a40000 -#define MX8MM_I2C4_BASE_ADDR 0x30a50000 -#define MX8MM_UART4_BASE_ADDR 0x30a60000 -#define MX8MM_USDHC1_BASE_ADDR 0x30b40000 -#define MX8MM_USDHC2_BASE_ADDR 0x30b50000 -#define MX8MM_USDHC3_BASE_ADDR 0x30b60000 -#define MX8MM_USB1_BASE_ADDR 0x32e40000 -#define MX8MM_USB2_BASE_ADDR 0x32e50000 -#define MX8MM_TZASC_BASE_ADDR 0x32f80000 -#define MX8MM_SRC_IPS_BASE_ADDR 0x30390000 -#define MX8MM_SRC_DDRC_RCR_ADDR 0x30391000 -#define MX8MM_SRC_DDRC2_RCR_ADDR 0x30391004 -#define MX8MM_DDRC_DDR_SS_GPR0 0x3d000000 -#define MX8MM_DDR_CSD1_BASE_ADDR 0x40000000 - -#endif /* __MACH_IMX8MM_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h deleted file mode 100644 index 2f6488af33..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h +++ /dev/null @@ -1,125 +0,0 @@ -#ifndef __MACH_IMX8MQ_REGS_H -#define __MACH_IMX8MQ_REGS_H - -#include <mach/imx8m-regs.h> - -#define MX8MQ_M4_BOOTROM_BASE_ADDR 0x007E0000 - -#define MX8MQ_SAI1_BASE_ADDR 0x30010000 -#define MX8MQ_SAI6_BASE_ADDR 0x30030000 -#define MX8MQ_SAI5_BASE_ADDR 0x30040000 -#define MX8MQ_SAI4_BASE_ADDR 0x30050000 -#define MX8MQ_SPBA2_BASE_ADDR 0x300F0000 -#define MX8MQ_AIPS1_BASE_ADDR 0x301F0000 -#define MX8MQ_GPIO1_BASE_ADDR 0X30200000 -#define MX8MQ_GPIO2_BASE_ADDR 0x30210000 -#define MX8MQ_GPIO3_BASE_ADDR 0x30220000 -#define MX8MQ_GPIO4_BASE_ADDR 0x30230000 -#define MX8MQ_GPIO5_BASE_ADDR 0x30240000 -#define MX8MQ_ANA_TSENSOR_BASE_ADDR 0x30260000 -#define MX8MQ_ANA_OSC_BASE_ADDR 0x30270000 -#define MX8MQ_WDOG1_BASE_ADDR 0x30280000 -#define MX8MQ_WDOG2_BASE_ADDR 0x30290000 -#define MX8MQ_WDOG3_BASE_ADDR 0x302A0000 -#define MX8MQ_SDMA2_BASE_ADDR 0x302C0000 -#define MX8MQ_GPT1_BASE_ADDR 0x302D0000 -#define MX8MQ_GPT2_BASE_ADDR 0x302E0000 -#define MX8MQ_GPT3_BASE_ADDR 0x302F0000 -#define MX8MQ_ROMCP_BASE_ADDR 0x30310000 -#define MX8MQ_LCDIF_BASE_ADDR 0x30320000 -#define MX8MQ_IOMUXC_BASE_ADDR 0x30330000 -#define MX8MQ_IOMUXC_GPR_BASE_ADDR 0x30340000 -#define MX8MQ_OCOTP_BASE_ADDR 0x30350000 -#define MX8MQ_ANATOP_BASE_ADDR 0x30360000 -#define MX8MQ_SNVS_HP_BASE_ADDR 0x30370000 -#define MX8MQ_CCM_BASE_ADDR 0x30380000 -#define MX8MQ_SRC_BASE_ADDR 0x30390000 -#define MX8MQ_GPC_BASE_ADDR 0x303A0000 -#define MX8MQ_SEMAPHORE1_BASE_ADDR 0x303B0000 -#define MX8MQ_SEMAPHORE2_BASE_ADDR 0x303C0000 -#define MX8MQ_RDC_BASE_ADDR 0x303D0000 -#define MX8MQ_CSU_BASE_ADDR 0x303E0000 - -#define MX8MQ_AIPS2_BASE_ADDR 0x305F0000 -#define MX8MQ_PWM1_BASE_ADDR 0x30660000 -#define MX8MQ_PWM2_BASE_ADDR 0x30670000 -#define MX8MQ_PWM3_BASE_ADDR 0x30680000 -#define MX8MQ_PWM4_BASE_ADDR 0x30690000 -#define MX8MQ_SYSCNT_RD_BASE_ADDR 0x306A0000 -#define MX8MQ_SYSCNT_CMP_BASE_ADDR 0x306B0000 -#define MX8MQ_SYSCNT_CTRL_BASE_ADDR 0x306C0000 -#define MX8MQ_GPT6_BASE_ADDR 0x306E0000 -#define MX8MQ_GPT5_BASE_ADDR 0x306F0000 -#define MX8MQ_GPT4_BASE_ADDR 0x30700000 -#define MX8MQ_PERFMON1_BASE_ADDR 0x307C0000 -#define MX8MQ_PERFMON2_BASE_ADDR 0x307D0000 -#define MX8MQ_QOSC_BASE_ADDR 0x307F0000 - -#define MX8MQ_SPDIF1_BASE_ADDR 0x30810000 -#define MX8MQ_ECSPI1_BASE_ADDR 0x30820000 -#define MX8MQ_ECSPI2_BASE_ADDR 0x30830000 -#define MX8MQ_ECSPI3_BASE_ADDR 0x30840000 -#define MX8MQ_UART1_BASE_ADDR 0x30860000 -#define MX8MQ_UART3_BASE_ADDR 0x30880000 -#define MX8MQ_UART2_BASE_ADDR 0x30890000 -#define MX8MQ_SPDIF2_BASE_ADDR 0x308A0000 -#define MX8MQ_SAI2_BASE_ADDR 0x308B0000 -#define MX8MQ_SAI3_BASE_ADDR 0x308C0000 -#define MX8MQ_SPBA1_BASE_ADDR 0x308F0000 -#define MX8MQ_CAAM_BASE_ADDR 0x30900000 -#define MX8MQ_AIPS3_BASE_ADDR 0x309F0000 -#define MX8MQ_MIPI_PHY_BASE_ADDR 0x30A00000 -#define MX8MQ_MIPI_DSI_BASE_ADDR 0x30A10000 -#define MX8MQ_I2C1_BASE_ADDR 0x30A20000 -#define MX8MQ_I2C2_BASE_ADDR 0x30A30000 -#define MX8MQ_I2C3_BASE_ADDR 0x30A40000 -#define MX8MQ_I2C4_BASE_ADDR 0x30A50000 -#define MX8MQ_UART4_BASE_ADDR 0x30A60000 -#define MX8MQ_MIPI_CSI_BASE_ADDR 0x30A70000 -#define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 -#define MX8MQ_CSI1_BASE_ADDR 0x30A90000 -#define MX8MQ_MU_A_BASE_ADDR 0x30AA0000 -#define MX8MQ_MU_B_BASE_ADDR 0x30AB0000 -#define MX8MQ_SEMAPHOR_HS_BASE_ADDR 0x30AC0000 -#define MX8MQ_USDHC1_BASE_ADDR 0x30B40000 -#define MX8MQ_USDHC2_BASE_ADDR 0x30B50000 -#define MX8MQ_MIPI_CS2_BASE_ADDR 0x30B60000 -#define MX8MQ_MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 -#define MX8MQ_CSI2_BASE_ADDR 0x30B80000 -#define MX8MQ_QSPI0_BASE_ADDR 0x30BB0000 -#define MX8MQ_QSPI0_AMBA_BASE 0x08000000 -#define MX8MQ_SDMA1_BASE_ADDR 0x30BD0000 -#define MX8MQ_ENET1_BASE_ADDR 0x30BE0000 - -#define MX8MQ_HDMI_CTRL_BASE_ADDR 0x32C00000 -#define MX8MQ_AIPS4_BASE_ADDR 0x32DF0000 -#define MX8MQ_DC1_BASE_ADDR 0x32E00000 -#define MX8MQ_DC2_BASE_ADDR 0x32E10000 -#define MX8MQ_DC3_BASE_ADDR 0x32E20000 -#define MX8MQ_HDMI_SEC_BASE_ADDR 0x32E40000 -#define MX8MQ_TZASC_BASE_ADDR 0x32F80000 -#define MX8MQ_MTR_BASE_ADDR 0x32FB0000 -#define MX8MQ_PLATFORM_CTRL_BASE_ADDR 0x32FE0000 - -#define MX8MQ_MXS_APBH_BASE 0x33000000 -#define MX8MQ_MXS_GPMI_BASE 0x33002000 -#define MX8MQ_MXS_BCH_BASE 0x33004000 - -#define MX8MQ_USB1_BASE_ADDR 0x38100000 -#define MX8MQ_USB2_BASE_ADDR 0x38200000 -#define MX8MQ_USB1_PHY_BASE_ADDR 0x381F0000 -#define MX8MQ_USB2_PHY_BASE_ADDR 0x382F0000 - -#define MX8MQ_MXS_LCDIF_BASE LCDIF_BASE_ADDR - -#define MX8MQ_SRC_IPS_BASE_ADDR 0x30390000 -#define MX8MQ_SRC_DDRC_RCR_ADDR 0x30391000 -#define MX8MQ_SRC_DDRC2_RCR_ADDR 0x30391004 - -#define MX8MQ_DDRC_PHY_BASE_ADDR 0x3c000000 -#define MX8MQ_DDRC_DDR_SS_GPR0 (MX8MQ_DDRC_PHY_BASE_ADDR + 0x01000000) -#define MX8MQ_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) -#define MX8MQ_DDRC_CTL_BASE_ADDR MX8MQ_DDRC_IPS_BASE_ADDR(0) -#define MX8MQ_DDR_CSD1_BASE_ADDR 0x40000000 - -#endif /* __MACH_IMX8MQ_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h deleted file mode 100644 index 2ef2987188..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8mq.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __MACH_IMX8MQ_H -#define __MACH_IMX8MQ_H - -#include <io.h> -#include <mach/generic.h> -#include <mach/imx8mq-regs.h> -#include <mach/imx8mm-regs.h> -#include <mach/revision.h> -#include <linux/bitfield.h> - -#define IMX8MQ_ROM_VERSION_A0 0x800 -#define IMX8MQ_ROM_VERSION_B0 0x83C -#define IMX8MQ_OCOTP_VERSION_B1 0x40 -#define IMX8MQ_OCOTP_VERSION_B1_MAGIC 0xff0055aa - -#define MX8MQ_ANATOP_DIGPROG 0x6c -#define MX8MM_ANATOP_DIGPROG 0x800 - -#define DIGPROG_MAJOR GENMASK(23, 8) -#define DIGPROG_MINOR GENMASK(7, 0) - -#define IMX8M_CPUTYPE_IMX8MQ 0x8240 -#define IMX8M_CPUTYPE_IMX8MM 0x8241 - -static inline int imx8mm_cpu_revision(void) -{ - void __iomem *anatop = IOMEM(MX8MM_ANATOP_BASE_ADDR); - uint32_t revision = FIELD_GET(DIGPROG_MINOR, - readl(anatop + MX8MM_ANATOP_DIGPROG)); - return revision; -} - -static inline int imx8mq_cpu_revision(void) -{ - void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); - void __iomem *ocotp = IOMEM(MX8MQ_OCOTP_BASE_ADDR); - uint32_t revision = FIELD_GET(DIGPROG_MINOR, - readl(anatop + MX8MQ_ANATOP_DIGPROG)); - uint32_t rom_version; - - if (revision != IMX_CHIP_REV_1_0) - return revision; - /* - * For B1 chip we need to check OCOTP - */ - if (readl(ocotp + IMX8MQ_OCOTP_VERSION_B1) == - IMX8MQ_OCOTP_VERSION_B1_MAGIC) - return IMX_CHIP_REV_2_1; - /* - * For B0 chip, the DIGPROG is not updated, still TO1.0. - * we have to check ROM version further - */ - rom_version = readb(IOMEM(IMX8MQ_ROM_VERSION_A0)); - if (rom_version != IMX_CHIP_REV_1_0) { - rom_version = readb(IOMEM(IMX8MQ_ROM_VERSION_B0)); - if (rom_version >= IMX_CHIP_REV_2_0) - revision = IMX_CHIP_REV_2_0; - } - - return revision; -} - -u64 imx8m_uid(void); - -#endif /* __MACH_IMX8_H */
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h deleted file mode 100644 index b3fccfadb5..0000000000 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __MACH_IMX_CPU_TYPES_H -#define __MACH_IMX_CPU_TYPES_H - -#define IMX_CPU_IMX1 1 -#define IMX_CPU_IMX21 21 -#define IMX_CPU_IMX25 25 -#define IMX_CPU_IMX27 27 -#define IMX_CPU_IMX31 31 -#define IMX_CPU_IMX35 35 -#define IMX_CPU_IMX50 50 -#define IMX_CPU_IMX51 51 -#define IMX_CPU_IMX53 53 -#define IMX_CPU_IMX6 6 -#define IMX_CPU_IMX7 7 -#define IMX_CPU_IMX8MQ 8 -#define IMX_CPU_IMX8MM 81 -#define IMX_CPU_VF610 610 - -#endif /* __MACH_IMX_CPU_TYPES_H */ diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h deleted file mode 100644 index 6df7a14dde..0000000000 --- a/arch/arm/mach-imx/include/mach/imxfb.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __MACH_IMXFB_H -#define __MACH_IMXFB_H - -/* - * This structure describes the machine which we are running on. - */ - -#include <fb.h> - -#define PCR_TFT (1 << 31) -#define PCR_COLOR (1 << 30) -#define PCR_PBSIZ_1 (0 << 28) -#define PCR_PBSIZ_2 (1 << 28) -#define PCR_PBSIZ_4 (2 << 28) -#define PCR_PBSIZ_8 (3 << 28) -#define PCR_BPIX_1 (0 << 25) -#define PCR_BPIX_2 (1 << 25) -#define PCR_BPIX_4 (2 << 25) -#define PCR_BPIX_8 (3 << 25) -#define PCR_BPIX_12 (4 << 25) -#define PCR_BPIX_16 (5 << 25) -#define PCR_BPIX_18 (6 << 25) -#define PCR_PIXPOL (1 << 24) -#define PCR_FLMPOL (1 << 23) -#define PCR_LPPOL (1 << 22) -#define PCR_CLKPOL (1 << 21) -#define PCR_OEPOL (1 << 20) -#define PCR_SCLKIDLE (1 << 19) -#define PCR_END_SEL (1 << 18) -#define PCR_END_BYTE_SWAP (1 << 17) -#define PCR_REV_VS (1 << 16) -#define PCR_ACD_SEL (1 << 15) -#define PCR_ACD(x) (((x) & 0x7f) << 8) -#define PCR_SCLK_SEL (1 << 7) -#define PCR_SHARP (1 << 6) -#define PCR_PCD(x) ((x) & 0x3f) - -#define PWMR_CLS(x) (((x) & 0x1ff) << 16) -#define PWMR_LDMSK (1 << 15) -#define PWMR_SCR1 (1 << 10) -#define PWMR_SCR0 (1 << 9) -#define PWMR_CC_EN (1 << 8) -#define PWMR_PW(x) ((x) & 0xff) - -#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) -#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) -#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) -#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY1(x) (((x) & 0xf)) - -#define DMACR_BURST (1 << 31) -#define DMACR_HM(x) (((x) & 0xf) << 16) -#define DMACR_TM(x) ((x) & 0xf) - -/** - * Define relevant framebuffer information - */ -struct imx_fb_platform_data { - struct fb_videomode *mode; - u_int num_modes; - - u_int cmap_greyscale:1, - cmap_inverse:1, - cmap_static:1, - unused:29; - - u_int pwmr; - u_int lscr1; - u_int dmacr; - u32 pcr; - unsigned char bpp; - - /** force a memory area to be used, else NULL for dynamic allocation */ - void *framebuffer; - /** force a memory area to be used, else NULL for dynamic allocation */ - void *framebuffer_ovl; - /** hook to enable backlight and stuff */ - void (*enable)(int enable); -}; - -void set_imx_fb_info(struct imx_fb_platform_data *); - -#endif /* __MACH_IMXFB_H */ - -/** - * @file - * @brief i.MX related framebuffer declarations - */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx1.h b/arch/arm/mach-imx/include/mach/iomux-mx1.h deleted file mode 100644 index 51317d35d5..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx1.h +++ /dev/null @@ -1,135 +0,0 @@ -#ifndef __MACH_IOMUX_MX1_H -#define __MACH_IOMUX_MX1_H - -#include <mach/iomux-v1.h> - -/* - * FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) -#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) - -#endif /* __MACH_IOMUX_MX1_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h deleted file mode 100644 index 203190d1d7..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx21.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __MACH_IOMUX_MX21_H__ -#define __MACH_IOMUX_MX21_H__ - -#include <mach/iomux-v1.h> -#include <mach/iomux-mx2x.h> - -/* Primary GPIO pin functions */ - -#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) -#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) -#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) -#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) -#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) -#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) -#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) -#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) -#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) -#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) -#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) -#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) -#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) -#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) - -/* Alternate GPIO pin functions */ - -#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) -#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) -#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) -#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) -#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) -#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) -#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) -#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) -#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) -#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) -#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) -#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) -#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) -#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) -#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) -#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) -#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) -#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) -#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) -#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) -#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) -#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) -#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) -#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) -#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) -#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) -#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) -#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) -#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) - -/* CIN GPIO pin functions */ - -#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) - -/* AOUT GPIO pin functions */ - -#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) -#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) -#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) -#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) -#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) -#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) -#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) -#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) -#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) -#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) -#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) -#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) -#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) -#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) -#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) - -#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h deleted file mode 100644 index 58761b5e77..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx25.h +++ /dev/null @@ -1,529 +0,0 @@ -/* - * arch/arm/plat-mxc/include/mach/iomux-mx25.h - * - * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de> - * - * based on arch/arm/mach-mx25/mx25_pins.h - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and - * arch/arm/plat-mxc/include/mach/iomux-mx35.h - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_IOMUX_MX25_H__ -#define __MACH_IOMUX_MX25_H__ - -#include <mach/iomux-v3.h> - -/* - * IOMUX/PAD Bit field definitions - */ - -#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL) - -#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL) - -#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL) - -#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL) - -#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL) - -#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE) -#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE) - -#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__USBH2_CLK IOMUX_PAD(0x2c0, 0xc8, 0x06, 0, 0, 0xe0) - -#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__USBH2_DIR IOMUX_PAD(0x2c4, 0x0cc, 0x06, 0, 0, 0xe0) - -#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__USBH2_STP IOMUX_PAD(0x2c8, 0x0d0, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__USBH2_NXT IOMUX_PAD(0x2cc, 0x0d4, 0x06, 0, 0, 0xe0) - -#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__USBH2_DATA0 IOMUX_PAD(0x2d0, 0x0d8, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__USBH2_DATA1 IOMUX_PAD(0x2d4, 0x0dc, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__USBH2_DATA2 IOMUX_PAD(0x2d8, 0x0e0, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__USBH2_DATA3 IOMUX_PAD(0x2dc, 0x0e4, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL) - -#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__USBH2_DATA4 IOMUX_PAD(0x300, 0x108, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__USBH2_DATA5 IOMUX_PAD(0x304, 0x10c, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__USBH2_DATA6 IOMUX_PAD(0x308, 0x110, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__USBH2_DATA7 IOMUX_PAD(0x30c, 0x114, 0x06, 0, 0, 0xe5) - -#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL) - -#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE) -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN) -#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL) - -#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE) -#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP) -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN) -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) -#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE) - -#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K) -#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) - -#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) - -#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX25_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h deleted file mode 100644 index b6e334559d..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx27.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef __MACH_IOMUX_MX27_H__ -#define __MACH_IOMUX_MX27_H__ - -#include <mach/iomux-v1.h> -#include <mach/iomux-mx2x.h> - -/* Primary GPIO pin functions */ - -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) -#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) -#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) -#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) -#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) -#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) -#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) -#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) -#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) -#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) -#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) -#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) -#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) -#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) -#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) -#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) -#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) -#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) -#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) -#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) -#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) -#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) -#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) -#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) -#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) -#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) -#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) - -/* Alternate GPIO pin functions */ - -#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) -#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) -#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) -#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) -#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) -#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) -#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) -#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) -#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) -#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) -#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) -#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) -#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) -#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) -#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) -#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) -#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) -#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) -#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) -#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) -#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) -#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) -#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) -#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) -#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) -#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) -#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) -#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) -#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) -#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) -#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) -#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) -#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) -#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) -#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) -#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) -#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) -#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) -#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) -#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) -#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) -#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) -#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) -#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) -#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) -#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) -#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) -#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) -#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) -#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) -#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) -#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) -#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) -#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) - -/* CIN GPIO pin functions */ - -#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) -#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) -#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) -#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) -#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) -#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) -#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) -#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) -#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) -#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) -#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) -#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) -#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) -#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) -#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) -#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) -#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) -/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ - -/* AOUT GPIO pin functions */ - -#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) -#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) - -/* BOUT GPIO pin functions */ - -#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) -#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) -#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) -#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) -#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) -#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) -#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) - -#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx2x.h b/arch/arm/mach-imx/include/mach/iomux-mx2x.h deleted file mode 100644 index 15c2e2b060..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx2x.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef __MACH_IOMUX_MX2x_H__ -#define __MACH_IOMUX_MX2x_H__ - -/* Primary GPIO pin functions */ - -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) -#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) -#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) -#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) -#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) -#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) -#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) -#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) -#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) -#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) -#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) -#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) -#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) -#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) -#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) -#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) -#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) -#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) -#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) -#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) -#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) -#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) -#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) -#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) -#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) -#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) -#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) -#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) -#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) -#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) -#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) -#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) -#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) -#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) -#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) -#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) -#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) -#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) -#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) -#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) - -/* Alternate GPIO pin functions */ - -#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) -#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) -#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) -#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) -#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) -#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) -#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) -#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) -#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) -#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) -#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) -#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) -#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) -#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) -#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) -#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) -#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) -#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) -#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) - -/* AIN GPIO pin functions */ - -#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) -#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) -#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) -#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) -#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) -#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) -#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) -#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) -#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) -#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) -#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) -#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) -#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) -#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) -#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) -#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) -#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) -#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) -#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) -#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) -#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) -#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) -#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) -#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) -#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) -#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) -#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) -#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) -#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) -#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) -#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) -#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) -#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) -#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) - -/* CIN GPIO pin functions */ - -#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) -#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) -#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) -#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) -#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) -#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) -#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) -#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) -#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) -#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) - -/* AOUT GPIO pin functions */ - -#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) -#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) -#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) -#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) -#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) - -#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h deleted file mode 100644 index c814c15912..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx31.h +++ /dev/null @@ -1,694 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef __MACH_IOMUX_MX3_H__ -#define __MACH_IOMUX_MX3_H__ - -#include <linux/types.h> -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* - * setups mutliple pins - * convenient way to call the above function with tables - */ -int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void imx_iomux_set_gpr(enum iomux_gp_func, bool en); - -/* - * This function only configures the iomux hardware. - * It is called by the setup functions and should not be called directly anymore. - * It is here visible for backward compatibility - */ -int imx_iomux_mode(unsigned int pin_mode); - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_GPIONUM_SHIFT 9 -#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) -#define IOMUX_MODE_SHIFT 17 -#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) - -#define IOMUX_PIN(gpionum, padnum) \ - (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ - (padnum & IOMUX_PADNUM_MASK)) - -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) - -#define IOMUX_TO_GPIO(iomux_pin) \ - ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), - MX31_PIN_PWMO = IOMUX_PIN( 9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), -}; - -#define PIN_MAX 327 -#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MX31_PIN_(pin name)__(function) - */ -#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) -#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) -#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) -#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) -#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) - - -/* - * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, - * cspi2_ss1, cspi1_ss0 cspi1_ss1 - */ - -/* - * This function configures the pad value for a IOMUX pin. - */ -void imx_iomux_set_pad(enum iomux_pins, u32); - -#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h deleted file mode 100644 index 30b94e3b00..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx35.h +++ /dev/null @@ -1,1264 +0,0 @@ -/* - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option, NO_PAD_CTRL) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_IOMUX_MX35_H__ -#define __MACH_IOMUX_MX35_H__ - -#include <mach/iomux-v3.h> - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) - -#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) - -#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) -#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) - -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) - -#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) - -#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) -#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) - -#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) -#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) -#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) -#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) -#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) -#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) -#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0x10, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) - -#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) - -#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - - -#endif /* __MACH_IOMUX_MX35_H__ */ - diff --git a/arch/arm/mach-imx/include/mach/iomux-mx50.h b/arch/arm/mach-imx/include/mach/iomux-mx50.h deleted file mode 100644 index c21bb3ea9b..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx50.h +++ /dev/null @@ -1,943 +0,0 @@ -/* - * Copyright 2013 Greg Ungerer <gerg@uclinux.org> - * Copyright 2016 Alexander Kurz <akurz@blala.de> - * based on linux imx50-pinfunc.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc.. - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_IOMUX_MX50_H__ -#define __MACH_IOMUX_MX50_H__ - -#include <mach/iomux-v3.h> - -/* These 2 defines are for pins that may not have a mux register, but could - * have a pad setting register, and vice-versa. */ -#define __NA_ 0x00 - -#define MX50_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) -#define MX50_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) -#define MX50_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_ODE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) -#define MX50_SPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x2CC, 0x020, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__GPIO4_0 IOMUX_PAD(0x2CC, 0x020, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE IOMUX_PAD(0x2CC, 0x020, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 IOMUX_PAD(0x2CC, 0x020, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY IOMUX_PAD(0x2CC, 0x020, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x2D0, 0x024, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__GPIO4_1 IOMUX_PAD(0x2D0, 0x024, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE IOMUX_PAD(0x2D0, 0x024, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 IOMUX_PAD(0x2D0, 0x024, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID IOMUX_PAD(0x2D0, 0x024, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x2D4, 0x028, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__GPIO4_2 IOMUX_PAD(0x2D4, 0x028, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 IOMUX_PAD(0x2D4, 0x028, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 IOMUX_PAD(0x2D4, 0x028, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE IOMUX_PAD(0x2D4, 0x028, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x2D8, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__GPIO4_3 IOMUX_PAD(0x2D8, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 IOMUX_PAD(0x2D8, 0x02C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 IOMUX_PAD(0x2D8, 0x02C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR IOMUX_PAD(0x2D8, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__KPP_COL_1 IOMUX_PAD(0x2DC, 0x030, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__GPIO4_4 IOMUX_PAD(0x2DC, 0x030, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 IOMUX_PAD(0x2DC, 0x030, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 IOMUX_PAD(0x2DC, 0x030, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK IOMUX_PAD(0x2DC, 0x030, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x2E0, 0x034, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__GPIO4_5 IOMUX_PAD(0x2E0, 0x034, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 IOMUX_PAD(0x2E0, 0x034, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 IOMUX_PAD(0x2E0, 0x034, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 IOMUX_PAD(0x2E0, 0x034, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__KPP_COL_2 IOMUX_PAD(0x2E4, 0x038, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__GPIO4_6 IOMUX_PAD(0x2E4, 0x038, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 IOMUX_PAD(0x2E4, 0x038, 2, 0x7B4, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 IOMUX_PAD(0x2E4, 0x038, 6, 0x7B8, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 IOMUX_PAD(0x2E4, 0x038, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x2E8, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__GPIO4_7 IOMUX_PAD(0x2E8, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS IOMUX_PAD(0x2E8, 0x03C, 2, 0x7B0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 IOMUX_PAD(0x2E8, 0x03C, 6, 0x7BC, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID IOMUX_PAD(0x2E8, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x040, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__GPIO6_18 IOMUX_PAD(0x2EC, 0x040, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX IOMUX_PAD(0x2EC, 0x040, 2, 0x7CC, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x044, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__GPIO6_19 IOMUX_PAD(0x2F0, 0x044, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX IOMUX_PAD(0x2F0, 0x044, 2, 0x7CC, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x048, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__GPIO6_20 IOMUX_PAD(0x2F4, 0x048, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x048, 2, __NA_, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x04C, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__GPIO6_21 IOMUX_PAD(0x2F8, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x04C, 2, 0x7C8, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x050, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPIO6_22 IOMUX_PAD(0x2FC, 0x050, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x050, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY IOMUX_PAD(0x2FC, 0x050, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x050, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x2FC, 0x050, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC IOMUX_PAD(0x2FC, 0x050, 7, 0x7E8, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x054, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPIO6_23 IOMUX_PAD(0x300, 0x054, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x054, 2, 0x774, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT IOMUX_PAD(0x300, 0x054, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB IOMUX_PAD(0x300, 0x054, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 IOMUX_PAD(0x300, 0x054, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x300, 0x054, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR IOMUX_PAD(0x300, 0x054, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x058, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__GPIO6_24 IOMUX_PAD(0x304, 0x058, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__USBOH1_USBOTG_OC IOMUX_PAD(0x304, 0x058, 2, 0x7E8, 1, NO_PAD_CTRL) -#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x058, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x304, 0x058, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__SJC_FAIL IOMUX_PAD(0x304, 0x058, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPIO6_25 IOMUX_PAD(0x308, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR IOMUX_PAD(0x308, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x308, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__SRC_ANY_PU_RST IOMUX_PAD(0x308, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__OWIRE_LINE IOMUX_PAD(0x30C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__GPIO6_26 IOMUX_PAD(0x30C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__USBOH1_USBH1_OC IOMUX_PAD(0x30C, 0x060, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x060, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x30C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__SJC_JTAG_ACT IOMUX_PAD(0x30C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__EPIT1_EPITO IOMUX_PAD(0x310, 0x064, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPIO6_27 IOMUX_PAD(0x310, 0x064, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__USBOH1_USBH1_PWR IOMUX_PAD(0x310, 0x064, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK IOMUX_PAD(0x310, 0x064, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__DPLLIP1_TOG_EN IOMUX_PAD(0x310, 0x064, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPT_CLK_IN IOMUX_PAD(0x310, 0x064, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__PMU_IRQ_B IOMUX_PAD(0x310, 0x064, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__SJC_DE_B IOMUX_PAD(0x310, 0x064, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__WDOG1_WDOG_B IOMUX_PAD(0x314, 0x068, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__GPIO6_28 IOMUX_PAD(0x314, 0x068, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x314, 0x068, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__CCM_XTAL32K IOMUX_PAD(0x314, 0x068, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__SJC_DONE IOMUX_PAD(0x314, 0x068, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS IOMUX_PAD(0x318, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__GPIO6_0 IOMUX_PAD(0x318, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 IOMUX_PAD(0x318, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 IOMUX_PAD(0x318, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC IOMUX_PAD(0x31C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__GPIO6_1 IOMUX_PAD(0x31C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 IOMUX_PAD(0x31C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 IOMUX_PAD(0x31C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD IOMUX_PAD(0x320, 0x074, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__GPIO6_2 IOMUX_PAD(0x320, 0x074, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x074, 4, 0x6E8, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 IOMUX_PAD(0x320, 0x074, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD IOMUX_PAD(0x324, 0x078, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__GPIO6_3 IOMUX_PAD(0x324, 0x078, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x078, 4, 0x6F4, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 IOMUX_PAD(0x324, 0x078, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS IOMUX_PAD(0x328, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__GPIO6_4 IOMUX_PAD(0x328, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX IOMUX_PAD(0x328, 0x07C, 2, 0x7E4, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 IOMUX_PAD(0x328, 0x07C, 3, 0x804, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x07C, 4, 0x6F0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x07C, 5, 0x770, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 IOMUX_PAD(0x328, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC IOMUX_PAD(0x32C, 0x080, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__GPIO6_5 IOMUX_PAD(0x32C, 0x080, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__UART5_RXD_MUX IOMUX_PAD(0x32C, 0x080, 2, 0x7E4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 IOMUX_PAD(0x32C, 0x080, 3, 0x808, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x080, 4, 0x6EC, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x080, 5, 0x780, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x080, 6, 0x774, 1, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 IOMUX_PAD(0x32C, 0x080, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_TXD__UART1_TXD_MUX IOMUX_PAD(0x330, 0x084, 0, 0x7C4, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_TXD__GPIO6_6 IOMUX_PAD(0x330, 0x084, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 IOMUX_PAD(0x330, 0x084, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RXD__UART1_RXD_MUX IOMUX_PAD(0x334, 0x088, 0, 0x7C4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RXD__GPIO6_7 IOMUX_PAD(0x334, 0x088, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 IOMUX_PAD(0x334, 0x088, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x08C, 0, __NA_, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__GPIO6_8 IOMUX_PAD(0x338, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART5_TXD_MUX IOMUX_PAD(0x338, 0x08C, 2, 0x7E4, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 IOMUX_PAD(0x338, 0x08C, 4, 0x760, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART1_CTS__ESDHC4_CMD IOMUX_PAD(0x338, 0x08C, 5, 0x74C, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 IOMUX_PAD(0x338, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x090, 0, 0x7C0, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__GPIO6_9 IOMUX_PAD(0x33C, 0x090, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RTS__UART5_RXD_MUX IOMUX_PAD(0x33C, 0x090, 2, 0x7E4, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 IOMUX_PAD(0x33C, 0x090, 4, 0x764, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART1_RTS__ESDHC4_CLK IOMUX_PAD(0x33C, 0x090, 5, 0x748, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 IOMUX_PAD(0x33C, 0x090, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_TXD__UART2_TXD_MUX IOMUX_PAD(0x340, 0x094, 0, 0x7CC, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_TXD__GPIO6_10 IOMUX_PAD(0x340, 0x094, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 IOMUX_PAD(0x340, 0x094, 4, 0x768, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 IOMUX_PAD(0x340, 0x094, 5, 0x760, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 IOMUX_PAD(0x340, 0x094, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RXD__UART2_RXD_MUX IOMUX_PAD(0x344, 0x098, 0, 0x7CC, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RXD__GPIO6_11 IOMUX_PAD(0x344, 0x098, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 IOMUX_PAD(0x344, 0x098, 4, 0x76C, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 IOMUX_PAD(0x344, 0x098, 5, 0x764, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 IOMUX_PAD(0x344, 0x098, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x09C, 0, __NA_, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_CTS__GPIO6_12 IOMUX_PAD(0x348, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_CTS__ESDHC4_CMD IOMUX_PAD(0x348, 0x09C, 4, 0x74C, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 IOMUX_PAD(0x348, 0x09C, 5, 0x768, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 IOMUX_PAD(0x348, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0x0A0, 0, 0x7C8, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RTS__GPIO6_13 IOMUX_PAD(0x34C, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RTS__ESDHC4_CLK IOMUX_PAD(0x34C, 0x0A0, 4, 0x748, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 IOMUX_PAD(0x34C, 0x0A0, 5, 0x76C, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 IOMUX_PAD(0x34C, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_TXD__UART3_TXD_MUX IOMUX_PAD(0x350, 0x0A4, 0, 0x7D4, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_TXD__GPIO6_14 IOMUX_PAD(0x350, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 IOMUX_PAD(0x350, 0x0A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 IOMUX_PAD(0x350, 0x0A4, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_TXD__ESDHC2_WP IOMUX_PAD(0x350, 0x0A4, 5, 0x744, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 IOMUX_PAD(0x350, 0x0A4, 6, 0x81C, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 IOMUX_PAD(0x350, 0x0A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_RXD__UART3_RXD_MUX IOMUX_PAD(0x354, 0x0A8, 0, 0x7D4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_RXD__GPIO6_15 IOMUX_PAD(0x354, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 IOMUX_PAD(0x354, 0x0A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 IOMUX_PAD(0x354, 0x0A8, 4, 0x754, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_RXD__ESDHC2_CD IOMUX_PAD(0x354, 0x0A8, 5, 0x740, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 IOMUX_PAD(0x354, 0x0A8, 6, 0x820, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 IOMUX_PAD(0x354, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART4_TXD_MUX IOMUX_PAD(0x358, 0x0AC, 0, 0x7DC, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__GPIO6_16 IOMUX_PAD(0x358, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0x0AC, 2, 0x7D0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 IOMUX_PAD(0x358, 0x0AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 IOMUX_PAD(0x358, 0x0AC, 4, 0x758, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_TXD__ESDHC2_LCTL IOMUX_PAD(0x358, 0x0AC, 5, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 IOMUX_PAD(0x358, 0x0AC, 6, 0x824, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_RXD__UART4_RXD_MUX IOMUX_PAD(0x35C, 0x0B0, 0, 0x7DC, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__GPIO6_17 IOMUX_PAD(0x35C, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0x0B0, 2, 0x7D0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 IOMUX_PAD(0x35C, 0x0B0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 IOMUX_PAD(0x35C, 0x0B0, 4, 0x75C, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_RXD__ESDHC1_LCTL IOMUX_PAD(0x35C, 0x0B0, 5, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 IOMUX_PAD(0x35C, 0x0B0, 6, 0x828, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0x0B4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_CSPI_SCLK__GPIO4_8 IOMUX_PAD(0x360, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0x0B8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_CSPI_MOSI__GPIO4_9 IOMUX_PAD(0x364, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0x0BC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_CSPI_MISO__GPIO4_10 IOMUX_PAD(0x368, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_SS0__GPIO4_11 IOMUX_PAD(0x36C, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0x0C4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 IOMUX_PAD(0x370, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0x0C4, 2, 0x6E8, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0x0C4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0x0C4, 4, 0x7D0, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 IOMUX_PAD(0x370, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 IOMUX_PAD(0x370, 0x0C4, 7, 0x80C, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0x0C8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 IOMUX_PAD(0x374, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0x0C8, 2, 0x6EC, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0x0C8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0x0C8, 4, __NA_, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 IOMUX_PAD(0x374, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 IOMUX_PAD(0x374, 0x0C8, 7, 0x810, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0x0CC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__GPIO4_14 IOMUX_PAD(0x378, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0x0CC, 2, 0x6F0, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0x0CC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0x0CC, 4, 0x7D8, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 IOMUX_PAD(0x378, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 IOMUX_PAD(0x378, 0x0CC, 7, 0x814, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__GPIO4_15 IOMUX_PAD(0x37C, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0x0D0, 2, 0x6F4, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0x0D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0x0D0, 4, __NA_, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 IOMUX_PAD(0x37C, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 IOMUX_PAD(0x37C, 0x0D0, 7, 0x818, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0x0D4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 IOMUX_PAD(0x380, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN IOMUX_PAD(0x380, 0x0D4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0x0D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0x0D4, 4, 0x7E0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 IOMUX_PAD(0x380, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 IOMUX_PAD(0x380, 0x0D4, 7, 0x80C, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0x0D8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 IOMUX_PAD(0x384, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E IOMUX_PAD(0x384, 0x0D8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0x0D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0x0D8, 4, 0x7E0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE IOMUX_PAD(0x384, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 IOMUX_PAD(0x384, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 IOMUX_PAD(0x384, 0x0D8, 7, 0x810, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0x0DC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__GPIO4_18 IOMUX_PAD(0x388, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0x0DC, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0x0DC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX IOMUX_PAD(0x388, 0x0DC, 4, 0x7E4, 4, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0x0DC, 5, 0x73C, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 IOMUX_PAD(0x388, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 IOMUX_PAD(0x388, 0x0DC, 7, 0x814, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__GPIO4_19 IOMUX_PAD(0x38C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0x0E0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 IOMUX_PAD(0x38C, 0x0E0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX IOMUX_PAD(0x38C, 0x0E0, 4, 0x7E4, 5, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0x0E0, 5, 0x6F8, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 IOMUX_PAD(0x38C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 IOMUX_PAD(0x38C, 0x0E0, 7, 0x818, 1, NO_PAD_CTRL) -#define MX50_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x390, 0x0E4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_CLK__GPIO5_0 IOMUX_PAD(0x390, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CLK__CCM_CLKO IOMUX_PAD(0x390, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x394, 0x0E8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_CMD__GPIO5_1 IOMUX_PAD(0x394, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CMD__CCM_CLKO2 IOMUX_PAD(0x394, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D0__ESDHC1_DAT0 IOMUX_PAD(0x398, 0x0EC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_D0__GPIO5_2 IOMUX_PAD(0x398, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D0__CCM_PLL1_BYP IOMUX_PAD(0x398, 0x0EC, 7, 0x6DC, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D1__ESDHC1_DAT1 IOMUX_PAD(0x39C, 0x0F0, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_D1__GPIO5_3 IOMUX_PAD(0x39C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D1__CCM_PLL2_BYP IOMUX_PAD(0x39C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D2__ESDHC1_DAT2 IOMUX_PAD(0x3A0, 0x0F4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_D2__GPIO5_4 IOMUX_PAD(0x3A0, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D2__CCM_PLL3_BYP IOMUX_PAD(0x3A0, 0x0F4, 7, 0x6E4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D3__ESDHC1_DAT3 IOMUX_PAD(0x3A4, 0x0F8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD1_D3__GPIO5_5 IOMUX_PAD(0x3A4, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x3A8, 0x0FC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_CLK__GPIO5_6 IOMUX_PAD(0x3A8, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0x0FC, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x3AC, 0x100, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_CMD__GPIO5_7 IOMUX_PAD(0x3AC, 0x100, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D0__ESDHC2_DAT0 IOMUX_PAD(0x3B0, 0x104, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D0__GPIO5_8 IOMUX_PAD(0x3B0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D0__MSHC_DATA_0 IOMUX_PAD(0x3B0, 0x104, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D0__KPP_COL_4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D1__ESDHC2_DAT1 IOMUX_PAD(0x3B4, 0x108, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D1__GPIO5_9 IOMUX_PAD(0x3B4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D1__MSHC_DATA_1 IOMUX_PAD(0x3B4, 0x108, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D1__KPP_ROW_4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7A0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D2__ESDHC2_DAT2 IOMUX_PAD(0x3B8, 0x10C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D2__GPIO5_10 IOMUX_PAD(0x3B8, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D2__MSHC_DATA_2 IOMUX_PAD(0x3B8, 0x10C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D2__KPP_COL_5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D3__ESDHC2_DAT3 IOMUX_PAD(0x3BC, 0x110, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D3__GPIO5_11 IOMUX_PAD(0x3BC, 0x110, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D3__MSHC_DATA_3 IOMUX_PAD(0x3BC, 0x110, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D3__KPP_ROW_5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7A4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__ESDHC2_DAT4 IOMUX_PAD(0x3C0, 0x114, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D4__GPIO5_12 IOMUX_PAD(0x3C0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6D0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__KPP_COL_6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7EC, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 IOMUX_PAD(0x3C0, 0x114, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__ESDHC2_DAT5 IOMUX_PAD(0x3C4, 0x118, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D5__GPIO5_13 IOMUX_PAD(0x3C4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6CC, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__KPP_ROW_6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7A8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7F0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 IOMUX_PAD(0x3C4, 0x118, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__ESDHC2_DAT6 IOMUX_PAD(0x3C8, 0x11C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D6__GPIO5_14 IOMUX_PAD(0x3C8, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6C4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__KPP_COL_7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79C, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7F4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 IOMUX_PAD(0x3C8, 0x11C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__ESDHC2_DAT7 IOMUX_PAD(0x3CC, 0x120, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_D7__GPIO5_15 IOMUX_PAD(0x3CC, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6D8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__KPP_ROW_7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7AC, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7F8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__ESDHC2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_WP__GPIO5_16 IOMUX_PAD(0x3D0, 0x124, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6C8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7FC, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__ESDHC2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD2_CD__GPIO5_17 IOMUX_PAD(0x3D4, 0x128, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6D4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__CCM_REF_EN_B IOMUX_PAD(0x3D4, 0x128, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6FC, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__GPIO2_0 IOMUX_PAD(0x40C, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__FEC_TX_CLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78C, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 IOMUX_PAD(0x40C, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 IOMUX_PAD(0x40C, 0x12C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 IOMUX_PAD(0x40C, 0x12C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__GPIO2_1 IOMUX_PAD(0x410, 0x130, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__FEC_RX_ERR IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 IOMUX_PAD(0x410, 0x130, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 IOMUX_PAD(0x410, 0x130, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 IOMUX_PAD(0x410, 0x130, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__GPIO2_2 IOMUX_PAD(0x414, 0x134, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 IOMUX_PAD(0x414, 0x134, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 IOMUX_PAD(0x414, 0x134, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 IOMUX_PAD(0x414, 0x134, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__GPIO2_3 IOMUX_PAD(0x418, 0x138, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_RDATA_1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 IOMUX_PAD(0x418, 0x138, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 IOMUX_PAD(0x418, 0x138, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 IOMUX_PAD(0x418, 0x138, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70C, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__GPIO2_4 IOMUX_PAD(0x41C, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__FEC_RDATA_0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 IOMUX_PAD(0x41C, 0x13C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 IOMUX_PAD(0x41C, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 IOMUX_PAD(0x41C, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__GPIO2_5 IOMUX_PAD(0x420, 0x140, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 IOMUX_PAD(0x420, 0x140, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 IOMUX_PAD(0x420, 0x140, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 IOMUX_PAD(0x420, 0x140, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__GPIO2_6 IOMUX_PAD(0x424, 0x144, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_TDATA_1 IOMUX_PAD(0x424, 0x144, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 IOMUX_PAD(0x424, 0x144, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 IOMUX_PAD(0x424, 0x144, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 IOMUX_PAD(0x424, 0x144, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__GPIO2_7 IOMUX_PAD(0x428, 0x148, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__FEC_TDATA_0 IOMUX_PAD(0x428, 0x148, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 IOMUX_PAD(0x428, 0x148, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 IOMUX_PAD(0x428, 0x148, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 IOMUX_PAD(0x428, 0x148, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN IOMUX_PAD(0x42C, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__GPIO2_16 IOMUX_PAD(0x42C, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK IOMUX_PAD(0x42C, 0x14C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 IOMUX_PAD(0x42C, 0x14C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 IOMUX_PAD(0x42C, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__USBPHY1_AVALID IOMUX_PAD(0x42C, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__ELCDIF_RD_E IOMUX_PAD(0x430, 0x150, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__GPIO2_19 IOMUX_PAD(0x430, 0x150, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__ELCDIF_ENABLE IOMUX_PAD(0x430, 0x150, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 IOMUX_PAD(0x430, 0x150, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 IOMUX_PAD(0x430, 0x150, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__USBPHY1_BVALID IOMUX_PAD(0x430, 0x150, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__GPIO2_17 IOMUX_PAD(0x434, 0x154, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73C, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 IOMUX_PAD(0x434, 0x154, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 IOMUX_PAD(0x434, 0x154, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION IOMUX_PAD(0x434, 0x154, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__GPIO2_21 IOMUX_PAD(0x438, 0x158, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6F8, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 IOMUX_PAD(0x438, 0x158, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 IOMUX_PAD(0x438, 0x158, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 IOMUX_PAD(0x438, 0x158, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__USBPHY1_IDDIG IOMUX_PAD(0x438, 0x158, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY IOMUX_PAD(0x43C, 0x15C, 0, 0x6F8, 2, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__GPIO2_18 IOMUX_PAD(0x43C, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 IOMUX_PAD(0x43C, 0x15C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 IOMUX_PAD(0x43C, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x43C, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__ELCDIF_RESET IOMUX_PAD(0x440, 0x160, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__GPIO2_20 IOMUX_PAD(0x440, 0x160, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 IOMUX_PAD(0x440, 0x160, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 IOMUX_PAD(0x440, 0x160, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK IOMUX_PAD(0x440, 0x160, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CMD__ESDHC3_CMD IOMUX_PAD(0x444, 0x164, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_CMD__GPIO5_18 IOMUX_PAD(0x444, 0x164, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CLK__ESDHC3_CLK IOMUX_PAD(0x448, 0x168, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_CLK__GPIO5_19 IOMUX_PAD(0x448, 0x168, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__ESDHC3_DAT0 IOMUX_PAD(0x44C, 0x16C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D0__GPIO5_20 IOMUX_PAD(0x44C, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 IOMUX_PAD(0x44C, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__CCM_PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6DC, 1, NO_PAD_CTRL) -#define MX50_PAD_SD3_D1__ESDHC3_DAT1 IOMUX_PAD(0x450, 0x170, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D1__GPIO5_21 IOMUX_PAD(0x450, 0x170, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 IOMUX_PAD(0x450, 0x170, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D1__SSP_D1 IOMUX_PAD(0x450, 0x170, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D1__CCM_PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__ESDHC3_DAT2 IOMUX_PAD(0x454, 0x174, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D2__GPIO5_22 IOMUX_PAD(0x454, 0x174, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 IOMUX_PAD(0x454, 0x174, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__CCM_PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6E4, 1, NO_PAD_CTRL) -#define MX50_PAD_SD3_D3__ESDHC3_DAT3 IOMUX_PAD(0x458, 0x178, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D3__GPIO5_23 IOMUX_PAD(0x458, 0x178, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 IOMUX_PAD(0x458, 0x178, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D4__ESDHC3_DAT4 IOMUX_PAD(0x45C, 0x17C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D4__GPIO5_24 IOMUX_PAD(0x45C, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 IOMUX_PAD(0x45C, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D5__ESDHC3_DAT5 IOMUX_PAD(0x460, 0x180, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D5__GPIO5_25 IOMUX_PAD(0x460, 0x180, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 IOMUX_PAD(0x460, 0x180, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D6__ESDHC3_DAT6 IOMUX_PAD(0x464, 0x184, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D6__GPIO5_26 IOMUX_PAD(0x464, 0x184, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 IOMUX_PAD(0x464, 0x184, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D7__ESDHC3_DAT7 IOMUX_PAD(0x468, 0x188, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_D7__GPIO5_27 IOMUX_PAD(0x468, 0x188, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 IOMUX_PAD(0x468, 0x188, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__ESDHC3_WP IOMUX_PAD(0x46C, 0x18C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_WP__GPIO5_28 IOMUX_PAD(0x46C, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__ESDHC4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 IOMUX_PAD(0x46C, 0x18C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 IOMUX_PAD(0x470, 0x190, 0, 0x71C, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__GPIO2_8 IOMUX_PAD(0x470, 0x190, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__EIM_NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__ESDHC1_LCTL IOMUX_PAD(0x470, 0x190, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D8__ESDHC4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74C, 2, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D8__KPP_COL_4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78C, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 IOMUX_PAD(0x470, 0x190, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__GPIO2_9 IOMUX_PAD(0x474, 0x194, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__EIM_NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__ESDHC2_LCTL IOMUX_PAD(0x474, 0x194, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D9__ESDHC4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D9__KPP_ROW_4 IOMUX_PAD(0x474, 0x194, 5, 0x7A0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 IOMUX_PAD(0x474, 0x194, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__GPIO2_10 IOMUX_PAD(0x478, 0x198, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 IOMUX_PAD(0x478, 0x198, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__ESDHC3_LCTL IOMUX_PAD(0x478, 0x198, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D10__ESDHC4_DAT0 IOMUX_PAD(0x478, 0x198, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D10__KPP_COL_5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 IOMUX_PAD(0x478, 0x198, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__GPIO2_11 IOMUX_PAD(0x47C, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 IOMUX_PAD(0x47C, 0x19C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__ESDHC4_DAT1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D11__KPP_ROW_5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7A4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__FEC_RDATA_1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77C, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 IOMUX_PAD(0x47C, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72C, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__GPIO2_12 IOMUX_PAD(0x480, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 IOMUX_PAD(0x480, 0x1A0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__ESDHC1_CD IOMUX_PAD(0x480, 0x1A0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D12__ESDHC4_DAT2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D12__KPP_COL_6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__FEC_RDATA_0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 IOMUX_PAD(0x480, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__GPIO2_13 IOMUX_PAD(0x484, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 IOMUX_PAD(0x484, 0x1A4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__ESDHC3_CD IOMUX_PAD(0x484, 0x1A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D13__ESDHC4_DAT3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75C, 1, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D13__KPP_ROW_6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7A8, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 IOMUX_PAD(0x484, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__GPIO2_14 IOMUX_PAD(0x488, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7B4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__ESDHC1_WP IOMUX_PAD(0x488, 0x1A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D14__ESDHC4_WP IOMUX_PAD(0x488, 0x1A8, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D14__KPP_COL_7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79C, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__FEC_TDATA_1 IOMUX_PAD(0x488, 0x1A8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 IOMUX_PAD(0x488, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__GPIO2_15 IOMUX_PAD(0x48C, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__EIM_NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7B0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__ESDHC3_RST IOMUX_PAD(0x48C, 0x1AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D15__ESDHC4_CD IOMUX_PAD(0x48C, 0x1AC, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) -#define MX50_PAD_DISP_D15__KPP_ROW_7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7AC, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__FEC_TDATA_0 IOMUX_PAD(0x48C, 0x1AC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 IOMUX_PAD(0x48C, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 IOMUX_PAD(0x54C, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__GPIO3_0 IOMUX_PAD(0x54C, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7EC, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK IOMUX_PAD(0x54C, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x54C, 0x1B0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x54C, 0x1B0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 IOMUX_PAD(0x550, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__GPIO3_1 IOMUX_PAD(0x550, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7F0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE IOMUX_PAD(0x550, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x550, 0x1B4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 IOMUX_PAD(0x550, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 IOMUX_PAD(0x554, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__GPIO3_2 IOMUX_PAD(0x554, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7F4, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN IOMUX_PAD(0x554, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73C, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x554, 0x1B8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 IOMUX_PAD(0x554, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 IOMUX_PAD(0x558, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__GPIO3_3 IOMUX_PAD(0x558, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7F8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_RD_E IOMUX_PAD(0x558, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6F8, 3, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x558, 0x1BC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 IOMUX_PAD(0x558, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 IOMUX_PAD(0x55C, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__GPIO3_4 IOMUX_PAD(0x55C, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7FC, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x55C, 0x1C0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 IOMUX_PAD(0x55C, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 IOMUX_PAD(0x560, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__GPIO3_5 IOMUX_PAD(0x560, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x560, 0x1C4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 IOMUX_PAD(0x560, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 IOMUX_PAD(0x564, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__GPIO3_6 IOMUX_PAD(0x564, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x564, 0x1C8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 IOMUX_PAD(0x564, 0x1C8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 IOMUX_PAD(0x568, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__GPIO3_7 IOMUX_PAD(0x568, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x568, 0x1CC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 IOMUX_PAD(0x568, 0x1CC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 IOMUX_PAD(0x56C, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__GPIO3_8 IOMUX_PAD(0x56C, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80C, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 IOMUX_PAD(0x56C, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x56C, 0x1D0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 IOMUX_PAD(0x56C, 0x1D0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 IOMUX_PAD(0x570, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__GPIO3_9 IOMUX_PAD(0x570, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 IOMUX_PAD(0x570, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x570, 0x1D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 IOMUX_PAD(0x570, 0x1D4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 IOMUX_PAD(0x574, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__GPIO3_10 IOMUX_PAD(0x574, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 IOMUX_PAD(0x574, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x574, 0x1D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 IOMUX_PAD(0x574, 0x1D8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 IOMUX_PAD(0x578, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__GPIO3_11 IOMUX_PAD(0x578, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 IOMUX_PAD(0x578, 0x1DC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x578, 0x1DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 IOMUX_PAD(0x578, 0x1DC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 IOMUX_PAD(0x57C, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__GPIO3_12 IOMUX_PAD(0x57C, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81C, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 IOMUX_PAD(0x57C, 0x1E0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x57C, 0x1E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 IOMUX_PAD(0x57C, 0x1E0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 IOMUX_PAD(0x580, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__GPIO3_13 IOMUX_PAD(0x580, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 IOMUX_PAD(0x580, 0x1E4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x580, 0x1E4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 IOMUX_PAD(0x580, 0x1E4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 IOMUX_PAD(0x584, 0x1E8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__GPIO3_14 IOMUX_PAD(0x584, 0x1E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 IOMUX_PAD(0x584, 0x1E8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x584, 0x1E8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 IOMUX_PAD(0x584, 0x1E8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 IOMUX_PAD(0x588, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__GPIO3_15 IOMUX_PAD(0x588, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 IOMUX_PAD(0x588, 0x1EC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x588, 0x1EC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 IOMUX_PAD(0x588, 0x1EC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__GPIO3_16 IOMUX_PAD(0x58C, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 IOMUX_PAD(0x58C, 0x1F0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 IOMUX_PAD(0x58C, 0x1F0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x58C, 0x1F0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK IOMUX_PAD(0x58C, 0x1F0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__EPCD_GDSP IOMUX_PAD(0x590, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__GPIO3_17 IOMUX_PAD(0x590, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 IOMUX_PAD(0x590, 0x1F4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 IOMUX_PAD(0x590, 0x1F4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x590, 0x1F4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID IOMUX_PAD(0x590, 0x1F4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__EPCD_GDOE IOMUX_PAD(0x594, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__GPIO3_18 IOMUX_PAD(0x594, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 IOMUX_PAD(0x594, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 IOMUX_PAD(0x594, 0x1F8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x594, 0x1F8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION IOMUX_PAD(0x594, 0x1F8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__EPCD_GDRL IOMUX_PAD(0x598, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__GPIO3_19 IOMUX_PAD(0x598, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 IOMUX_PAD(0x598, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 IOMUX_PAD(0x598, 0x1FC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x598, 0x1FC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG IOMUX_PAD(0x598, 0x1FC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK IOMUX_PAD(0x59C, 0x200, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__GPIO3_20 IOMUX_PAD(0x59C, 0x200, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 IOMUX_PAD(0x59C, 0x200, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 IOMUX_PAD(0x59C, 0x200, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x59C, 0x200, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x59C, 0x200, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 IOMUX_PAD(0x5A0, 0x204, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 IOMUX_PAD(0x5A0, 0x204, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 IOMUX_PAD(0x5A0, 0x204, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x5A0, 0x204, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY IOMUX_PAD(0x5A0, 0x204, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__EPCD_SDOED IOMUX_PAD(0x5A4, 0x208, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__GPIO3_22 IOMUX_PAD(0x5A4, 0x208, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 IOMUX_PAD(0x5A4, 0x208, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 IOMUX_PAD(0x5A4, 0x208, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x5A4, 0x208, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID IOMUX_PAD(0x5A4, 0x208, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__EPCD_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__GPIO3_23 IOMUX_PAD(0x5A8, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 IOMUX_PAD(0x5A8, 0x20C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 IOMUX_PAD(0x5A8, 0x20C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5A8, 0x20C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE IOMUX_PAD(0x5A8, 0x20C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__EPCD_SDLE IOMUX_PAD(0x5AC, 0x210, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__GPIO3_24 IOMUX_PAD(0x5AC, 0x210, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 IOMUX_PAD(0x5AC, 0x210, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71C, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5AC, 0x210, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR IOMUX_PAD(0x5AC, 0x210, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 IOMUX_PAD(0x5B0, 0x214, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 IOMUX_PAD(0x5B0, 0x214, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x5B0, 0x214, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK IOMUX_PAD(0x5B0, 0x214, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__GPIO3_26 IOMUX_PAD(0x5B4, 0x218, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 IOMUX_PAD(0x5B4, 0x218, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6C8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x5B4, 0x218, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 IOMUX_PAD(0x5B4, 0x218, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 IOMUX_PAD(0x5B8, 0x21C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 IOMUX_PAD(0x5B8, 0x21C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6D4, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x5B8, 0x21C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 IOMUX_PAD(0x5B8, 0x21C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 IOMUX_PAD(0x5BC, 0x220, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 IOMUX_PAD(0x5BC, 0x220, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72C, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6D8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE IOMUX_PAD(0x5BC, 0x220, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID IOMUX_PAD(0x5BC, 0x220, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 IOMUX_PAD(0x5C0, 0x224, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 IOMUX_PAD(0x5C0, 0x224, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6C4, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x5C0, 0x224, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID IOMUX_PAD(0x5C0, 0x224, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 IOMUX_PAD(0x5C4, 0x228, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 IOMUX_PAD(0x5C4, 0x228, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6CC, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD IOMUX_PAD(0x5C4, 0x228, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST IOMUX_PAD(0x5C4, 0x228, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 IOMUX_PAD(0x5C8, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 IOMUX_PAD(0x5C8, 0x22C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6D0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7B8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST IOMUX_PAD(0x5C8, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 IOMUX_PAD(0x5CC, 0x230, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 IOMUX_PAD(0x5CC, 0x230, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7BC, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK IOMUX_PAD(0x5CC, 0x230, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 IOMUX_PAD(0x5D0, 0x234, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__GPIO4_21 IOMUX_PAD(0x5D0, 0x234, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 IOMUX_PAD(0x5D0, 0x234, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK IOMUX_PAD(0x5D0, 0x234, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 IOMUX_PAD(0x5D4, 0x238, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__GPIO4_22 IOMUX_PAD(0x5D4, 0x238, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 IOMUX_PAD(0x5D4, 0x238, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 IOMUX_PAD(0x5D8, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__GPIO4_23 IOMUX_PAD(0x5D8, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 IOMUX_PAD(0x5DC, 0x240, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__GPIO4_24 IOMUX_PAD(0x5DC, 0x240, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 IOMUX_PAD(0x5E0, 0x244, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__GPIO4_25 IOMUX_PAD(0x5E0, 0x244, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 IOMUX_PAD(0x5E4, 0x248, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__GPIO4_26 IOMUX_PAD(0x5E4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 IOMUX_PAD(0x5E4, 0x248, 3, 0x70C, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 IOMUX_PAD(0x5E8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__GPIO4_27 IOMUX_PAD(0x5E8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 IOMUX_PAD(0x5EC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__GPIO4_28 IOMUX_PAD(0x5EC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 IOMUX_PAD(0x5F0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__GPIO4_29 IOMUX_PAD(0x5F0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 IOMUX_PAD(0x5F4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__GPIO4_30 IOMUX_PAD(0x5F4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6FC, 1, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 IOMUX_PAD(0x5F8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__GPIO1_0 IOMUX_PAD(0x5F8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__KPP_COL_4 IOMUX_PAD(0x5F8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 IOMUX_PAD(0x5F8, 0x25C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 IOMUX_PAD(0x5F8, 0x25C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 IOMUX_PAD(0x5FC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__GPIO1_1 IOMUX_PAD(0x5FC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__KPP_ROW_4 IOMUX_PAD(0x5FC, 0x260, 3, 0x7A0, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 IOMUX_PAD(0x5FC, 0x260, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 IOMUX_PAD(0x5FC, 0x260, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 IOMUX_PAD(0x600, 0x264, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__GPIO1_2 IOMUX_PAD(0x600, 0x264, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__KPP_COL_5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 IOMUX_PAD(0x600, 0x264, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 IOMUX_PAD(0x600, 0x264, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 IOMUX_PAD(0x604, 0x268, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__GPIO1_3 IOMUX_PAD(0x604, 0x268, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__KPP_ROW_5 IOMUX_PAD(0x604, 0x268, 3, 0x7A4, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 IOMUX_PAD(0x604, 0x268, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 IOMUX_PAD(0x604, 0x268, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 IOMUX_PAD(0x608, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__GPIO1_4 IOMUX_PAD(0x608, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__KPP_COL_6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 IOMUX_PAD(0x608, 0x26C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 IOMUX_PAD(0x608, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 IOMUX_PAD(0x60C, 0x270, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__GPIO1_5 IOMUX_PAD(0x60C, 0x270, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__KPP_ROW_6 IOMUX_PAD(0x60C, 0x270, 3, 0x7A8, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 IOMUX_PAD(0x60C, 0x270, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 IOMUX_PAD(0x60C, 0x270, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 IOMUX_PAD(0x610, 0x274, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__GPIO1_6 IOMUX_PAD(0x610, 0x274, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__KPP_COL_7 IOMUX_PAD(0x610, 0x274, 3, 0x79C, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 IOMUX_PAD(0x610, 0x274, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 IOMUX_PAD(0x610, 0x274, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 IOMUX_PAD(0x614, 0x278, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__GPIO1_7 IOMUX_PAD(0x614, 0x278, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__KPP_ROW_7 IOMUX_PAD(0x614, 0x278, 3, 0x7AC, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 IOMUX_PAD(0x614, 0x278, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 IOMUX_PAD(0x614, 0x278, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 IOMUX_PAD(0x618, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__GPIO1_8 IOMUX_PAD(0x618, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 IOMUX_PAD(0x618, 0x27C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 IOMUX_PAD(0x618, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 IOMUX_PAD(0x61C, 0x280, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__GPIO1_9 IOMUX_PAD(0x61C, 0x280, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 IOMUX_PAD(0x61C, 0x280, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 IOMUX_PAD(0x61C, 0x280, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 IOMUX_PAD(0x620, 0x284, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__GPIO1_10 IOMUX_PAD(0x620, 0x284, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 IOMUX_PAD(0x620, 0x284, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 IOMUX_PAD(0x620, 0x284, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 IOMUX_PAD(0x620, 0x284, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 IOMUX_PAD(0x624, 0x288, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__GPIO1_11 IOMUX_PAD(0x624, 0x288, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 IOMUX_PAD(0x624, 0x288, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 IOMUX_PAD(0x624, 0x288, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 IOMUX_PAD(0x624, 0x288, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 IOMUX_PAD(0x628, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__GPIO1_12 IOMUX_PAD(0x628, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 IOMUX_PAD(0x628, 0x28C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 IOMUX_PAD(0x628, 0x28C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 IOMUX_PAD(0x628, 0x28C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 IOMUX_PAD(0x628, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 IOMUX_PAD(0x62C, 0x290, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__GPIO1_13 IOMUX_PAD(0x62C, 0x290, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 IOMUX_PAD(0x62C, 0x290, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 IOMUX_PAD(0x62C, 0x290, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 IOMUX_PAD(0x62C, 0x290, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 IOMUX_PAD(0x62C, 0x290, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 IOMUX_PAD(0x630, 0x294, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__GPIO1_14 IOMUX_PAD(0x630, 0x294, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 IOMUX_PAD(0x630, 0x294, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 IOMUX_PAD(0x630, 0x294, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 IOMUX_PAD(0x630, 0x294, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 IOMUX_PAD(0x634, 0x298, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__GPIO1_15 IOMUX_PAD(0x634, 0x298, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 IOMUX_PAD(0x634, 0x298, 3, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 IOMUX_PAD(0x634, 0x298, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 IOMUX_PAD(0x634, 0x298, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 IOMUX_PAD(0x638, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__GPIO1_16 IOMUX_PAD(0x638, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 IOMUX_PAD(0x638, 0x29C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__TPIU_TRCLK IOMUX_PAD(0x638, 0x29C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 IOMUX_PAD(0x638, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 IOMUX_PAD(0x63C, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__GPIO1_17 IOMUX_PAD(0x63C, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__TPIU_TRCTL IOMUX_PAD(0x63C, 0x2A0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 IOMUX_PAD(0x63C, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 IOMUX_PAD(0x640, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS0__GPIO1_18 IOMUX_PAD(0x640, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 IOMUX_PAD(0x640, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 IOMUX_PAD(0x644, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB0__GPIO1_19 IOMUX_PAD(0x644, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 IOMUX_PAD(0x644, 0x2A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 IOMUX_PAD(0x648, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB1__GPIO1_20 IOMUX_PAD(0x648, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 IOMUX_PAD(0x648, 0x2AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__GPIO1_21 IOMUX_PAD(0x64C, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B IOMUX_PAD(0x64C, 0x2B0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 IOMUX_PAD(0x64C, 0x2B0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_BCLK__GPIO1_22 IOMUX_PAD(0x650, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 IOMUX_PAD(0x650, 0x2B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RDY__GPIO1_23 IOMUX_PAD(0x654, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 IOMUX_PAD(0x654, 0x2B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_OE__EIM_WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_OE__GPIO1_24 IOMUX_PAD(0x658, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_OE__INT_BOOT IOMUX_PAD(0x658, 0x2BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RW__EIM_WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RW__GPIO1_25 IOMUX_PAD(0x65C, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RW__SYSTEM_RST IOMUX_PAD(0x65C, 0x2C0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_LBA__GPIO1_26 IOMUX_PAD(0x660, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_LBA__TESTER_ACK IOMUX_PAD(0x660, 0x2C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CRE__GPIO1_27 IOMUX_PAD(0x664, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h deleted file mode 100644 index 2623e7a2e1..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx51.h +++ /dev/null @@ -1,827 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX51_H__ -#define __MACH_IOMUX_MX51_H__ - -#include <mach/iomux-v3.h> -#define __NA_ 0x000 - - -/* Pad control groupings */ -#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS | PAD_CTL_PUE) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ - PAD_CTL_SRE_FAST | PAD_CTL_DVS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) - -#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - -/* - * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* Raw pin modes without pad control */ -/* PAD MUX ALT INPSE PATH PADCTRL */ - -/* The same pins as above but with the default pad control values applied */ -#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ - MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) -#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx53.h b/arch/arm/mach-imx/include/mach/iomux-mx53.h deleted file mode 100644 index 527f8fe3e3..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx53.h +++ /dev/null @@ -1,1219 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc.. - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_IOMUX_MX53_H__ -#define __MACH_IOMUX_MX53_H__ - -#include <mach/iomux-v3.h> - -/* These 2 defines are for pins that may not have a mux register, but could - * have a pad setting register, and vice-versa. */ -#define __NA_ 0x00 - -#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) - - -#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ - IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ - IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ - IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ - IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ - IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ - IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ - IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ - IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ - IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ - IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ - IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ - IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C) -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) -#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6.h b/arch/arm/mach-imx/include/mach/iomux-mx6.h deleted file mode 100644 index 57d1a3bf9f..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx6.h +++ /dev/null @@ -1,5633 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Auto Generate file, please don't edit it - * - */ -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#ifndef __MACH_IOMUX_MX6Q_H__ -#define __MACH_IOMUX_MX6Q_H__ - -#include <mach/iomux-v3.h> - -#define NON_MUX_I 0x3FF -#define NON_PAD_I 0x7FF - -/* - * Use to set PAD control - */ -#define MX6_PAD_CTL_HYS (1 << 16) - -#define MX6_PAD_CTL_PUS_100K_DOWN (0 << 14) -#define MX6_PAD_CTL_PUS_47K_UP (1 << 14) -#define MX6_PAD_CTL_PUS_100K_UP (2 << 14) -#define MX6_PAD_CTL_PUS_22K_UP (3 << 14) - -#define MX6_PAD_CTL_PUE (1 << 13) -#define MX6_PAD_CTL_PKE (1 << 12) -#define MX6_PAD_CTL_ODE (1 << 11) - -#define MX6_PAD_CTL_SPEED_LOW (1 << 6) -#define MX6_PAD_CTL_SPEED_MED (2 << 6) -#define MX6_PAD_CTL_SPEED_HIGH (3 << 6) - -#define MX6_PAD_CTL_DSE_DISABLE (0 << 3) -#define MX6_PAD_CTL_DSE_240ohm (1 << 3) -#define MX6_PAD_CTL_DSE_120ohm (2 << 3) -#define MX6_PAD_CTL_DSE_80ohm (3 << 3) -#define MX6_PAD_CTL_DSE_60ohm (4 << 3) -#define MX6_PAD_CTL_DSE_48ohm (5 << 3) -#define MX6_PAD_CTL_DSE_40ohm (6 << 3) -#define MX6_PAD_CTL_DSE_34ohm (7 << 3) - -#define MX6_PAD_CTL_SRE_FAST (1 << 0) -#define MX6_PAD_CTL_SRE_SLOW (0 << 0) - -#define MX6Q_UART_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS) - -#define MX6Q_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS) - -#define MX6Q_USDHC_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_HIGH | \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS) - -#define MX6Q_ENET_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS) - -#define MX6Q_I2C_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \ - MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST) - -#define MX6Q_PWM_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED| \ - MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \ - MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST) - -#define MX6Q_USB_HSIC_PAD_CTRL (MX6_PAD_CTL_HYS | MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \ - MX6_PAD_CTL_DSE_40ohm) - -#define MX6Q_HIGH_DRV (MX6_PAD_CTL_DSE_120ohm) - -#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ - IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \ - IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \ - IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \ - IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \ - IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \ - IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \ - IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \ - IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \ - IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \ - IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \ - IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \ - IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \ - IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \ - IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \ - IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \ - IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \ - IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \ - IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ - IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \ - IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \ - IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \ - IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \ - IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \ - IOMUX_PAD(0x036C, 0x0058, IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \ - IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \ - IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0) -#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \ - IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \ - IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \ - IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \ - IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \ - IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \ - IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \ - IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \ - IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \ - IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \ - IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \ - IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \ - IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \ - IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \ - IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \ - IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \ - IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \ - IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \ - IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \ - IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \ - IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \ - IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \ - IOMUX_PAD(0x0380, 0x006C, IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \ - IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0) -#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \ - IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \ - IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \ - IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \ - IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0) -#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \ - IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \ - IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \ - IOMUX_PAD(0x0388, 0x0074, IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \ - IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \ - IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \ - IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \ - IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0) - -#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \ - IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \ - IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0) -#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \ - IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \ - IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \ - IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \ - IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \ - IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0) -#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \ - IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \ - IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \ - IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \ - IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0) -#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \ - IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \ - IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \ - IOMUX_PAD(0x0398, 0x0084, IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \ - IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0) -#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \ - IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \ - IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \ - IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \ - IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \ - IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \ - IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \ - IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \ - IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \ - IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0) -#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \ - IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \ - IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \ - IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0) -#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \ - IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0) -#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \ - IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0) -#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \ - IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0) -#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \ - IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \ - IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0) -#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \ - IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \ - IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \ - IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0) -#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \ - IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \ - IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0) -#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \ - IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0) -#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \ - IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D16__I2C2_SDA \ - IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0) - -#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \ - IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \ - IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0) -#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \ - IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \ - IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0) -#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \ - IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \ - IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D17__I2C3_SCL \ - IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0) -#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \ - IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \ - IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \ - IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0) -#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \ - IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \ - IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0) -#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \ - IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \ - IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D18__I2C3_SDA \ - IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0) -#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \ - IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \ - IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \ - IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0) -#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \ - IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \ - IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0) -#define _MX6Q_PAD_EIM_D19__UART1_CTS \ - IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0) -#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \ - IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \ - IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \ - IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \ - IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \ - IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0) -#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \ - IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \ - IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0) -#define _MX6Q_PAD_EIM_D20__UART1_CTS \ - IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D20__UART1_RTS \ - IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0) -#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \ - IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \ - IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \ - IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \ - IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \ - IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \ - IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0) -#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \ - IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0) -#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \ - IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D21__I2C1_SCL \ - IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0) -#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \ - IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0) - -#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \ - IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \ - IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \ - IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \ - IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0) -#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \ - IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \ - IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \ - IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \ - IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \ - IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \ - IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D23__UART3_CTS \ - IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0) -#define _MX6Q_PAD_EIM_D23__UART1_DCD \ - IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \ - IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0) -#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \ - IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \ - IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \ - IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \ - IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \ - IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__UART3_CTS \ - IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__UART3_RTS \ - IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0) -#define _MX6Q_PAD_EIM_EB3__UART1_RI \ - IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \ - IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0) -#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \ - IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \ - IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \ - IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \ - IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \ - IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D24__UART3_TXD \ - IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D24__UART3_RXD \ - IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0) -#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \ - IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0) -#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \ - IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \ - IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \ - IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0) -#define _MX6Q_PAD_EIM_D24__UART1_DTR \ - IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \ - IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \ - IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D25__UART3_TXD \ - IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D25__UART3_RXD \ - IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0) -#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \ - IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0) -#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \ - IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \ - IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \ - IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0) -#define _MX6Q_PAD_EIM_D25__UART1_DSR \ - IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \ - IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \ - IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \ - IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \ - IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0) -#define _MX6Q_PAD_EIM_D26__UART2_TXD \ - IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__UART2_RXD \ - IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0) -#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \ - IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \ - IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \ - IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \ - IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \ - IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \ - IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \ - IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0) -#define _MX6Q_PAD_EIM_D27__UART2_TXD \ - IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__UART2_RXD \ - IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0) -#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \ - IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \ - IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \ - IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ - IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D28__I2C1_SDA \ - IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0) -#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ - IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ - IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0) -#define _MX6Q_PAD_EIM_D28__UART2_CTS \ - IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0) -#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \ - IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \ - IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \ - IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \ - IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \ - IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \ - IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0) -#define _MX6Q_PAD_EIM_D29__UART2_CTS \ - IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D29__UART2_RTS \ - IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0) -#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \ - IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \ - IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0) -#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \ - IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \ - IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \ - IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \ - IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \ - IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D30__UART3_CTS \ - IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0) -#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \ - IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \ - IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0) -#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \ - IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \ - IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \ - IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \ - IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \ - IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__UART3_CTS \ - IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__UART3_RTS \ - IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0) -#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \ - IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \ - IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \ - IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \ - IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \ - IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \ - IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0) -#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \ - IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \ - IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \ - IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \ - IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \ - IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \ - IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \ - IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \ - IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0) -#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \ - IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \ - IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \ - IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \ - IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \ - IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \ - IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \ - IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \ - IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0) -#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \ - IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \ - IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \ - IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \ - IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \ - IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \ - IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0) -#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \ - IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \ - IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \ - IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \ - IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \ - IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \ - IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \ - IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \ - IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0) -#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \ - IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \ - IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \ - IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \ - IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \ - IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \ - IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \ - IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \ - IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0) -#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \ - IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \ - IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \ - IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \ - IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \ - IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \ - IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \ - IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \ - IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0) -#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \ - IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \ - IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \ - IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \ - IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \ - IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \ - IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \ - IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \ - IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0) -#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \ - IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \ - IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \ - IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \ - IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \ - IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \ - IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \ - IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \ - IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0) -#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \ - IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \ - IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \ - IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \ - IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \ - IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \ - IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \ - IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0) -#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \ - IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \ - IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \ - IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \ - IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \ - IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \ - IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0) -#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \ - IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \ - IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \ - IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \ - IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \ - IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \ - IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0) -#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \ - IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \ - IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \ - IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \ - IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \ - IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \ - IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0) -#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \ - IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \ - IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \ - IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \ - IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \ - IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \ - IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \ - IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0) -#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \ - IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \ - IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \ - IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \ - IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \ - IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \ - IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0) -#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \ - IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \ - IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0) -#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \ - IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \ - IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \ - IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \ - IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \ - IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \ - IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0) -#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \ - IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \ - IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \ - IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \ - IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \ - IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \ - IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \ - IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \ - IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \ - IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \ - IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \ - IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \ - IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \ - IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \ - IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \ - IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ - IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \ - IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \ - IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \ - IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \ - IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \ - IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \ - IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \ - IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ - IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \ - IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \ - IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \ - IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \ - IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \ - IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \ - IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \ - IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \ - IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \ - IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \ - IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \ - IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \ - IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \ - IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \ - IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \ - IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \ - IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \ - IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \ - IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \ - IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \ - IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \ - IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \ - IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \ - IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \ - IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \ - IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \ - IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \ - IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \ - IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \ - IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \ - IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \ - IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \ - IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \ - IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \ - IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \ - IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \ - IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \ - IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \ - IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \ - IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \ - IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \ - IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \ - IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \ - IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \ - IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \ - IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \ - IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \ - IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \ - IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \ - IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \ - IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \ - IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \ - IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \ - IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \ - IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \ - IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \ - IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \ - IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \ - IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \ - IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0) -#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \ - IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \ - IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \ - IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \ - IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \ - IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \ - IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \ - IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0) -#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \ - IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \ - IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \ - IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \ - IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \ - IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \ - IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \ - IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \ - IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0) -#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \ - IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \ - IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \ - IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \ - IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \ - IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \ - IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \ - IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \ - IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0) -#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \ - IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \ - IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \ - IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \ - IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \ - IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \ - IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \ - IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \ - IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \ - IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \ - IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \ - IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \ - IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \ - IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \ - IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \ - IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \ - IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \ - IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \ - IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \ - IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \ - IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \ - IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \ - IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \ - IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \ - IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \ - IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \ - IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \ - IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \ - IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \ - IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \ - IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \ - IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \ - IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \ - IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \ - IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \ - IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \ - IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \ - IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \ - IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \ - IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \ - IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \ - IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \ - IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \ - IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \ - IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \ - IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \ - IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \ - IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \ - IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \ - IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \ - IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \ - IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \ - IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \ - IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \ - IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \ - IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \ - IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \ - IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \ - IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \ - IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \ - IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \ - IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \ - IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \ - IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \ - IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \ - IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \ - IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \ - IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \ - IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \ - IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \ - IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \ - IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \ - IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \ - IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \ - IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \ - IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \ - IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \ - IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ - IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \ - IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \ - IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \ - IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \ - IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \ - IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \ - IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \ - IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \ - IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \ - IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \ - IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \ - IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \ - IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \ - IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \ - IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \ - IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \ - IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \ - IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \ - IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \ - IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \ - IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \ - IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \ - IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \ - IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \ - IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \ - IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \ - IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \ - IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \ - IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \ - IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \ - IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \ - IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \ - IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \ - IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \ - IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \ - IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \ - IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \ - IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \ - IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \ - IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \ - IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \ - IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \ - IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \ - IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \ - IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \ - IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \ - IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \ - IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \ - IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \ - IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \ - IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \ - IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \ - IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \ - IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \ - IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \ - IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \ - IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \ - IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \ - IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \ - IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \ - IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \ - IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \ - IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \ - IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \ - IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \ - IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \ - IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \ - IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \ - IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \ - IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \ - IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ - IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \ - IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \ - IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \ - IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \ - IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \ - IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \ - IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ - IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \ - IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \ - IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \ - IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \ - IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \ - IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \ - IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ - IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \ - IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \ - IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \ - IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \ - IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \ - IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \ - IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0) -#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ - IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \ - IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \ - IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \ - IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \ - IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \ - IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \ - IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0) -#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ - IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \ - IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \ - IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \ - IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \ - IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \ - IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0) -#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \ - IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0) -#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ - IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \ - IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \ - IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \ - IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \ - IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \ - IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \ - IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0) -#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \ - IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \ - IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \ - IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \ - IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \ - IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \ - IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \ - IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \ - IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0) -#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \ - IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \ - IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \ - IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \ - IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \ - IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \ - IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \ - IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \ - IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0) -#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \ - IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \ - IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \ - IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \ - IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \ - IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \ - IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \ - IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \ - IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0) -#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \ - IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \ - IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \ - IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \ - IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \ - IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \ - IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \ - IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \ - IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0) -#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \ - IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ - IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \ - IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \ - IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \ - IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \ - IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \ - IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \ - IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0) -#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \ - IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0) -#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \ - IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \ - IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \ - IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \ - IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \ - IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \ - IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \ - IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0) -#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \ - IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0) -#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \ - IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \ - IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \ - IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \ - IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \ - IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \ - IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \ - IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0) -#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \ - IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0) -#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \ - IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \ - IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \ - IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \ - IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \ - IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \ - IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \ - IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ - IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \ - IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \ - IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \ - IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \ - IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \ - IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \ - IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \ - IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \ - IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \ - IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ - IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \ - IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \ - IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0) -#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \ - IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0) -#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \ - IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \ - IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \ - IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ - IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \ - IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \ - IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0) -#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \ - IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0) -#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \ - IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0) -#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \ - IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \ - IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ - IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \ - IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0) -#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \ - IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0) -#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \ - IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0) -#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \ - IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \ - IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \ - IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ - IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \ - IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \ - IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0) -#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \ - IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0) -#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \ - IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \ - IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \ - IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ - IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \ - IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \ - IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \ - IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0) -#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \ - IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \ - IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ - IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \ - IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \ - IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \ - IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \ - IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \ - IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \ - IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ - IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \ - IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \ - IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \ - IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0) -#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \ - IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \ - IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ - IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \ - IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0) -#define _MX6Q_PAD_ENET_MDC__ENET_MDC \ - IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \ - IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0) -#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ - IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \ - IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \ - IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ - IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \ - IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \ - IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \ - IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \ - IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ - IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ - IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ - IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ - IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \ - IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \ - IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \ - IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \ - IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \ - IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \ - IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \ - IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \ - IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \ - IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \ - IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \ - IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \ - IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \ - IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \ - IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \ - IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \ - IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \ - IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ - IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ - IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \ - IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \ - IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ - IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ - IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ - IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ - IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ - IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \ - IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ - IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ - IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ - IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ - IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ - IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ - IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ - IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ - IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \ - IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \ - IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \ - IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \ - IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \ - IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0) -#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \ - IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0) -#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \ - IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0) -#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \ - IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL0__UART4_TXD \ - IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL0__UART4_RXD \ - IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0) -#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \ - IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \ - IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \ - IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \ - IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0) -#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \ - IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \ - IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0) -#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \ - IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \ - IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \ - IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0) -#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \ - IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \ - IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \ - IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \ - IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0) -#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \ - IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0) -#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \ - IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0) -#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \ - IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL1__UART5_TXD \ - IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL1__UART5_RXD \ - IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0) -#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \ - IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \ - IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \ - IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \ - IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0) -#define _MX6Q_PAD_KEY_ROW1__ENET_COL \ - IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \ - IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0) -#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \ - IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \ - IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \ - IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0) -#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \ - IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \ - IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \ - IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \ - IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0) -#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \ - IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0) -#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \ - IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \ - IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL2__ENET_MDC \ - IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \ - IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \ - IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \ - IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \ - IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0) -#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \ - IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \ - IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0) -#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \ - IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \ - IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \ - IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ - IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0) -#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \ - IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \ - IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0) -#define _MX6Q_PAD_KEY_COL3__ENET_CRS \ - IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ - IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0) -#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \ - IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \ - IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0) -#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \ - IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \ - IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0) -#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \ - IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \ - IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ - IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0) -#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ - IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0) -#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ - IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \ - IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0) -#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \ - IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \ - IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \ - IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \ - IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \ - IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \ - IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0) -#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \ - IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__UART5_CTS \ - IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__UART5_RTS \ - IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0) -#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \ - IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \ - IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \ - IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \ - IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \ - IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \ - IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \ - IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \ - IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0) -#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \ - IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \ - IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \ - IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_0__CCM_CLKO \ - IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \ - IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0) -#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \ - IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0) -#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \ - IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \ - IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \ - IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \ - IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \ - IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0) -#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \ - IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \ - IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0) -#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \ - IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \ - IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_1__USDHC1_CD \ - IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \ - IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \ - IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0) -#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \ - IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \ - IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0) -#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \ - IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \ - IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \ - IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_9__USDHC1_WP \ - IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0) -#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \ - IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \ - IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0) -#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ - IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_3__I2C3_SCL \ - IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0) -#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ - IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \ - IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \ - IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \ - IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0) -#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \ - IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0) - -#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \ - IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0) -#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ - IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_6__I2C3_SDA \ - IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0) -#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ - IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \ - IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \ - IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \ - IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \ - IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0) - -#define _MX6Q_PAD_GPIO_2__ESAI1_FST \ - IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0) -#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \ - IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \ - IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0) -#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \ - IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \ - IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \ - IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_2__USDHC2_WP \ - IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \ - IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0) - -#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \ - IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0) -#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \ - IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \ - IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0) -#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \ - IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \ - IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \ - IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_4__USDHC2_CD \ - IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ - IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \ - IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0) -#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \ - IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \ - IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0) -#define _MX6Q_PAD_GPIO_5__CCM_CLKO \ - IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \ - IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \ - IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_5__I2C3_SCL \ - IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0) -#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \ - IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \ - IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0) -#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \ - IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \ - IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \ - IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__UART2_TXD \ - IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__UART2_RXD \ - IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0) -#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \ - IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \ - IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \ - IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \ - IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0) -#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \ - IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \ - IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \ - IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0) -#define _MX6Q_PAD_GPIO_8__UART2_TXD \ - IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_8__UART2_RXD \ - IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0) -#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \ - IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \ - IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \ - IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \ - IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0) -#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \ - IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ - IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0) -#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \ - IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \ - IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0) -#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \ - IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_16__I2C3_SDA \ - IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0) -#define _MX6Q_PAD_GPIO_16__SJC_DE_B \ - IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \ - IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0) -#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \ - IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \ - IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0) -#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \ - IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0) -#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \ - IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \ - IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \ - IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \ - IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0) -#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \ - IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0) -#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \ - IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \ - IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0) -#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \ - IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0) -#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \ - IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \ - IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \ - IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \ - IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0) -#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \ - IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \ - IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__CCM_CLKO \ - IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \ - IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \ - IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \ - IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \ - IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \ - IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \ - IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \ - IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \ - IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \ - IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \ - IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \ - IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \ - IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \ - IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \ - IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \ - IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \ - IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \ - IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \ - IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \ - IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \ - IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \ - IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \ - IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \ - IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \ - IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \ - IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \ - IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \ - IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \ - IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \ - IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \ - IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \ - IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \ - IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \ - IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \ - IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0) -#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \ - IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0) -#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \ - IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \ - IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \ - IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \ - IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \ - IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \ - IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \ - IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0) -#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \ - IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0) -#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ - IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \ - IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ - IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \ - IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \ - IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \ - IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \ - IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0) -#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \ - IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0) -#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \ - IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \ - IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \ - IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \ - IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \ - IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \ - IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \ - IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0) -#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \ - IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0) -#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \ - IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \ - IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \ - IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \ - IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \ - IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \ - IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \ - IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0) -#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \ - IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0) -#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \ - IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0) -#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \ - IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ - IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \ - IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \ - IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \ - IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \ - IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0) -#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \ - IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0) -#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \ - IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0) -#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \ - IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ - IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \ - IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \ - IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \ - IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \ - IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0) -#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \ - IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \ - IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \ - IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \ - IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \ - IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \ - IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \ - IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \ - IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \ - IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0) -#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \ - IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \ - IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0) -#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \ - IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \ - IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \ - IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \ - IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \ - IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \ - IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \ - IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \ - IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \ - IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0) -#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \ - IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \ - IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \ - IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \ - IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \ - IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \ - IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \ - IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \ - IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \ - IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0) -#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \ - IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \ - IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \ - IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \ - IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \ - IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \ - IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \ - IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \ - IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \ - IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0) -#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \ - IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \ - IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \ - IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \ - IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \ - IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \ - IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \ - IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \ - IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \ - IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0) -#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \ - IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \ - IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \ - IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \ - IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \ - IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \ - IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \ - IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \ - IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \ - IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \ - IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \ - IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \ - IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \ - IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \ - IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \ - IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \ - IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \ - IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0) -#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \ - IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \ - IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \ - IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \ - IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \ - IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \ - IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \ - IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \ - IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \ - IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0) -#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \ - IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \ - IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \ - IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \ - IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \ - IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \ - IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \ - IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \ - IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0) -#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \ - IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \ - IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \ - IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \ - IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \ - IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \ - IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \ - IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \ - IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \ - IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \ - IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_POR_B__SRC_POR_B \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \ - IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \ - IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \ - IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \ - IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0) -#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \ - IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \ - IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \ - IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \ - IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \ - IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ - IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \ - IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \ - IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \ - IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0) -#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \ - IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \ - IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \ - IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \ - IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \ - IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \ - IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \ - IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \ - IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \ - IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0) -#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \ - IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \ - IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \ - IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \ - IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \ - IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \ - IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \ - IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \ - IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \ - IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0) -#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \ - IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \ - IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \ - IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \ - IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \ - IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \ - IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \ - IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__UART2_CTS \ - IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0) -#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \ - IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \ - IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \ - IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \ - IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \ - IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \ - IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \ - IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__UART2_CTS \ - IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__UART2_RTS \ - IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0) -#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \ - IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0) -#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \ - IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \ - IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \ - IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \ - IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \ - IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \ - IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \ - IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0) -#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \ - IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \ - IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \ - IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \ - IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \ - IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \ - IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \ - IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \ - IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \ - IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0) -#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \ - IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0) -#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \ - IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \ - IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \ - IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \ - IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \ - IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \ - IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \ - IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \ - IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \ - IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \ - IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \ - IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \ - IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \ - IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \ - IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0) -#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \ - IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \ - IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \ - IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \ - IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \ - IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \ - IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD3_RST__USDHC3_RST \ - IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__UART3_CTS \ - IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__UART3_RTS \ - IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0) -#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \ - IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \ - IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \ - IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \ - IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \ - IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \ - IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \ - IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \ - IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \ - IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \ - IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \ - IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \ - IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \ - IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \ - IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \ - IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \ - IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \ - IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \ - IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \ - IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \ - IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \ - IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \ - IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \ - IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \ - IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \ - IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \ - IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \ - IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \ - IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \ - IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \ - IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \ - IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \ - IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \ - IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \ - IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \ - IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \ - IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \ - IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \ - IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \ - IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \ - IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \ - IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \ - IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \ - IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \ - IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \ - IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \ - IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \ - IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \ - IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \ - IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \ - IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \ - IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \ - IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0) -#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \ - IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \ - IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \ - IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \ - IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \ - IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \ - IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \ - IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0) -#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \ - IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \ - IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \ - IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \ - IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \ - IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \ - IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \ - IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CMD__UART3_TXD \ - IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CMD__UART3_RXD \ - IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0) -#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \ - IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \ - IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \ - IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \ - IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \ - IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CLK__UART3_TXD \ - IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CLK__UART3_RXD \ - IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0) -#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \ - IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \ - IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \ - IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \ - IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \ - IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \ - IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \ - IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \ - IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \ - IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \ - IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \ - IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \ - IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \ - IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \ - IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \ - IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \ - IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \ - IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \ - IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \ - IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \ - IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \ - IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \ - IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \ - IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \ - IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \ - IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \ - IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \ - IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \ - IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \ - IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \ - IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \ - IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \ - IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \ - IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \ - IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \ - IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \ - IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \ - IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \ - IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \ - IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \ - IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \ - IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \ - IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \ - IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \ - IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \ - IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \ - IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \ - IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \ - IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \ - IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \ - IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \ - IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \ - IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \ - IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \ - IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \ - IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \ - IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \ - IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \ - IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \ - IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \ - IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \ - IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \ - IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \ - IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \ - IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \ - IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \ - IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \ - IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \ - IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \ - IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \ - IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \ - IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \ - IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \ - IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \ - IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \ - IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \ - IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \ - IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \ - IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \ - IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \ - IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \ - IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \ - IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \ - IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \ - IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \ - IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \ - IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \ - IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \ - IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \ - IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \ - IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \ - IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \ - IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \ - IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \ - IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \ - IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \ - IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \ - IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \ - IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \ - IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \ - IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \ - IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0) -#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \ - IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \ - IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \ - IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \ - IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \ - IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \ - IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \ - IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \ - IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \ - IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0) -#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \ - IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \ - IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \ - IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \ - IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \ - IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \ - IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \ - IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \ - IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0) -#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \ - IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \ - IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \ - IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \ - IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \ - IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \ - IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \ - IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \ - IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \ - IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0) -#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \ - IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \ - IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \ - IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \ - IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \ - IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \ - IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \ - IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0) -#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \ - IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \ - IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \ - IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \ - IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \ - IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \ - IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \ - IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \ - IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0) -#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \ - IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \ - IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \ - IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \ - IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \ - IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \ - IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \ - IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \ - IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \ - IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \ - IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \ - IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \ - IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \ - IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \ - IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \ - IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \ - IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0) -#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \ - IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \ - IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \ - IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \ - IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \ - IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \ - IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0) -#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \ - IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \ - IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \ - IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \ - IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \ - IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \ - IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \ - IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \ - IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0) -#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \ - IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \ - IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \ - IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \ - IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \ - IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \ - IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \ - IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0) -#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \ - IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0) -#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ - IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0) -#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \ - IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \ - IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \ - IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \ - IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \ - IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \ - IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0) -#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \ - IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0) -#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ - IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0) -#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \ - IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \ - IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0) - -#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \ - IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \ - IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \ - IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0) -#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \ - IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0) -#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \ - IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \ - IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \ - IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0) -#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ - IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0) - -#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__CCM_WAIT (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__CCM_STOP (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD1__SJC_FAIL (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__ECSPI2_RDY (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__GPIO_5_2 (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__GPIO_3_19 (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__EPIT1_EPITO (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__UART1_CTS (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__UART1_RTS (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__GPIO_3_20 (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D20__EPIT2_EPITO (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__ECSPI4_MISO (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__GPIO_3_22 (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__UART3_CTS (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__UART1_DCD (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__GPIO_3_23 (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__UART3_CTS (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__UART3_RTS (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__UART1_RI (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__GPIO_2_31 (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__UART3_TXD (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__UART3_RXD (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__GPIO_3_24 (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D24__UART1_DTR (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__UART3_TXD (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__UART3_RXD (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__GPIO_3_25 (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D25__UART1_DSR (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__UART2_TXD (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__UART2_RXD (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__GPIO_3_26 (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__UART2_TXD (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__UART2_RXD (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__GPIO_3_27 (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__GPIO_3_28 (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__UART2_CTS (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__UART2_RTS (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__GPIO_3_29 (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__UART3_CTS (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__GPIO_3_30 (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__UART3_CTS (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__UART3_RTS (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__GPIO_3_31 (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__GPIO_5_4 (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__GPIO_6_6 (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A22__GPIO_2_16 (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__RESERVED_RESERVED (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__GPIO_2_17 (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__RESERVED_RESERVED (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__GPIO_2_18 (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__RESERVED_RESERVED (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__GPIO_2_19 (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__RESERVED_RESERVED (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__GPIO_2_20 (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__RESERVED_RESERVED (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__GPIO_2_21 (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__GPIO_2_22 (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS0__GPIO_2_23 (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS1__GPIO_2_24 (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_OE__ECSPI2_MISO (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_OE__GPIO_2_25 (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__GPIO_2_26 (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_LBA__GPIO_2_27 (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__GPIO_2_28 (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__GPIO_2_29 (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__GPIO_3_0 (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__GPIO_3_1 (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__GPIO_3_2 (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__GPIO_3_3 (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__GPIO_3_4 (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__GPIO_3_5 (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__GPIO_3_6 (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__GPIO_3_7 (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__GPIO_3_8 (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__GPIO_3_9 (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__GPIO_3_10 (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__GPIO_3_11 (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__GPIO_3_12 (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__GPIO_3_13 (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__GPIO_3_14 (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__GPIO_3_15 (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__USDHC1_WP (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__PHY_TDI (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__ESAI1_FST (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__PHY_TCK (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__PHY_TMS (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__KPP_COL_0 (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__UART4_TXD (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__UART4_RXD (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__GPIO_4_6 (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__UART4_TXD (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__UART4_RXD (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__ENET_MDIO (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__KPP_COL_1 (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__UART5_TXD (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__UART5_RXD (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__GPIO_4_8 (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__ENET_COL (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__UART5_TXD (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__UART5_RXD (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__KPP_COL_2 (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__ENET_MDC (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__GPIO_4_10 (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__KPP_COL_4 (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__UART5_CTS (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__UART5_RTS (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__GPIO_4_14 (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__UART5_CTS (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_0__CCM_CLKO (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__KPP_COL_5 (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__EPIT1_EPITO (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__GPIO_1_0 (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_1__ESAI1_SCKR (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__KPP_ROW_5 (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__PWM2_PWMO (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__GPIO_1_1 (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__USDHC1_CD (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_9__ESAI1_FSR (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) -#define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__MLB_MLBCLK (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__USDHC2_LCTL (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__MLB_MLBSIG (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_2__ESAI1_FST (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__KPP_ROW_6 (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__GPIO_1_2 (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__USDHC2_WP (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_2__MLB_MLBDAT (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_4__ESAI1_HCKT (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__KPP_COL_7 (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__GPIO_1_4 (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__USDHC2_CD (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__KPP_ROW_7 (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__ECSPI5_RDY (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__EPIT1_EPITO (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__CAN1_TXCAN (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__UART2_TXD (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__UART2_RXD (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__GPIO_1_7 (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__EPIT2_EPITO (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__CAN1_RXCAN (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__UART2_TXD (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__UART2_RXD (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__GPIO_1_8 (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__GPIO_7_12 (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_18__ESAI1_TX1 (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__ENET_RX_CLK (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__GPIO_7_13 (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_GPIO_19__KPP_COL_5 (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__CCM_CLKO (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__ECSPI1_RDY (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__GPIO_4_5 (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__ENET_TX_ER (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__UART1_TXD (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__UART1_RXD (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__UART1_TXD (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__UART1_RXD (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__UART4_TXD (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__UART4_RXD (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__UART4_TXD (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__UART4_RXD (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__UART5_TXD (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__UART5_RXD (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__UART5_TXD (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__UART5_RXD (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__UART4_CTS (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__UART4_RTS (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__UART4_CTS (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__UART5_CTS (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__UART5_RTS (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__UART5_CTS (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_TMS__SJC_TMS (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_MOD__SJC_MOD (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_TDI__SJC_TDI (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_TCK__SJC_TCK (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_JTAG_TDO__SJC_TDO (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_POR_B__SRC_POR_B (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__UART1_TXD (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__UART1_RXD (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__UART1_TXD (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__UART1_RXD (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__UART2_TXD (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__UART2_RXD (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__UART2_TXD (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__UART2_RXD (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_CMD__USDHC3_CMD (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__UART2_CTS (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__GPIO_7_2 (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_CLK__USDHC3_CLK (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__UART2_CTS (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__UART2_RTS (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__GPIO_7_3 (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__UART1_CTS (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__UART1_CTS (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__UART1_RTS (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__UART3_CTS (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD3_RST__USDHC3_RST (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__UART3_CTS (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__UART3_RTS (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__GPIO_7_8 (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__USDHC4_RST (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_CMD__USDHC4_CMD (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__UART3_TXD (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__UART3_RXD (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__GPIO_7_9 (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_CLK__USDHC4_CLK (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_CLK__UART3_TXD (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_CLK__UART3_RXD (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_CLK__GPIO_7_10 (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__GPIO_2_0 (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__GPIO_2_1 (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__GPIO_2_2 (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__GPIO_2_3 (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__GPIO_2_4 (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__GPIO_2_5 (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__GPIO_2_6 (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__GPIO_2_7 (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__UART2_TXD (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__UART2_RXD (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__UART2_CTS (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__UART2_RTS (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__UART2_CTS (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__UART2_TXD (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__UART2_RXD (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_CMD__USDHC1_CMD (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CMD__PWM4_PWMO (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CMD__GPIO_1_18 (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD1_CLK__USDHC1_CLK (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__GPT_CLKIN (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__GPIO_1_20 (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD2_CLK__USDHC2_CLK (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__KPP_COL_5 (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__GPIO_1_10 (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD2_CMD__USDHC2_CMD (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_CMD__GPIO_1_11 (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__SJC_DONE (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) - -#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-mx7.h b/arch/arm/mach-imx/include/mach/iomux-mx7.h deleted file mode 100644 index def9cf4d44..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx7.h +++ /dev/null @@ -1,1330 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_IOMUX_IMX7D_H__ -#define __MACH_IOMUX_IMX7D_H__ - -#include <mach/iomux-v3.h> -#include <mach/imx7-regs.h> - -enum { - MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), - MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), - - MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), - MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), - - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), - MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), - MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), - MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), - - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), - MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), - MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), - - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), - MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), - MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), - MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), - MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), - - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), - MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), - MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), - MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), -}; - -enum { - MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), - MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), - MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), - MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), - MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), - MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), - MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), - MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), - MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), - MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), - MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), - MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), - MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), - MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), - MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), - MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), - MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), - MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), - MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), - - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), - MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), - MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), - - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), - MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), - MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), - MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), - - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), - MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), - MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), - - MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), - MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), - MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), - MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), - MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), - MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), - MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), - - MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), - MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), - MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), - MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), - MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), - MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), - MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), - MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), - MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), - MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), - MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), - MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), - MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), - MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), - MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), - MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), - MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), - MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), - MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), - MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), - MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), - MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), - MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), - MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), - MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), - MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), - MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), - MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), - MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), - MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), - MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), - MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), - MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), - MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), - MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), - MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), - MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), - - MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), - MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), - MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), - - MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), - MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), - MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), - - MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), - MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), - MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), - - MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), - MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), - - MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), - MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), - MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), - - MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), - MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), - MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), - - MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), - MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), - MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), - - MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), - MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), - MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), - - MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), - MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), - - MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), - - MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), - MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), - - MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), - MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), - - MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), - MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), - - MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), - MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), - - MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), - MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), - - MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), - MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), - MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), - MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), - MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), - MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), - MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), - MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), - MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), - MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), - MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), - MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), - MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), - MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), - MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), - MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), - MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), - MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), - MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), - MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), - MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), - MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), - MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), - MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), - MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), - MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), - MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), - MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), - MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), - MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), - MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), - MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), - MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), - MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), - MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), - MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), - MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), - MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), - MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), - MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), - MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), - MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), - MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), - MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), - MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), - - MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), - MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), - MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), - MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), - MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), - - MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), - MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), - MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), - - MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), - MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), - MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), - - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0), - - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), - - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), - - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), - MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), - MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), - - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0), - - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), - - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), - - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0), - MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), - MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), - MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), - - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), - MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), - MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), - MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), - - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), - MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), - MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), - MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0), - - MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), - - MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), - MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), - MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), - MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), - MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), - MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), - MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), - MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), - MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), - MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), - MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), - MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), - MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), - MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), - MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), - MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), - MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), - MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), - - MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), - MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), - MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), - MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), - - MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), - MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), - MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), - MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), - MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), - MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), - MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), - MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), - MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), - MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), - MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), - MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), - MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), - MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), - MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), - MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), - MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), - MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), - MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), - MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), - MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), - - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), - MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), - - MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), - MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), - MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), - MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), - MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), - MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), - MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), - MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), - MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), - MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), - MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), - - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), - MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), - MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), - MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), - MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), - MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), - MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), - MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), - MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), - MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), - MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), - MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), - MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), - MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), - MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), - MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), - MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), - MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), - MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), - MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), - MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), - - MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), - MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), - MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), - MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), - - MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), - MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), - MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), - MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), - - MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), - MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), - MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), - - MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), - MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), - MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), - MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), - - MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), - MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), - - MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), - MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), - MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), - MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), - MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), - MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), - MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), - MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), - MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), - MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), - MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), - MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), - MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), - MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), - MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), - MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), - MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), - MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), - MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), - MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), - MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), - MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), - MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), - MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), - MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), - MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), - MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), - MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), - MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), - MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), - MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), - MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), - MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), - MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), - MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), - MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), - MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), - MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), - MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), - MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), - MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), - MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), - MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), - MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), - MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), - - MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), - MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), - MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), - MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), - MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), - MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), - MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), - MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), - MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), - MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), - MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), - - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), - - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), - - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), - - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), - MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), - MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), - MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), - MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), - MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), - MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), - MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), - MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), - MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), - MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), - MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), -}; - -static inline void imx7_setup_pad(iomux_v3_cfg_t pad) -{ - void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); - unsigned int flags = 0; - uint32_t mode = IOMUX_MODE(pad); - - if (mode & IOMUX_CONFIG_LPSR) { - mode &= ~IOMUX_CONFIG_LPSR; - flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; - } - - iomux_v3_setup_pad(iomux, flags, - IOMUX_CTRL_OFS(pad), - IOMUX_PAD_CTRL_OFS(pad), - IOMUX_SEL_INPUT_OFS(pad), - mode, - IOMUX_PAD_CTRL(pad), - IOMUX_SEL_INPUT(pad)); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8m.h b/arch/arm/mach-imx/include/mach/iomux-mx8m.h deleted file mode 100644 index de6675064a..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx8m.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __MACH_IOMUX_IMX8M_H__ -#define __MACH_IOMUX_IMX8M_H__ - -#include <mach/iomux-v3.h> - -#define PAD_CTL_DSE_3P3V_45_OHM 0b110 - -static inline void imx8m_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) -{ - unsigned int flags = 0; - uint32_t mode = IOMUX_MODE(pad); - - if (mode & IOMUX_CONFIG_LPSR) { - mode &= ~IOMUX_CONFIG_LPSR; - flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; - } - - iomux_v3_setup_pad(iomux, flags, - IOMUX_CTRL_OFS(pad), - IOMUX_PAD_CTRL_OFS(pad), - IOMUX_SEL_INPUT_OFS(pad), - mode, - IOMUX_PAD_CTRL(pad), - IOMUX_SEL_INPUT(pad)); -} - -#endif /* __MACH_IOMUX_IMX8MQ_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h deleted file mode 100644 index f91671865d..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h +++ /dev/null @@ -1,701 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __ASM_ARCH_IMX8MM_PINS_H__ -#define __ASM_ARCH_IMX8MM_PINS_H__ - -#include <mach/iomux-v3.h> -#include <mach/imx8mm-regs.h> -#include <mach/iomux-mx8m.h> - -enum { - IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), - IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), - IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), - IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), - IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), - IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), - IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), - IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), - IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), - IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), - IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), - IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), - IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), - IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), - IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), - IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), - IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), - IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), - IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), - IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), - IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), - IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), - IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), - IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), - IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), - IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), - IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), - IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), - IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), - IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), - IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), - IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), - IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), - IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), - IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), - IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), - IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), - IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), - IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), - IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), - IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), - IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), - IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), - IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), - IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), - IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), - IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), - IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), - IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), - IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), - IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), - IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), - IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), - IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), - IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), - IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), - IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), - IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), - IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), - IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), - IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), - IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), - IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), - IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), - IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), - IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), - IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), - IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), - IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), - IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), - IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), - IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), - IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), - IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), - IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), - IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), - IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), - IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), - IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), - IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), - IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), - IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), - IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), - IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), - IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), - IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), - IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), - IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; - -static inline void imx8mm_setup_pad(iomux_v3_cfg_t pad) -{ - void __iomem *iomux = IOMEM(MX8MM_IOMUXC_BASE_ADDR); - - imx8m_setup_pad(iomux, pad); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h deleted file mode 100644 index d397e975c0..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h +++ /dev/null @@ -1,633 +0,0 @@ -/* - * Copyright (C) 2017 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_IOMUX_IMX8MQ_H__ -#define __MACH_IOMUX_IMX8MQ_H__ - -#include <mach/iomux-v3.h> -#include <mach/iomux-mx8m.h> -#include <mach/imx8mq-regs.h> - -enum { - IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), - - IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), - IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), - IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), - IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), - IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), - IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), - IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), - IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), - IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), - IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), - IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), - IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), - IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), - IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), - IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), - IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), - IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), - IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), - IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), - IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), - IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), - IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), - IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), - IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), - IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), - IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), - IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), - IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), - IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), - IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), - IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), - IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), - IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), - IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), - IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), - IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), - IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), - IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), - IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; - -static inline void imx8mq_setup_pad(iomux_v3_cfg_t pad) -{ - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); - - imx8m_setup_pad(iomux, pad); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-v1.h b/arch/arm/mach-imx/include/mach/iomux-v1.h deleted file mode 100644 index 8f75933e39..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-v1.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef __MACH_IOMUX_V1_H__ -#define __MACH_IOMUX_V1_H__ - -#include <linux/compiler.h> - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define GPIO_GIUS (1 << 16) - -void imx_iomuxv1_init(void __iomem *base); -void imx_gpio_mode(void __iomem *base, int gpio_mode); - -#include <mach/imx1-regs.h> -#include <mach/imx21-regs.h> -#include <mach/imx27-regs.h> - -static inline void imx1_gpio_mode(int gpio_mode) -{ - imx_gpio_mode(IOMEM(MX1_GPIO1_BASE_ADDR), gpio_mode); -} - -static inline void imx21_gpio_mode(int gpio_mode) -{ - imx_gpio_mode(IOMEM(MX21_GPIO1_BASE_ADDR), gpio_mode); -} - -static inline void imx27_gpio_mode(int gpio_mode) -{ - imx_gpio_mode(IOMEM(MX27_GPIO1_BASE_ADDR), gpio_mode); -} - -#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h deleted file mode 100644 index d1a72a2cf5..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-v3.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ - -#include <io.h> -#include <linux/bitfield.h> - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) -*/ - -typedef u64 iomux_v3_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) -#define MUX_PAD_CTRL_OFS_SHIFT 12 -#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 24 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 36 -#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) -#define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) -#define MUX_SEL_INPUT_SHIFT 59 -#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) - -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ - _sel_input, _pad_ctrl) \ - (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define IOMUX_PAD_FIELD(name, pad) (((pad) & name##_MASK) >> name##_SHIFT) -#define IOMUX_CTRL_OFS(pad) IOMUX_PAD_FIELD(MUX_CTRL_OFS, pad) -#define IOMUX_MODE(pad) IOMUX_PAD_FIELD(MUX_MODE, pad) -#define IOMUX_SEL_INPUT_OFS(pad) IOMUX_PAD_FIELD(MUX_SEL_INPUT_OFS, pad) -#define IOMUX_SEL_INPUT(pad) IOMUX_PAD_FIELD(MUX_SEL_INPUT, pad) -#define IOMUX_PAD_CTRL_OFS(pad) IOMUX_PAD_FIELD(MUX_PAD_CTRL_OFS, pad) -#define IOMUX_PAD_CTRL(pad) IOMUX_PAD_FIELD(MUX_PAD_CTRL, pad) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) -/* - * Use to set PAD control - */ - -#define NO_PAD_CTRL (1 << 17) -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_HYS (1 << 8) - -#define SHARE_CONF_PAD_CTL_DSE GENMASK(2, 0) -#define SHARE_CONF_PAD_CTL_SRE GENMASK(4, 3) - -#define SHARE_CONF_PAD_CTL_ODE BIT(5) -#define SHARE_CONF_PAD_CTL_PUE BIT(6) -#define SHARE_CONF_PAD_CTL_HYS BIT(7) - -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) - -#define PAD_CTL_ODE (1 << 3) - -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) - -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define IOMUX_CONFIG_SION (0x1 << 4) -#define IOMUX_CONFIG_LPSR BIT(5) - -#define SHARE_MUX_CONF_REG 0x1 -#define ZERO_OFFSET_VALID 0x2 -#define IMX7_PINMUX_LPSR 0x4 -#define SHARE_CONF BIT(3) - -static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags, - u32 mux_reg, u32 conf_reg, u32 input_reg, - u32 mux_val, u32 conf_val, u32 input_val) -{ - const bool mux_ok = !!mux_reg || (flags & ZERO_OFFSET_VALID); - const bool conf_ok = !!conf_reg; - const bool input_ok = !!input_reg; - - /* - * The sel_input registers for the LPSR controller pins are in the regular pinmux - * controller, so bend the register offset over to the other controller. - */ - if (flags & IMX7_PINMUX_LPSR) - input_reg += 0x70000; - - if (flags & SHARE_MUX_CONF_REG) { - mux_val |= conf_val; - } else { - if (conf_ok) - writel(conf_val, iomux + conf_reg); - } - - if (mux_ok) - writel(mux_val, iomux + mux_reg); - - if (input_ok) - writel(input_val, iomux + input_reg); -} - -static inline void imx_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) -{ - uint32_t conf_reg, pad_ctrl; - - /* dont write PAD_CTRL when NO_PAD_CTRL is set */ - pad_ctrl = IOMUX_PAD_CTRL(pad); - conf_reg = IOMUX_PAD_CTRL_OFS(pad); - conf_reg = (pad_ctrl & NO_PAD_CTRL) ? 0 : conf_reg, - - iomux_v3_setup_pad(iomux, 0, - IOMUX_CTRL_OFS(pad), - conf_reg, - IOMUX_SEL_INPUT_OFS(pad), - IOMUX_MODE(pad), - pad_ctrl, - IOMUX_SEL_INPUT(pad)); -} - - - -/* - * setups a single pad in the iomuxer - */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); - -/* - * setups mutliple pads - * convenient way to call the above function with tables - */ -int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count); - -#endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/mach-imx/include/mach/iomux-vf610.h b/arch/arm/mach-imx/include/mach/iomux-vf610.h deleted file mode 100644 index b9e509b396..0000000000 --- a/arch/arm/mach-imx/include/mach/iomux-vf610.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_IOMUX_VF610_H__ -#define __MACH_IOMUX_VF610_H__ - -#include <mach/iomux-v3.h> - -#undef PAD_CTL_ODE -#undef PAD_CTL_PKE -#undef PAD_CTL_PUE - -enum { - PAD_MUX_MODE_SHIFT = 20, - PAD_CTL_INPUT_DIFFERENTIAL = 1 << 16, - PAD_CTL_SPEED_MED = 1 << 12, - PAD_CTL_SPEED_HIGH = 3 << 12, - PAD_CTL_SRE = 1 << 11, - PAD_CTL_ODE = 1 << 10, - PAD_CTL_DSE_150ohm = 1 << 6, - PAD_CTL_DSE_50ohm = 3 << 6, - PAD_CTL_DSE_25ohm = 6 << 6, - PAD_CTL_DSE_20ohm = 7 << 6, - PAD_CTL_PKE = 1 << 3, - PAD_CTL_PUE = 1 << 2 | PAD_CTL_PKE, - PAD_CTL_OBE_IBE_ENABLE = 3 << 0, - PAD_CTL_OBE_ENABLE = 1 << 1, - PAD_CTL_IBE_ENABLE = 1 << 0, -}; - -/* These 2 defines are for pins that may not have a mux register, but could - * have a pad setting register, and vice-versa. */ -#define __NA_ 0x00 - -/* Pad control groupings */ -enum { - - VF610_UART_PAD_CTRL = PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE, - VF610_SDHC_PAD_CTRL = PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE, - VF610_ENET_PAD_CTRL = PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE, - VF610_DDR_PAD_CTRL = PAD_CTL_DSE_25ohm, - VF610_DDR_PAD_CTRL_1 = PAD_CTL_DSE_25ohm | PAD_CTL_INPUT_DIFFERENTIAL, - VF610_I2C_PAD_CTRL = PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | PAD_CTL_OBE_IBE_ENABLE, - VF610_NFC_IO_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_OBE_IBE_ENABLE, - VF610_NFC_CN_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE, - VF610_NFC_RB_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE, - VF610_QSPI_PAD_CTRL = PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE, - VF610_GPIO_PAD_CTRL = PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | PAD_CTL_IBE_ENABLE, - VF610_DSPI_PAD_CTRL = PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH, - VF610_DSPI_SIN_PAD_CTRL = PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH, -}; - -enum { - VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), - VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD19__GPIO_75 = IOMUX_PAD(0x012C, 0x012C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD18__GPIO_76 = IOMUX_PAD(0x0120, 0x0130, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD17__GPIO_77 = IOMUX_PAD(0x0134, 0x0134, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD16__GPIO_78 = IOMUX_PAD(0x0138, 0x0138, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), - VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), -}; - -#define PINCTRL_VF610_MUX_SHIFT 20 - - -static inline void vf610_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) -{ - iomux_v3_setup_pad(iomux, SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, - IOMUX_CTRL_OFS(pad), - IOMUX_PAD_CTRL_OFS(pad), - IOMUX_SEL_INPUT_OFS(pad), - IOMUX_MODE(pad) << PINCTRL_VF610_MUX_SHIFT, - IOMUX_PAD_CTRL(pad), - IOMUX_SEL_INPUT(pad)); -} - - -#endif /* __IOMUX_VF610_H__ */ diff --git a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h deleted file mode 100644 index aec50dbf8a..0000000000 --- a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef __MACH_IMX_OCOTP_FUSEMAP_H -#define __MACH_IMX_OCOTP_FUSEMAP_H - -#include <mach/ocotp.h> - -#define OCOTP_TESTER_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(0) | OCOTP_WIDTH(2)) -#define OCOTP_BOOT_CFG_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(2) | OCOTP_WIDTH(2)) -#define OCOTP_MEM_TRIM_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(4) | OCOTP_WIDTH(2)) -#define OCOTP_SJC_RESP_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(6) | OCOTP_WIDTH(1)) -#define OCOTP_MAC_ADDR_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(8) | OCOTP_WIDTH(2)) -#define OCOTP_GP1_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(10) | OCOTP_WIDTH(2)) -#define OCOTP_GP2_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(12) | OCOTP_WIDTH(2)) -#define OCOTP_SRK_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(14) | OCOTP_WIDTH(1)) -#define OCOTP_ANALOG_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(18) | OCOTP_WIDTH(2)) -#define OCOTP_MISC_CONF_LOCK (OCOTP_WORD(0x400) | OCOTP_BIT(22) | OCOTP_WIDTH(1)) - -/* 0 <= n <= 1 */ -#define OCOTP_UNIQUE_ID(n) (OCOTP_WORD(0x410 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_NUM_CORES (OCOTP_WORD(0x430) | OCOTP_BIT(20) | OCOTP_WIDTH(2)) -#define OCOTP_MLB_DISABLE (OCOTP_WORD(0x430) | OCOTP_BIT(26) | OCOTP_WIDTH(1)) - -#define OCOTP_BOOT_CFG1 (OCOTP_WORD(0x450) | OCOTP_BIT(0) | OCOTP_WIDTH(8)) -#define OCOTP_BOOT_CFG2 (OCOTP_WORD(0x450) | OCOTP_BIT(8) | OCOTP_WIDTH(8)) -#define OCOTP_BOOT_CFG3 (OCOTP_WORD(0x450) | OCOTP_BIT(16) | OCOTP_WIDTH(8)) -#define OCOTP_BOOT_CFG4 (OCOTP_WORD(0x450) | OCOTP_BIT(24) | OCOTP_WIDTH(8)) -/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ -#define OCOTP_SDP_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(0) | OCOTP_WIDTH(1)) -#define OCOTP_SEC_CONFIG_1 (OCOTP_WORD(0x460) | OCOTP_BIT(1) | OCOTP_WIDTH(1)) -/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ -#define OCOTP_SDP_READ_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(2) | OCOTP_WIDTH(1)) -#define OCOTP_DIR_BT_DIS (OCOTP_WORD(0x460) | OCOTP_BIT(3) | OCOTP_WIDTH(1)) -#define OCOTP_BT_FUSE_SEL (OCOTP_WORD(0x460) | OCOTP_BIT(4) | OCOTP_WIDTH(1)) -#define OCOTP_SJC_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(20) | OCOTP_WIDTH(1)) -#define OCOTP_WDOG_ENABLE (OCOTP_WORD(0x460) | OCOTP_BIT(21) | OCOTP_WIDTH(1)) -#define OCOTP_JTAG_SMODE (OCOTP_WORD(0x460) | OCOTP_BIT(22) | OCOTP_WIDTH(2)) -#define OCOTP_KTE (OCOTP_WORD(0x460) | OCOTP_BIT(26) | OCOTP_WIDTH(1)) -#define OCOTP_JTAG_HEO (OCOTP_WORD(0x460) | OCOTP_BIT(27) | OCOTP_WIDTH(1)) -/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ -#define OCOTP_FORCE_INTERNAL_BOOT (OCOTP_WORD(0x460) | OCOTP_BIT(31) | OCOTP_WIDTH(1)) -#define OCOTP_NAND_READ_CMD_CODE1 (OCOTP_WORD(0x470) | OCOTP_BIT(0) | OCOTP_WIDTH(8)) -#define OCOTP_NAND_READ_CMD_CODE2 (OCOTP_WORD(0x470) | OCOTP_BIT(8) | OCOTP_WIDTH(8)) -#define OCOTP_TEMP_SENSE (OCOTP_WORD(0x4e0) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_USB_VID (OCOTP_WORD(0x4f0) | OCOTP_BIT(0) | OCOTP_WIDTH(16)) -#define OCOTP_USB_PID (OCOTP_WORD(0x4f0) | OCOTP_BIT(16) | OCOTP_WIDTH(16)) -/* 0 <= n <= 7 */ -#define OCOTP_SRK_HASH(n) (OCOTP_WORD(0x580 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_SJC_RESP_31_0 (OCOTP_WORD(0x600) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_SJC_RESP_55_32 (OCOTP_WORD(0x610) | OCOTP_BIT(0) | OCOTP_WIDTH(24)) -#define OCOTP_MAC_ADDR_31_0 (OCOTP_WORD(0x620) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_MAC_ADDR_47_32 (OCOTP_WORD(0x630) | OCOTP_BIT(0) | OCOTP_WIDTH(16)) -#define OCOTP_GP1 (OCOTP_WORD(0x660) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_GP2 (OCOTP_WORD(0x670) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define OCOTP_PAD_SETTINGS (OCOTP_WORD(0x6d0) | OCOTP_BIT(0) | OCOTP_WIDTH(6)) - -#endif /* __MACH_IMX_OCOTP_FUSEMAP_H */ diff --git a/arch/arm/mach-imx/include/mach/ocotp.h b/arch/arm/mach-imx/include/mach/ocotp.h deleted file mode 100644 index 7ba5da156b..0000000000 --- a/arch/arm/mach-imx/include/mach/ocotp.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef __MACH_IMX_OCOTP_H -#define __MACH_IMX_OCOTP_H - -#include <linux/bitfield.h> -#include <linux/types.h> - -#define OCOTP_SHADOW_OFFSET 0x400 -#define OCOTP_SHADOW_SPACING 0x10 - -/* - * Trivial shadow register offset -> ocotp register index. - * - * NOTE: Doesn't handle special mapping quirks. See - * imx6q_addr_to_offset and vf610_addr_to_offset for more details. Use - * with care - */ -#define OCOTP_OFFSET_TO_INDEX(o) \ - (((o) - OCOTP_SHADOW_OFFSET) / OCOTP_SHADOW_SPACING) - -#define OCOTP_WORD_MASK GENMASK( 7, 0) -#define OCOTP_BIT_MASK GENMASK(12, 8) -#define OCOTP_WIDTH_MASK GENMASK(17, 13) - -#define OCOTP_WORD(n) FIELD_PREP(OCOTP_WORD_MASK, \ - OCOTP_OFFSET_TO_INDEX(n)) -#define OCOTP_BIT(n) FIELD_PREP(OCOTP_BIT_MASK, n) -#define OCOTP_WIDTH(n) FIELD_PREP(OCOTP_WIDTH_MASK, (n) - 1) - -#define OCOTP_OFFSET_CFG0 0x410 -#define OCOTP_OFFSET_CFG1 0x420 - - -int imx_ocotp_read_field(uint32_t field, unsigned *value); -int imx_ocotp_write_field(uint32_t field, unsigned value); -int imx_ocotp_permanent_write(int enable); -bool imx_ocotp_sense_enable(bool enable); - -static inline u64 imx_ocotp_read_uid(void __iomem *ocotp) -{ - u64 uid; - - uid = readl(ocotp + OCOTP_OFFSET_CFG0); - uid <<= 32; - uid |= readl(ocotp + OCOTP_OFFSET_CFG1); - - return uid; -} - -#endif /* __MACH_IMX_OCOTP_H */ diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h deleted file mode 100644 index 91a8171896..0000000000 --- a/arch/arm/mach-imx/include/mach/reset-reason.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __MACH_RESET_REASON_H__ -#define __MACH_RESET_REASON_H__ - -#include <reset_source.h> - -#define IMX_SRC_SRSR_IPP_RESET BIT(0) -#define IMX_SRC_SRSR_CSU_RESET BIT(2) -#define IMX_SRC_SRSR_IPP_USER_RESET BIT(3) -#define IMX_SRC_SRSR_WDOG1_RESET BIT(4) -#define IMX_SRC_SRSR_JTAG_RESET BIT(5) -#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6) -#define IMX_SRC_SRSR_WDOG3_RESET BIT(7) -#define IMX_SRC_SRSR_WDOG4_RESET BIT(8) -#define IMX_SRC_SRSR_TEMPSENSE_RESET BIT(9) -#define IMX_SRC_SRSR_WARM_BOOT BIT(16) - -#define IMX_SRC_SRSR 0x008 -#define IMX7_SRC_SRSR 0x05c - -#define VF610_SRC_SRSR_SW_RST BIT(18) -#define VF610_SRC_SRSR_RESETB BIT(7) -#define VF610_SRC_SRSR_JTAG_RST BIT(5) -#define VF610_SRC_SRSR_WDOG_M4 BIT(4) -#define VF610_SRC_SRSR_WDOG_A5 BIT(3) -#define VF610_SRC_SRSR_POR_RST BIT(0) - -struct imx_reset_reason { - uint32_t mask; - enum reset_src_type type; - int instance; -}; - -void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *); - -extern const struct imx_reset_reason imx_reset_reasons[]; -extern const struct imx_reset_reason imx7_reset_reasons[]; - -#endif /* __MACH_RESET_REASON_H__ */ diff --git a/arch/arm/mach-imx/include/mach/revision.h b/arch/arm/mach-imx/include/mach/revision.h deleted file mode 100644 index d9495d967f..0000000000 --- a/arch/arm/mach-imx/include/mach/revision.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __MACH_REVISION_H__ -#define __MACH_REVISION_H__ - -/* silicon revisions */ -#define IMX_CHIP_REV_1_0 0x10 -#define IMX_CHIP_REV_1_1 0x11 -#define IMX_CHIP_REV_1_2 0x12 -#define IMX_CHIP_REV_1_3 0x13 -#define IMX_CHIP_REV_1_4 0x14 -#define IMX_CHIP_REV_1_5 0x15 -#define IMX_CHIP_REV_1_6 0x16 -#define IMX_CHIP_REV_2_0 0x20 -#define IMX_CHIP_REV_2_1 0x21 -#define IMX_CHIP_REV_2_2 0x22 -#define IMX_CHIP_REV_2_3 0x23 -#define IMX_CHIP_REV_3_0 0x30 -#define IMX_CHIP_REV_3_1 0x31 -#define IMX_CHIP_REV_3_2 0x32 -#define IMX_CHIP_REV_UNKNOWN 0xff - -int imx_silicon_revision(void); - -void imx_set_silicon_revision(const char *soc, int revision); - -#endif /* __MACH_REVISION_H__ */ diff --git a/arch/arm/mach-imx/include/mach/spi.h b/arch/arm/mach-imx/include/mach/spi.h deleted file mode 100644 index 08be445e8e..0000000000 --- a/arch/arm/mach-imx/include/mach/spi.h +++ /dev/null @@ -1,27 +0,0 @@ - -#ifndef __MACH_SPI_H_ -#define __MACH_SPI_H_ - -/* - * struct spi_imx_master - device.platform_data for SPI controller devices. - * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio - * pins, numbers < 0 mean internal CSPI chipselects according - * to MXC_SPI_CS(). Normally you want to use gpio based chip - * selects as the CSPI module tries to be intelligent about - * when to assert the chipselect: The CSPI module deasserts the - * chipselect once it runs out of input data. The other problem - * is that it is not possible to mix between high active and low - * active chipselects on one single bus using the internal - * chipselects. Unfortunately Freescale decided to put some - * chipselects on dedicated pins which are not usable as gpios, - * so we have to support the internal chipselects. - * @num_chipselect: ARRAY_SIZE(chipselect) - */ -struct spi_imx_master { - int *chipselect; - int num_chipselect; -}; - -#define MXC_SPI_CS(no) ((no) - 32) - -#endif /* __MACH_SPI_H_*/ diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h deleted file mode 100644 index 3209bf9095..0000000000 --- a/arch/arm/mach-imx/include/mach/usb.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __MACH_USB_H_ -#define __MACH_USB_H_ - -/* configuration bits for i.MX25 and i.MX35 */ -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) - -#define USBCMD 0x140 -#define USB_CMD_RESET 0x00000002 - -/* - * imx_reset_otg_controller - reset the USB OTG controller - * @base: The base address of the controller - * - * When booting from USB the ROM just leaves the controller enabled. This can - * have bad side effects when for example we change PLL frequencies. In this - * case it is seen that the hub the board is connected to gets confused and USB - * is no longer working properly on the remote host. This function resets the - * OTG controller. It should be called before the clocks the controller hangs on - * is fiddled with. - */ -static inline void imx_reset_otg_controller(void __iomem *base) -{ - u32 r; - - r = readl(base + USBCMD); - r |= USB_CMD_RESET; - writel(r, base + USBCMD); -} - -#endif /* __MACH_USB_H_*/ diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h deleted file mode 100644 index 33c1aaddf3..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * VFxxx DDRMC register addresses definitions for use in DCD - * - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -#define DDRMC_CR00 0x400ae000 -#define DDRMC_CR02 0x400ae008 -#define DDRMC_CR10 0x400ae028 -#define DDRMC_CR11 0x400ae02c -#define DDRMC_CR12 0x400ae030 -#define DDRMC_CR13 0x400ae034 -#define DDRMC_CR14 0x400ae038 -#define DDRMC_CR16 0x400ae040 -#define DDRMC_CR17 0x400ae044 -#define DDRMC_CR18 0x400ae048 -#define DDRMC_CR20 0x400ae050 -#define DDRMC_CR21 0x400ae054 -#define DDRMC_CR22 0x400ae058 -#define DDRMC_CR23 0x400ae05c -#define DDRMC_CR24 0x400ae060 -#define DDRMC_CR25 0x400ae064 -#define DDRMC_CR26 0x400ae068 -#define DDRMC_CR28 0x400ae070 -#define DDRMC_CR29 0x400ae074 -#define DDRMC_CR30 0x400ae078 -#define DDRMC_CR31 0x400ae07c -#define DDRMC_CR33 0x400ae084 -#define DDRMC_CR34 0x400ae088 -#define DDRMC_CR38 0x400ae098 -#define DDRMC_CR39 0x400ae09c -#define DDRMC_CR41 0x400ae0a4 -#define DDRMC_CR48 0x400ae0c0 -#define DDRMC_CR49 0x400ae0c4 -#define DDRMC_CR51 0x400ae0cc -#define DDRMC_CR57 0x400ae0e4 -#define DDRMC_CR66 0x400ae108 -#define DDRMC_CR67 0x400ae10c -#define DDRMC_CR69 0x400ae114 -#define DDRMC_CR70 0x400ae118 -#define DDRMC_CR72 0x400ae120 -#define DDRMC_CR73 0x400ae124 -#define DDRMC_CR74 0x400ae128 -#define DDRMC_CR75 0x400ae12c -#define DDRMC_CR76 0x400ae130 -#define DDRMC_CR77 0x400ae134 -#define DDRMC_CR78 0x400ae138 -#define DDRMC_CR79 0x400ae13c -#define DDRMC_CR82 0x400ae148 -#define DDRMC_CR87 0x400ae15c -#define DDRMC_CR88 0x400ae160 -#define DDRMC_CR89 0x400ae164 -#define DDRMC_CR91 0x400ae16c -#define DDRMC_CR96 0x400ae180 -#define DDRMC_CR97 0x400ae184 -#define DDRMC_CR98 0x400ae188 -#define DDRMC_CR99 0x400ae18c -#define DDRMC_CR102 0x400ae198 -#define DDRMC_CR105 0x400ae1a4 -#define DDRMC_CR106 0x400ae1a8 -#define DDRMC_CR110 0x400ae1b8 -#define DDRMC_CR114 0x400ae1c8 -#define DDRMC_CR115 0x400ae1cc -#define DDRMC_CR117 0x400ae1d4 -#define DDRMC_CR118 0x400ae1d8 -#define DDRMC_CR120 0x400ae1e0 -#define DDRMC_CR121 0x400ae1e4 -#define DDRMC_CR122 0x400ae1e8 -#define DDRMC_CR123 0x400ae1ec -#define DDRMC_CR124 0x400ae1f0 -#define DDRMC_CR126 0x400ae1f8 -#define DDRMC_CR132 0x400ae210 -#define DDRMC_CR137 0x400ae224 -#define DDRMC_CR138 0x400ae228 -#define DDRMC_CR139 0x400ae22c -#define DDRMC_CR140 0x400ae230 -#define DDRMC_CR143 0x400ae23c -#define DDRMC_CR144 0x400ae240 -#define DDRMC_CR145 0x400ae244 -#define DDRMC_CR146 0x400ae248 -#define DDRMC_CR147 0x400ae24c -#define DDRMC_CR148 0x400ae250 -#define DDRMC_CR151 0x400ae25c -#define DDRMC_CR154 0x400ae268 -#define DDRMC_CR155 0x400ae26c -#define DDRMC_CR158 0x400ae278 -#define DDRMC_CR161 0x400ae284 - -#define DDRMC_CR00_DRAM_CLASS_DDR3 0x00000600 -#define DDRMC_CR00_DRAM_CLASS_DDR3_START 0x00000601 - -#define DDRMC_PHY00 0x400ae400 -#define DDRMC_PHY01 0x400ae404 -#define DDRMC_PHY02 0x400ae408 -#define DDRMC_PHY03 0x400ae40c -#define DDRMC_PHY04 0x400ae410 -#define DDRMC_PHY16 0x400ae440 -#define DDRMC_PHY17 0x400ae444 -#define DDRMC_PHY18 0x400ae448 -#define DDRMC_PHY19 0x400ae44c -#define DDRMC_PHY20 0x400ae450 -#define DDRMC_PHY32 0x400ae480 -#define DDRMC_PHY34 0x400ae488 -#define DDRMC_PHY35 0x400ae48c -#define DDRMC_PHY36 0x400ae490 -#define DDRMC_PHY49 0x400ae4c4 -#define DDRMC_PHY50 0x400ae4c8 -#define DDRMC_PHY52 0x400ae4d0 diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h deleted file mode 100644 index 07feb036e5..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __MACH_DDRMC_H -#define __MACH_DDRMC_H - -#include <mach/vf610-regs.h> - - -#define DDRMC_CR(x) ((x) * 4) - -#define DDRMC_CR01_MAX_COL_REG(reg) (((reg) >> 8) & 0b01111) -#define DDRMC_CR01_MAX_ROW_REG(reg) (((reg) >> 0) & 0b11111) -#define DDRMC_CR73_COL_DIFF(reg) (((reg) >> 16) & 0b00111) -#define DDRMC_CR73_ROW_DIFF(reg) (((reg) >> 8) & 0b00011) -#define DDRMC_CR73_BANK_DIFF(reg) (((reg) >> 0) & 0b00011) - -#define DDRMC_CR78_REDUC BIT(8) - - -#endif /* __MACH_MMDC_H */ diff --git a/arch/arm/mach-imx/include/mach/vf610-fusemap.h b/arch/arm/mach-imx/include/mach/vf610-fusemap.h deleted file mode 100644 index a56faf10cc..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610-fusemap.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __MACH_VF610_OCOTP_H -#define __MACH_VF610_OCOTP_H - -#include <mach/ocotp-fusemap.h> - -#define VF610_OCOTP_CPU_BUS_FRQ OCOTP_WORD(0x430) | OCOTP_BIT(22) | OCOTP_WIDTH(1) -#define VF610_OCOTP_OVG_DISABLE OCOTP_WORD(0x430) | OCOTP_BIT(30) | OCOTP_WIDTH(1) -#define VF610_OCOTP_SEC_CONFIG_0 OCOTP_WORD(0x440) | OCOTP_BIT(1) | OCOTP_WIDTH(1) -#define VF610_OCOTP_SPEED_GRADING OCOTP_WORD(0x440) | OCOTP_BIT(18) | OCOTP_WIDTH(4) -#define VF610_OCOTP_MAC_ADDR0_31_0 OCOTP_MAC_ADDR_31_0 -#define VF610_OCOTP_MAC_ADDR0_47_32 OCOTP_MAC_ADDR_47_32 -#define VF610_OCOTP_MAC_ADDR1_31_0 (OCOTP_WORD(0x640) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) -#define VF610_OCOTP_MAC_ADDR1_47_32 (OCOTP_WORD(0x650) | OCOTP_BIT(0) | OCOTP_WIDTH(16)) - -#endif diff --git a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h deleted file mode 100644 index c85f0b74b9..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * VFxxx IOMUX register addresses definitions for use in DCD - * - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -#define VF610_PAD_DDR_RESETB 0x4004821c -#define VF610_PAD_DDR_A15__DDR_A_15 0x40048220 -#define VF610_PAD_DDR_A14__DDR_A_14 0x40048224 -#define VF610_PAD_DDR_A13__DDR_A_13 0x40048228 -#define VF610_PAD_DDR_A12__DDR_A_12 0x4004822c -#define VF610_PAD_DDR_A11__DDR_A_11 0x40048230 -#define VF610_PAD_DDR_A10__DDR_A_10 0x40048234 -#define VF610_PAD_DDR_A9__DDR_A_9 0x40048238 -#define VF610_PAD_DDR_A8__DDR_A_8 0x4004823c -#define VF610_PAD_DDR_A7__DDR_A_7 0x40048240 -#define VF610_PAD_DDR_A6__DDR_A_6 0x40048244 -#define VF610_PAD_DDR_A5__DDR_A_5 0x40048248 -#define VF610_PAD_DDR_A4__DDR_A_4 0x4004824c -#define VF610_PAD_DDR_A3__DDR_A_3 0x40048250 -#define VF610_PAD_DDR_A2__DDR_A_2 0x40048254 -#define VF610_PAD_DDR_A1__DDR_A_1 0x40048258 -#define VF610_PAD_DDR_A0__DDR_A_0 0x4004825c -#define VF610_PAD_DDR_BA2__DDR_BA_2 0x40048260 -#define VF610_PAD_DDR_BA1__DDR_BA_1 0x40048264 -#define VF610_PAD_DDR_BA0__DDR_BA_0 0x40048268 -#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x4004826c -#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x40048270 -#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x40048274 -#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x40048278 -#define VF610_PAD_DDR_D15__DDR_D_15 0x4004827c -#define VF610_PAD_DDR_D14__DDR_D_14 0x40048280 -#define VF610_PAD_DDR_D13__DDR_D_13 0x40048284 -#define VF610_PAD_DDR_D12__DDR_D_12 0x40048288 -#define VF610_PAD_DDR_D11__DDR_D_11 0x4004828c -#define VF610_PAD_DDR_D10__DDR_D_10 0x40048290 -#define VF610_PAD_DDR_D9__DDR_D_9 0x40048294 -#define VF610_PAD_DDR_D8__DDR_D_8 0x40048298 -#define VF610_PAD_DDR_D7__DDR_D_7 0x4004829c -#define VF610_PAD_DDR_D6__DDR_D_6 0x400482a0 -#define VF610_PAD_DDR_D5__DDR_D_5 0x400482a4 -#define VF610_PAD_DDR_D4__DDR_D_4 0x400482a8 -#define VF610_PAD_DDR_D3__DDR_D_3 0x400482ac -#define VF610_PAD_DDR_D2__DDR_D_2 0x400482b0 -#define VF610_PAD_DDR_D1__DDR_D_1 0x400482b4 -#define VF610_PAD_DDR_D0__DDR_D_0 0x400482b8 -#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x400482bc -#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x400482c0 -#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x400482c4 -#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x400482c8 -#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x400482cc -#define VF610_PAD_DDR_WE__DDR_WE_B 0x400482d0 -#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x400482d4 -#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x400482d8 - -#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x400482dc -#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 0x400482e0 diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h deleted file mode 100644 index 416b457aff..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610-regs.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_VF610_REGS_H__ -#define __MACH_VF610_REGS_H__ - -#define VF610_IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define VF610_IRAM_SIZE 0x00080000 /* 512 KB */ - -#define VF610_AIPS0_BASE_ADDR 0x40000000 -#define VF610_AIPS1_BASE_ADDR 0x40080000 - -#define VF610_RAM_BASE_ADDR 0x80000000 - -/* AIPS 0 */ -#define VF610_MSCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001000) -#define VF610_MSCM_IR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001800) -#define VF610_CA5SCU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00002000) -#define VF610_CA5_INTD_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00003000) -#define VF610_CA5_L2C_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00006000) -#define VF610_NIC0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00008000) -#define VF610_NIC1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00009000) -#define VF610_NIC2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000A000) -#define VF610_NIC3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000B000) -#define VF610_NIC4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000C000) -#define VF610_NIC5_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000D000) -#define VF610_NIC6_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000E000) -#define VF610_NIC7_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0000F000) -#define VF610_AHBTZASC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00010000) -#define VF610_TZASC_SYS0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00011000) -#define VF610_TZASC_SYS1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00012000) -#define VF610_TZASC_GFX_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00013000) -#define VF610_TZASC_DDR0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00014000) -#define VF610_TZASC_DDR1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00015000) -#define VF610_CSU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00017000) -#define VF610_DMA0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00018000) -#define VF610_DMA0_TCD_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00019000) -#define VF610_SEMA4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0001D000) -#define VF610_FB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0001E000) -#define VF610_DMA_MUX0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00024000) -#define VF610_UART1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00027000) -#define VF610_UART2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00028000) -#define VF610_UART3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00029000) -#define VF610_UART4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002A000) -#define VF610_SPI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002C000) -#define VF610_SPI1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002D000) -#define VF610_SAI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0002F000) -#define VF610_SAI1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00030000) -#define VF610_SAI2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00031000) -#define VF610_SAI3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00032000) -#define VF610_CRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00033000) -#define VF610_USBC0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00034000) -#define VF610_PDB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00036000) -#define VF610_PIT_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00037000) -#define VF610_FTM0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00038000) -#define VF610_FTM1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00039000) -#define VF610_ADC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003B000) -#define VF610_TCON0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003D000) -#define VF610_WDOG1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0003E000) -#define VF610_LPTMR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00040000) -#define VF610_RLE_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00042000) -#define VF610_MLB_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00043000) -#define VF610_QSPI0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00044000) -#define VF610_IOMUXC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00048000) -#define VF610_ANADIG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050000) -#define VF610_USB_PHY0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050800) -#define VF610_USB_PHY1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00050C00) -#define VF610_SCSC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00052000) -#define VF610_ASRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00060000) -#define VF610_SPDIF_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00061000) -#define VF610_ESAI_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00062000) -#define VF610_ESAI_FIFO_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00063000) -#define VF610_WDOG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00065000) -#define VF610_I2C1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00066000) -#define VF610_I2C2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00067000) -#define VF610_I2C3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000E6000) -#define VF610_I2C4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000E7000) -#define VF610_WKUP_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006A000) -#define VF610_CCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006B000) -#define VF610_GPC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006C000) -#define VF610_VREG_DIG_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006D000) -#define VF610_SRC_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006E000) -#define VF610_CMU_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x0006F000) -#define VF610_GPIO0_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF000) -#define VF610_GPIO1_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF040) -#define VF610_GPIO2_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF080) -#define VF610_GPIO3_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF0C0) -#define VF610_GPIO4_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x000FF100) - -/* AIPS 1 */ -#define VF610_OCOTP_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00025000) -#define VF610_DDR_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x0002E000) -#define VF610_ESDHC0_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00031000) -#define VF610_ESDHC1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00032000) -#define VF610_USBC1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00034000) -#define VF610_ENET_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00050000) -#define VF610_ENET1_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00051000) -#define VF610_NFC_BASE_ADDR (VF610_AIPS1_BASE_ADDR + 0x00060000) - -#define VF610_QSPI0_AMBA_BASE 0x20000000 - - -/* MSCM interrupt rounter */ -#define VF610_MSCM_IRSPRC(n) (0x880 + 2 * (n)) -#define VF610_MSCM_CPxTYPE 0 -#define VF610_MSCM_IRSPRC_CP0_EN 1 -#define VF610_MSCM_IRSPRC_NUM 112 - -#define VF610_MSCM_CPxCOUNT 0x00c -#define VF610_MSCM_CPxCFG1 0x014 - -#endif diff --git a/arch/arm/mach-imx/include/mach/vf610.h b/arch/arm/mach-imx/include/mach/vf610.h deleted file mode 100644 index 7ac10a7b1e..0000000000 --- a/arch/arm/mach-imx/include/mach/vf610.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __MACH_VF610_H -#define __MACH_VF610_H - -#include <io.h> -#include <mach/generic.h> -#include <mach/vf610-regs.h> -#include <mach/revision.h> - -#define VF610_CPUTYPE_VFx10 0x010 - -#define VF610_CPUTYPE_VF610 0x610 -#define VF610_CPUTYPE_VF600 0x600 -#define VF610_CPUTYPE_VF510 0x510 -#define VF610_CPUTYPE_VF500 0x500 - -#define VF610_ROM_VERSION_OFFSET 0x80 - -static inline int __vf610_cpu_type(void) -{ - void __iomem *mscm = IOMEM(VF610_MSCM_BASE_ADDR); - const u32 cpxcount = readl(mscm + VF610_MSCM_CPxCOUNT); - const u32 cpxcfg1 = readl(mscm + VF610_MSCM_CPxCFG1); - int cpu_type; - - cpu_type = cpxcount ? VF610_CPUTYPE_VF600 : VF610_CPUTYPE_VF500; - - return cpxcfg1 ? cpu_type | VF610_CPUTYPE_VFx10 : cpu_type; -} - -static inline int vf610_cpu_type(void) -{ - if (!cpu_is_vf610()) - return 0; - - return __vf610_cpu_type(); -} - -static inline int vf610_cpu_revision(void) -{ - if (!cpu_is_vf610()) - return IMX_CHIP_REV_UNKNOWN; - - /* - * There doesn't seem to be a documented way of retreiving - * silicon revision on VFxxx cpus, so we just report Mask ROM - * version instead - */ - return readl(VF610_ROM_VERSION_OFFSET) & 0xff; -} - -u64 vf610_uid(void); - -#endif diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h deleted file mode 100644 index 22d9c76d61..0000000000 --- a/arch/arm/mach-imx/include/mach/weim.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __MACH_WEIM_H -#define __MACH_WEIM_H - -#include <linux/types.h> - -void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, - unsigned additional); - -void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower, - unsigned additional); - -void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower, - unsigned additional); - -void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower); - -void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower); - -#endif /* __MACH_WEIM_H */ diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h deleted file mode 100644 index dca05aa5d4..0000000000 --- a/arch/arm/mach-imx/include/mach/xload.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __MACH_XLOAD_H -#define __MACH_XLOAD_H - -int imx53_nand_start_image(void); -int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len); -int imx6_spi_start_image(int instance); -int imx6_esdhc_start_image(int instance); -int imx8m_esdhc_load_image(int instance, bool start); - -int imx_image_size(void); -int piggydata_size(void); - -extern unsigned char input_data[]; -extern unsigned char input_data_end[]; - -#endif /* __MACH_XLOAD_H */ diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c index 7574fe80b2..bbfcfac457 100644 --- a/arch/arm/mach-imx/nand.c +++ b/arch/arm/mach-imx/nand.c @@ -1,23 +1,12 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> -#include <mach/generic.h> -#include <mach/imx21-regs.h> -#include <mach/imx25-regs.h> -#include <mach/imx27-regs.h> -#include <mach/imx35-regs.h> -#include <mach/imx-nand.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx21-regs.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx35-regs.h> +#include <mach/imx/imx-nand.h> #include <io.h> #define RCSR_NFC_FMS (1 << 8) diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c new file mode 100644 index 0000000000..0f1555abad --- /dev/null +++ b/arch/arm/mach-imx/romapi.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "romapi: " fmt + +#include <common.h> +#include <linux/bitfield.h> +#include <soc/imx9/flash_header.h> +#include <asm/sections.h> +#include <mach/imx/romapi.h> +#include <mach/imx/atf.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/xload.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm.h> +#include <zero_page.h> +#include <memory.h> +#include <init.h> +#include <pbl.h> +#include <mmu.h> +#include <bootsource.h> + +#define BOOTROM_INFO_VERSION 0x1 +#define BOOTROM_INFO_BOOT_DEVICE 0x2 +#define BOOTROM_INFO_DEVICE_PAGE_SIZE 0x3 +#define BOOTROM_INFO_OFFSET_IVT 0x4 +#define BOOTROM_INFO_BOOT_STAGE 0x5 +#define BOOTROM_INFO_OFFSET_IMAGE 0x6 + +#define BOOTROM_BOOT_DEVICE_INTERFACE GENMASK(23, 16) +#define BOOTROM_BOOT_DEVICE_INSTANCE GENMASK(15, 8) +#define BOOTROM_BOOT_DEVICE_STATE GENMASK(7, 0) + +static int imx_bootrom_query(struct rom_api *rom_api, uint32_t type, uint32_t *__info) +{ + static uint32_t info; + uint32_t xor = type ^ (uintptr_t)&info; + int ret; + + ret = rom_api->query_boot_infor(type, &info, xor); + if (ret != ROM_API_OKAY) + return -EIO; + + *__info = info; + + return 0; +} + +static int imx_romapi_load_stream(struct rom_api *rom_api, void *adr, size_t size) +{ + while (size) { + size_t chunksize = min(size, (size_t)1024); + int ret; + + ret = rom_api->download_image(adr, 0, chunksize, + (uintptr_t)adr ^ chunksize); + if (ret != ROM_API_OKAY) { + pr_err("Failed to load piggy data (ret = %x)\n", ret); + return -EIO; + } + + adr += chunksize; + size -= chunksize; + } + return 0; +} + +static int imx_romapi_load_seekable(struct rom_api *rom_api, void *adr, uint32_t offset, + size_t size) +{ + int ret; + + size = PAGE_ALIGN(size); + + ret = rom_api->download_image(adr, offset, size, + (uintptr_t)adr ^ offset ^ size); + if (ret != ROM_API_OKAY) { + pr_err("Failed to load piggy data (ret = %x)\n", ret); + return -EIO; + } + + return 0; +} + +/* read piggydata via a bootrom callback and place it behind our copy in SDRAM */ +static int imx_romapi_load_image(struct rom_api *rom_api, void *bl33) +{ + return imx_romapi_load_stream(rom_api, bl33 + barebox_pbl_size, + __image_end - __piggydata_start); +} + +int imx8mp_romapi_load_image(void *bl33) +{ + struct rom_api *rom_api = (void *)0x980; + + OPTIMIZER_HIDE_VAR(rom_api); + + return imx_romapi_load_image(rom_api, bl33); +} + +int imx8mn_romapi_load_image(void *bl33) +{ + return imx8mp_romapi_load_image(bl33); +} + +static int imx_romapi_boot_device(struct rom_api *rom_api) +{ + uint32_t boot_device_type, boot_instance, boot_device; + enum bootsource bootsource = BOOTSOURCE_UNKNOWN; + int ret; + + ret = imx_bootrom_query(rom_api, BOOTROM_INFO_BOOT_DEVICE, &boot_device); + if (ret) + return ret; + + boot_device_type = FIELD_GET(BOOTROM_BOOT_DEVICE_INTERFACE, boot_device); + boot_instance = FIELD_GET(BOOTROM_BOOT_DEVICE_INSTANCE, boot_device); + + switch (boot_device_type) { + case BT_DEV_TYPE_MMC: + case BT_DEV_TYPE_SD: + bootsource = BOOTSOURCE_MMC; + break; + case BT_DEV_TYPE_NAND: + bootsource = BOOTSOURCE_NAND; + break; + case BT_DEV_TYPE_FLEXSPINOR: + case BT_DEV_TYPE_SPI_NOR: + bootsource = BOOTSOURCE_SPI_NOR; + break; + case BT_DEV_TYPE_USB: + bootsource = BOOTSOURCE_USB; + break; + } + + bootsource_set(bootsource, boot_instance); + + return 0; +} + +static int imx_romapi_boot_device_seekable(struct rom_api *rom_api) +{ + uint32_t boot_device, boot_device_type, boot_device_state; + int ret; + bool seekable; + + ret = imx_bootrom_query(rom_api, BOOTROM_INFO_BOOT_DEVICE, &boot_device); + if (ret) + return ret; + + boot_device_type = FIELD_GET(BOOTROM_BOOT_DEVICE_INTERFACE, boot_device); + + switch (boot_device_type) { + case BT_DEV_TYPE_SD: + case BT_DEV_TYPE_NAND: + case BT_DEV_TYPE_FLEXSPINOR: + case BT_DEV_TYPE_SPI_NOR: + seekable = true; + break; + case BT_DEV_TYPE_USB: + seekable = false; + break; + case BT_DEV_TYPE_MMC: + boot_device_state = FIELD_GET(BOOTROM_BOOT_DEVICE_STATE, boot_device); + if (boot_device_state & BIT(0)) + seekable = false; + else + seekable = true; + break; + default: + return -EINVAL; + } + + return seekable; +} + +int imx93_romapi_load_image(void) +{ + struct rom_api *rom_api = (void *)0x1980; + int ret; + int seekable; + uint32_t offset, image_offset; + void *bl33 = (void *)MX93_ATF_BL33_BASE_ADDR; + struct flash_header_v3 *fh; + + OPTIMIZER_HIDE_VAR(rom_api); + + seekable = imx_romapi_boot_device_seekable(rom_api); + if (seekable < 0) + return seekable; + + if (!seekable) { + int align_size = ALIGN(barebox_pbl_size, 1024) - barebox_pbl_size; + void *pbl_size_aligned = bl33 + ALIGN(barebox_pbl_size, 1024); + + /* + * The USB protocol uploads in chunks of 1024 bytes. This means + * the initial piggy data up to the next 1KiB boundary is already + * transferred. Align up the start address to this boundary. + */ + + return imx_romapi_load_stream(rom_api, + pbl_size_aligned, + __image_end - __piggydata_start - align_size); + } + + ret = imx_bootrom_query(rom_api, BOOTROM_INFO_OFFSET_IMAGE, &offset); + if (ret) + return ret; + + pr_debug("%s: IVT offset on boot device: 0x%08x\n", __func__, offset); + + ret = imx_romapi_load_seekable(rom_api, bl33, offset, 4096); + if (ret) + return ret; + + fh = bl33; + + if (fh->tag != 0x87) { + pr_err("Invalid IVT header: 0x%02x, expected 0x87\n", fh->tag); + return -EINVAL; + } + + image_offset = fh->img[0].offset; + + pr_debug("%s: offset in image: 0x%08x\n", __func__, image_offset); + + /* + * We assume the first image in the first container is the barebox image, + * which is what the imx9image call in images/Makefile.imx generates. + */ + ret = imx_romapi_load_seekable(rom_api, bl33, offset + image_offset, barebox_image_size); + if (ret) + return ret; + + return ret; +} + +const u32 *imx8m_get_bootrom_log(void) +{ + if (current_el() == 3) { + ulong *rom_log_addr_offset = (void *)0x9e0; + ulong rom_log_addr; + + OPTIMIZER_HIDE_VAR(rom_log_addr_offset); + + zero_page_access(); + rom_log_addr = *rom_log_addr_offset; + zero_page_faulting(); + + if (rom_log_addr < MX8M_OCRAM_BASE_ADDR || + rom_log_addr >= MX8M_OCRAM_BASE_ADDR + MX8M_OCRAM_MAX_SIZE || + rom_log_addr & 0x3) { + pr_warn("No BootROM log found at address 0x%08lx\n", rom_log_addr); + return NULL; + } + + return (u32 *)rom_log_addr; + } + + if (!IN_PBL) + return imx8m_scratch_get_bootrom_log(); + + return NULL; +} + +void imx8m_save_bootrom_log(void) +{ + const u32 *rom_log; + + if (!IS_ENABLED(CONFIG_IMX_SAVE_BOOTROM_LOG)) { + pr_debug("skipping bootrom log saving\n"); + return; + } + + rom_log = imx8m_get_bootrom_log(); + if (!rom_log) { + pr_warn("bootrom log not found\n"); + return; + } + + imx8m_scratch_save_bootrom_log(rom_log); +} + +#define IMX93_BOOT_ROM_BASE 0x1000 +#define IMX93_BOOT_ROM_END (0x40000 - 1) + +void imx93_bootsource(void) +{ + struct rom_api *rom_api = (void *)0x1980; + struct resource rom = { + .start = IMX93_BOOT_ROM_BASE, + .end = IMX93_BOOT_ROM_END, + }; + struct resource *r; + int ret; + + r = request_iomem_region("Boot ROM", rom.start, rom.end); + if (IS_ERR(r)) { + ret = PTR_ERR(r); + goto out; + } + + arch_remap_range((void *)rom.start, rom.start, resource_size(&rom), MAP_CACHED); + + OPTIMIZER_HIDE_VAR(rom_api); + + ret = imx_romapi_boot_device(rom_api); +out: + if (ret) + pr_err("Failed to get bootsource: %pe\n", ERR_PTR(ret)); +} diff --git a/arch/arm/mach-imx/scratch.c b/arch/arm/mach-imx/scratch.c new file mode 100644 index 0000000000..60d15a4f1a --- /dev/null +++ b/arch/arm/mach-imx/scratch.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/barebox-arm.h> +#include <init.h> +#include <linux/err.h> +#include <linux/printk.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/imx9-regs.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/scratch.h> +#include <memory.h> +#include <tee/optee.h> +#include <pbl.h> + +struct imx_scratch_space { + u32 bootrom_log[128]; + u32 reserved[128]; /* reserve for bootrom log */ + struct optee_header optee_hdr; +}; + +static struct imx_scratch_space *scratch; + +void imx8m_init_scratch_space(int ddr_buswidth, bool zero_init) +{ + ulong endmem = MX8M_DDR_CSD1_BASE_ADDR + + imx8m_barebox_earlymem_size(ddr_buswidth); + + scratch = (void *)arm_mem_scratch(endmem); + + if (zero_init) + memset(scratch, 0, sizeof(*scratch)); +} + +void imx93_init_scratch_space(bool zero_init) +{ + ulong endmem = MX9_DDR_CSD1_BASE_ADDR + imx9_ddrc_sdram_size(); + + scratch = (void *)arm_mem_scratch(endmem); + + if (zero_init) + memset(scratch, 0, sizeof(*scratch)); +} + +void imx8m_scratch_save_bootrom_log(const u32 *rom_log) +{ + size_t sz = sizeof(scratch->bootrom_log); + + if (!scratch) { + pr_err("No scratch area initialized, skip saving bootrom log"); + return; + } + + pr_debug("Saving bootrom log to scratch area 0x%p\n", &scratch->bootrom_log); + + memcpy(scratch->bootrom_log, rom_log, sz); +} + +const u32 *imx8m_scratch_get_bootrom_log(void) +{ + if (!scratch) { + if (IN_PBL) + return ERR_PTR(-EINVAL); + else + scratch = (void *)arm_mem_scratch_get(); + } + + return scratch->bootrom_log; +} + +void imx_scratch_save_optee_hdr(const struct optee_header *hdr) +{ + size_t sz = sizeof(*hdr); + + if (!scratch) { + pr_err("No scratch area initialized, skip saving optee-hdr"); + return; + } + + pr_debug("Saving optee-hdr to scratch area 0x%p\n", &scratch->optee_hdr); + + memcpy(&scratch->optee_hdr, hdr, sz); +} + +const struct optee_header *imx_scratch_get_optee_hdr(void) +{ + if (!scratch) { + if (IN_PBL) + return ERR_PTR(-EINVAL); + else + scratch = (void *)arm_mem_scratch_get(); + } + + return &scratch->optee_hdr; +} + +static int imx8m_reserve_scratch_area(void) +{ + return PTR_ERR_OR_ZERO(request_sdram_region("scratch area", + (ulong)arm_mem_scratch_get(), + sizeof(struct imx_scratch_space))); +} +device_initcall(imx8m_reserve_scratch_area); diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 73350d15e1..ec8d1bf6f6 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -1,11 +1,5 @@ -/* - * Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Sascha Hauer <s.hauer@pengutronix.de> #include <common.h> #include <init.h> @@ -16,7 +10,7 @@ #define SCR_WARM_RESET_ENABLE BIT(0) -static int imx_src_reset_probe(struct device_d *dev) +static int imx_src_reset_probe(struct device *dev) { struct resource *res; u32 val; @@ -43,15 +37,11 @@ static const struct of_device_id imx_src_dt_ids[] = { { .compatible = "fsl,imx51-src", }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, imx_src_dt_ids); -static struct driver_d imx_src_reset_driver = { +static struct driver imx_src_reset_driver = { .name = "imx-src", .probe = imx_src_reset_probe, .of_compatible = DRV_OF_COMPAT(imx_src_dt_ids), }; - -static int imx_src_reset_init(void) -{ - return platform_driver_register(&imx_src_reset_driver); -} -postcore_initcall(imx_src_reset_init); +postcore_platform_driver(imx_src_reset_driver); diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c new file mode 100644 index 0000000000..4cb4d7c5cf --- /dev/null +++ b/arch/arm/mach-imx/tzasc.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/imx/generic.h> +#include <mach/imx/tzasc.h> +#include <linux/bitops.h> +#include <mach/imx/imx8m-regs.h> +#include <io.h> + +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_ID_SWAP_BYPASS BIT(1) +#define GPR_TZASC_EN_LOCK BIT(16) +#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17) + +#define MX8M_TZASC_REGION_ATTRIBUTES_0 (MX8M_TZASC_BASE_ADDR + 0x108) +#define MX8M_TZASC_REGION_ATTRIBUTES_0_SP GENMASK(31, 28) + +void imx8m_tzc380_init(void) +{ + u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR); + + /* Enable TZASC and lock setting */ + setbits_le32(&gpr[10], GPR_TZASC_EN); + setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK); + + /* + * According to TRM, TZASC_ID_SWAP_BYPASS should be set in + * order to avoid AXI Bus errors when GPU is in use + */ + if (cpu_is_mx8mm() || cpu_is_mx8mn() || cpu_is_mx8mp()) + setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS); + + /* + * imx8mn and imx8mp implements the lock bit for + * TZASC_ID_SWAP_BYPASS, enable it to lock settings + */ + if (cpu_is_mx8mn() || cpu_is_mx8mp()) + setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK); + + /* + * set Region 0 attribute to allow secure and non-secure + * read/write permission. Found some masters like usb dwc3 + * controllers can't work with secure memory. + */ + writel(MX8M_TZASC_REGION_ATTRIBUTES_0_SP, + MX8M_TZASC_REGION_ATTRIBUTES_0); +} + +bool imx8m_tzc380_is_enabled(void) +{ + u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR); + + return (readl(&gpr[10]) & (GPR_TZASC_EN | GPR_TZASC_EN_LOCK)) + == (GPR_TZASC_EN | GPR_TZASC_EN_LOCK); +} diff --git a/arch/arm/mach-imx/vf610.c b/arch/arm/mach-imx/vf610.c index 2fbd6393ea..74d190d7bc 100644 --- a/arch/arm/mach-imx/vf610.c +++ b/arch/arm/mach-imx/vf610.c @@ -1,25 +1,14 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> #include <io.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/vf610.h> -#include <mach/reset-reason.h> -#include <mach/ocotp.h> +#include <mach/imx/generic.h> +#include <mach/imx/revision.h> +#include <mach/imx/vf610.h> +#include <mach/imx/reset-reason.h> +#include <mach/imx/ocotp.h> static const struct imx_reset_reason vf610_reset_reasons[] = { { VF610_SRC_SRSR_POR_RST, RESET_POR, 0 }, diff --git a/arch/arm/mach-imx/xload-common.c b/arch/arm/mach-imx/xload-common.c index bd6405258e..025d87fffc 100644 --- a/arch/arm/mach-imx/xload-common.c +++ b/arch/arm/mach-imx/xload-common.c @@ -1,7 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> +#include <asm/cache.h> #include <asm/sections.h> #include <linux/sizes.h> -#include <mach/xload.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/imx-header.h> +#include <asm/barebox-arm.h> int imx_image_size(void) { @@ -14,3 +21,150 @@ int piggydata_size(void) return input_data_end - input_data; } +#define HDR_SIZE 512 + +static int +imx_search_header(struct imx_flash_header_v2 **header_pointer, + void *buffer, u32 *offset, u32 ivt_offset, + int (*read)(void *dest, size_t len, void *priv), + void *priv) +{ + int ret; + int i, header_count = 1; + void *buf = buffer; + struct imx_flash_header_v2 *hdr; + + for (i = 0; i < header_count; i++) { + ret = read(buf, *offset + ivt_offset + HDR_SIZE, priv); + if (ret) + return ret; + + hdr = buf + *offset + ivt_offset; + + if (!is_imx_flash_header_v2(hdr)) { + pr_debug("No IVT header! " + "Found tag: 0x%02x length: 0x%04x " + "version: %02x\n", + hdr->header.tag, hdr->header.length, + hdr->header.version); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_ARCH_IMX8MQ) && + hdr->boot_data.plugin & PLUGIN_HDMI_IMAGE) { + /* + * In images that include signed HDMI + * firmware, first v2 header would be + * dedicated to that and would not contain any + * useful for us information. In order for us + * to pull the rest of the bootloader image + * in, we need to re-read header from SD/MMC, + * this time skipping anything HDMI firmware + * related. + */ + *offset += hdr->boot_data.size + hdr->header.length; + header_count++; + } + } + *header_pointer = hdr; + return 0; +} + +/** + * imx_load_image - Load i.MX barebox image from boot medium + * @address: Start address of SDRAM where barebox can be loaded into + * @entry: Address where barebox entry point should be placed. + * This is ignored unless @start == false + * @offset: Start offset for i.MX header search + * @ivt_offset: offset between i.MX header and IVT + * @start: whether image should be started after loading + * @alignment: If nonzero, image size hardcoded in PBL will be aligned up + * to this value + * @read: function pointer for reading from the beginning of the boot + * medium onwards + * @priv: private data pointer passed to read function + * + * Return: A negative error code on failure. + * On success, if @start == true, the function will not return. + * If @start == false, the function will return 0 after placing the + * barebox entry point (without header) at @entry. + */ +int imx_load_image(ptrdiff_t address, ptrdiff_t entry, u32 offset, + u32 ivt_offset, bool start, unsigned int alignment, + int (*read)(void *dest, size_t len, void *priv), + void *priv) +{ + + void *buf = (void *)address; + struct imx_flash_header_v2 *hdr = NULL; + int ret, len; + void __noreturn (*bb)(void); + unsigned int ofs; + + len = imx_image_size(); + if (alignment) + len = ALIGN(len, alignment); + + ret = imx_search_header(&hdr, buf, &offset, ivt_offset, read, priv); + if (ret) + return ret; + + pr_debug("Check ok, loading image\n"); + + ofs = offset + hdr->entry - hdr->boot_data.start; + + if (!start) { + /* + * When !start, the caller will start the image later on, + * expecting that it is placed such that its entry + * point would be exactly at 'entry', that is: + * + * buf + ofs = entry + * + * solving the above for 'buf' gives us the + * adjustment that needs to be made: + * + * buf = entry - ofs + * + */ + if (WARN_ON(entry - ofs < address)) { + /* + * We want to make sure we won't try to place + * the start of the image before the beginning + * of the memory buffer we were given in + * address. + */ + return -EINVAL; + } + + buf = (void *)(entry - ofs); + } + + /* + * For SD/MMC High-Capacity support (> 2G), the offset for the block + * read command is in blocks, not bytes. We don't have the information + * whether we have a SDHC card or not, when we run here though, because + * card setup was done by BootROM. To workaround this, we just read + * from offset 0 as 0 blocks == 0 bytes. + * + * A result of this is that we will have to read the i.MX header and + * padding in front of the binary first to arrive at the barebox entry + * point. + */ + ret = read(buf, ofs + len, priv); + if (ret) { + pr_err("Loading image failed with %d\n", ret); + return ret; + } + + pr_debug("Image loaded successfully\n"); + + if (!start) + return 0; + + bb = buf + ofs; + + sync_caches_for_execution(); + + bb(); +} diff --git a/arch/arm/mach-imx/xload-gpmi-nand.c b/arch/arm/mach-imx/xload-gpmi-nand.c new file mode 100644 index 0000000000..8221e1ace0 --- /dev/null +++ b/arch/arm/mach-imx/xload-gpmi-nand.c @@ -0,0 +1,1212 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "xload-gpmi-nand: " fmt + +#include <common.h> +#include <stmp-device.h> +#include <asm-generic/io.h> +#include <linux/sizes.h> +#include <linux/mtd/nand.h> +#include <linux/bitfield.h> +#include <asm/cache.h> +#include <mach/imx/xload.h> +#include <soc/imx/imx-nand-bcb.h> +#include <linux/mtd/rawnand.h> +#include <soc/imx/gpmi-nand.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx7-regs.h> +#include <mach/imx/clock-imx6.h> +#include <dma/apbh-dma.h> + +struct apbh_dma { + void __iomem *regs; + enum mxs_dma_id id; +}; + +struct mxs_dma_chan { + unsigned int flags; + int channel; + struct apbh_dma *apbh; +}; + +/* udelay() is not available in PBL, need to improvise */ +static void __udelay(int us) +{ + volatile int i; + + for (i = 0; i < us * 4; i++); +} + +/* + * Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + */ +static int mxs_dma_enable(struct mxs_dma_chan *pchan, + struct mxs_dma_cmd *pdesc) +{ + struct apbh_dma *apbh = pchan->apbh; + int channel_bit; + int channel = pchan->channel; + unsigned long pdesc32 = (unsigned long)pdesc; + + if (apbh_dma_is_imx23(apbh)) { + writel(pdesc32, + apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel)); + writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel)); + channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL; + } else { + writel(pdesc32, + apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel)); + writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel)); + channel_bit = channel; + } + + writel(1 << channel_bit, apbh->regs + + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); + + return 0; +} + +/* + * Resets the DMA channel hardware. + */ +static int mxs_dma_reset(struct mxs_dma_chan *pchan) +{ + struct apbh_dma *apbh = pchan->apbh; + + if (apbh_dma_is_imx23(apbh)) + writel(1 << (pchan->channel + BP_APBH_CTRL0_RESET_CHANNEL), + apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); + else + writel(1 << (pchan->channel + + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), + apbh->regs + HW_APBHX_CHANNEL_CTRL + + STMP_OFFSET_REG_SET); + + return 0; +} + +static int mxs_dma_wait_complete(struct mxs_dma_chan *pchan) +{ + struct apbh_dma *apbh = pchan->apbh; + int timeout = 1000000; + + while (1) { + if (readl(apbh->regs + HW_APBHX_CTRL1) & (1 << pchan->channel)) + return 0; + + if (!timeout--) + return -ETIMEDOUT; + } +} + +/* + * Execute the DMA channel + */ +static int mxs_dma_run(struct mxs_dma_chan *pchan, struct mxs_dma_cmd *pdesc, + int num) +{ + struct apbh_dma *apbh = pchan->apbh; + int i, ret; + + /* chain descriptors */ + for (i = 0; i < num - 1; i++) { + pdesc[i].next = (unsigned long)(&pdesc[i + 1]); + pdesc[i].data |= MXS_DMA_DESC_CHAIN; + } + + writel(1 << (pchan->channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN), + apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); + + ret = mxs_dma_enable(pchan, pdesc); + if (ret) { + pr_err("%s: Failed to enable dma channel: %d\n", + __func__, ret); + return ret; + } + + ret = mxs_dma_wait_complete(pchan); + if (ret) { + pr_err("%s: Failed to wait for completion: %d\n", + __func__, ret); + return ret; + } + + /* Shut the DMA channel down. */ + writel(1 << pchan->channel, apbh->regs + + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); + writel(1 << pchan->channel, apbh->regs + + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); + + mxs_dma_reset(pchan); + + writel(1 << (pchan->channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN), + apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); + + return 0; +} + +/* ----------------------------- NAND driver part -------------------------- */ + +struct mxs_nand_info { + void __iomem *io_base; + void __iomem *bch_base; + struct mxs_dma_chan *dma_channel; + int cs; + uint8_t *cmd_buf; + struct mxs_dma_cmd *desc; + struct fcb_block fcb; + int dbbt_num_entries; + u32 *dbbt; + struct nand_memory_organization organization; + unsigned long nand_size; +}; + +/** + * It was discovered that xloading barebox from NAND sometimes fails. Observed + * behaviour is similar to silicon errata ERR007117 for i.MX6. + * + * ERR007117 description: + * For raw NAND boot, ROM switches the source of enfc_clk_root from PLL2_PFD2 + * to PLL3. The root clock is required to be gated before switching the source + * clock. If the root clock is not gated, clock glitches might be passed to the + * divider that follows the clock mux, and the divider might behave + * unpredictably. This can cause the clock generation to fail and the chip will + * not boot successfully. + * + * Workaround solution for this errata: + * 1) gate all GPMI/BCH related clocks (CG15, G14, CG13, CG12 and CG6) + * 2) reconfigure clocks + * 3) ungate all GPMI/BCH related clocks + * + */ +static inline void imx6_errata_007117_enable(void) +{ + u32 reg; + + /* Gate (disable) the GPMI/BCH clocks in CCM_CCGR4 */ + reg = readl(MXC_CCM_CCGR4); + reg &= ~(0xFF003000); + writel(reg, MXC_CCM_CCGR4); + + /** + * Gate (disable) the enfc_clk_root before changing the enfc_clk_root + * source or dividers by clearing CCM_CCGR2[CG7] to 2'b00. This + * disables the iomux_ipt_clk_io_clk. + */ + reg = readl(MXC_CCM_CCGR2); + reg &= ~(0x3 << 14); + writel(reg, MXC_CCM_CCGR2); + + /* Configure CCM_CS2CDR for the new clock source configuration */ + reg = readl(MXC_CCM_CS2CDR); + reg &= ~(0x7FF0000); + writel(reg, MXC_CCM_CS2CDR); + reg |= 0xF0000; + writel(reg, MXC_CCM_CS2CDR); + + /** + * Enable enfc_clk_root by setting CCM_CCGR2[CG7] to 2'b11. This + * enables the iomux_ipt_clk_io_clk. + */ + reg = readl(MXC_CCM_CCGR2); + reg |= 0x3 << 14; + writel(reg, MXC_CCM_CCGR2); + + /* Ungate (enable) the GPMI/BCH clocks in CCM_CCGR4 */ + reg = readl(MXC_CCM_CCGR4); + reg |= 0xFF003000; + writel(reg, MXC_CCM_CCGR4); +} + +static uint32_t mxs_nand_aux_status_offset(void) +{ + return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; +} + +static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize, + int oobsize, int pagenum, void *databuf, int raw, bool randomizer) +{ + void __iomem *bch_regs = info->bch_base; + unsigned column = 0; + struct mxs_dma_cmd *d; + int cmd_queue_len; + u8 *cmd_buf; + int ret; + int timeout; + int descnum = 0; + int max_pagenum = info->nand_size / + info->organization.pagesize; + + memset(info->desc, 0, + sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT); + + /* Compile DMA descriptor - read0 */ + cmd_buf = info->cmd_buf; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + cmd_buf[cmd_queue_len++] = NAND_CMD_READ0; + cmd_buf[cmd_queue_len++] = column; + cmd_buf[cmd_queue_len++] = column >> 8; + cmd_buf[cmd_queue_len++] = pagenum; + cmd_buf[cmd_queue_len++] = pagenum >> 8; + + if ((max_pagenum - 1) >= SZ_64K) + cmd_buf[cmd_queue_len++] = pagenum >> 16; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - readstart */ + cmd_buf = &info->cmd_buf[8]; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + + cmd_buf[cmd_queue_len++] = NAND_CMD_READSTART; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - wait for ready. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_NAND_WAIT_4_READY | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(2); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA; + + if (raw) { + /* Compile DMA descriptor - read. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(writesize + oobsize) | + MXS_DMA_DESC_COMMAND_DMA_WRITE; + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + (writesize + oobsize); + d->address = (dma_addr_t)databuf; + } else { + /* Compile DMA descriptor - enable the BCH block and read. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_WAIT4END | MXS_DMA_DESC_PIO_WORDS(6); + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + (writesize + oobsize); + d->pio_words[1] = 0; + d->pio_words[2] = GPMI_ECCCTRL_ENABLE_ECC | + GPMI_ECCCTRL_ECC_CMD_DECODE | + GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; + d->pio_words[3] = writesize + oobsize; + d->pio_words[4] = (dma_addr_t)databuf; + d->pio_words[5] = (dma_addr_t)(databuf + writesize); + + if (randomizer) { + d->pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | + GPMI_ECCCTRL_RANDOMIZER_TYPE2; + d->pio_words[3] |= (pagenum % 256) << 16; + } + + /* Compile DMA descriptor - disable the BCH block. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_NAND_WAIT_4_READY | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(3); + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + (writesize + oobsize); + } + + /* Compile DMA descriptor - de-assert the NAND lock and interrupt. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + /* Execute the DMA chain. */ + ret = mxs_dma_run(info->dma_channel, info->desc, descnum); + if (ret) { + pr_err("DMA read error\n"); + goto err; + } + + if (raw) + return 0; + + timeout = 1000000; + + while (1) { + if (!timeout--) { + ret = -ETIMEDOUT; + goto err; + } + + if (readl(bch_regs + BCH_CTRL) & BCH_CTRL_COMPLETE_IRQ) + break; + } + + writel(BCH_CTRL_COMPLETE_IRQ, + bch_regs + BCH_CTRL + STMP_OFFSET_REG_CLR); + + ret = 0; +err: + return ret; +} + +static int mxs_nand_get_ecc_status(struct mxs_nand_info *info, void *databuf) +{ + uint8_t *status; + int i; + + /* Loop over status bytes, accumulating ECC status. */ + status = databuf + info->organization.pagesize + mxs_nand_aux_status_offset(); + for (i = 0; i < info->organization.pagesize / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; i++) { + if (status[i] == 0xfe) + return -EBADMSG; + } + + return 0; +} + +static int mxs_nand_get_read_status(struct mxs_nand_info *info, void *databuf) +{ + int ret; + u8 *cmd_buf; + struct mxs_dma_cmd *d; + int descnum = 0; + int cmd_queue_len; + + memset(info->desc, 0, + sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT); + + /* Compile DMA descriptor - READ STATUS */ + cmd_buf = info->cmd_buf; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + cmd_buf[cmd_queue_len++] = NAND_CMD_STATUS; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - read. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(1) | + MXS_DMA_DESC_COMMAND_DMA_WRITE; + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + (1); + d->address = (dma_addr_t)databuf; + + /* Compile DMA descriptor - de-assert the NAND lock and interrupt. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + /* Execute the DMA chain. */ + ret = mxs_dma_run(info->dma_channel, info->desc, descnum); + if (ret) { + pr_err("DMA read error\n"); + return ret; + } + + return ret; +} + +static int mxs_nand_reset(struct mxs_nand_info *info, void *databuf) +{ + int ret, i; + u8 *cmd_buf; + struct mxs_dma_cmd *d; + int descnum = 0; + int cmd_queue_len; + u8 read_status; + + memset(info->desc, 0, + sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT); + + /* Compile DMA descriptor - RESET */ + cmd_buf = info->cmd_buf; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + cmd_buf[cmd_queue_len++] = NAND_CMD_RESET; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - de-assert the NAND lock and interrupt. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + /* Execute the DMA chain. */ + ret = mxs_dma_run(info->dma_channel, info->desc, descnum); + if (ret) { + pr_err("DMA read error\n"); + return ret; + } + + /* Wait for NAND to wake up */ + for (i = 0; i < 10; i++) { + __udelay(50000); + ret = mxs_nand_get_read_status(info, databuf); + if (ret) + return ret; + memcpy(&read_status, databuf, 1); + if (read_status & NAND_STATUS_READY) + return 0; + } + + pr_warn("NAND Reset failed\n"); + return -1; +} + +/* function taken from nand_onfi.c */ +static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) +{ + int i; + + while (len--) { + crc ^= *p++ << 8; + for (i = 0; i < 8; i++) + crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); + } + return crc; +} + +static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf) +{ + int ret; + u8 *cmd_buf; + u16 crc; + struct mxs_dma_cmd *d; + int descnum = 0; + int cmd_queue_len; + struct nand_onfi_params nand_params; + + memset(info->desc, 0, + sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT); + + /* Compile DMA descriptor - READ PARAMETER PAGE */ + cmd_buf = info->cmd_buf; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + cmd_buf[cmd_queue_len++] = NAND_CMD_PARAM; + cmd_buf[cmd_queue_len++] = 0x00; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - wait for ready. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_NAND_WAIT_4_READY | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(2); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA; + + /* Compile DMA descriptor - read. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(sizeof(struct nand_onfi_params)) | + MXS_DMA_DESC_COMMAND_DMA_WRITE; + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + (sizeof(struct nand_onfi_params)); + d->address = (dma_addr_t)databuf; + + /* Compile DMA descriptor - de-assert the NAND lock and interrupt. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + /* Execute the DMA chain. */ + ret = mxs_dma_run(info->dma_channel, info->desc, descnum); + if (ret) { + pr_err("DMA read error\n"); + return ret; + } + + memcpy(&nand_params, databuf, sizeof(struct nand_onfi_params)); + + crc = onfi_crc16(NAND_ONFI_CRC_BASE, (u8 *)&nand_params, 254); + pr_debug("ONFI CRC: 0x%x, CALC. CRC 0x%x\n", nand_params.crc, crc); + if (crc != le16_to_cpu(nand_params.crc)) { + pr_debug("ONFI CRC mismatch!\n"); + ret = -EUCLEAN; + return ret; + } + + /* Fill the NAND organization struct with data */ + info->organization.bits_per_cell = nand_params.bits_per_cell; + info->organization.pagesize = le32_to_cpu(nand_params.byte_per_page); + info->organization.oobsize = + le16_to_cpu(nand_params.spare_bytes_per_page); + info->organization.pages_per_eraseblock = + le32_to_cpu(nand_params.pages_per_block); + info->organization.eraseblocks_per_lun = + le32_to_cpu(nand_params.blocks_per_lun); + info->organization.max_bad_eraseblocks_per_lun = + le16_to_cpu(nand_params.bb_per_lun); + info->organization.luns_per_target = nand_params.lun_count; + info->nand_size = info->organization.pagesize * + info->organization.pages_per_eraseblock * + info->organization.eraseblocks_per_lun * + info->organization.luns_per_target; + + return ret; +} + +static int mxs_nand_read_id(struct mxs_nand_info *info, u8 adr, void *databuf, size_t len) +{ + int ret; + u8 *cmd_buf; + struct mxs_dma_cmd *d; + int descnum = 0; + int cmd_queue_len; + + memset(info->desc, 0, + sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT); + + /* Compile DMA descriptor - READID + 0x20 (ADDR) */ + cmd_buf = info->cmd_buf; + cmd_queue_len = 0; + d = &info->desc[descnum++]; + d->address = (dma_addr_t)(cmd_buf); + cmd_buf[cmd_queue_len++] = NAND_CMD_READID; + cmd_buf[cmd_queue_len++] = adr; + + d->data = MXS_DMA_DESC_COMMAND_DMA_READ | + MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(cmd_queue_len); + + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_CLE | + GPMI_CTRL0_ADDRESS_INCREMENT | + cmd_queue_len; + + /* Compile DMA descriptor - read. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_WAIT4END | + MXS_DMA_DESC_PIO_WORDS(1) | + MXS_DMA_DESC_XFER_COUNT(len) | + MXS_DMA_DESC_COMMAND_DMA_WRITE; + d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ | + GPMI_CTRL0_WORD_LENGTH | + FIELD_PREP(GPMI_CTRL0_CS, info->cs) | + GPMI_CTRL0_ADDRESS_NAND_DATA | + len; + d->address = (dma_addr_t)databuf; + + /* Compile DMA descriptor - de-assert the NAND lock and interrupt. */ + d = &info->desc[descnum++]; + d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + /* Execute the DMA chain. */ + ret = mxs_dma_run(info->dma_channel, info->desc, descnum); + if (ret) + pr_err("DMA read error\n"); + + return ret; +} + +struct onfi_header { + u8 byte0; + u8 byte1; + u8 byte2; + u8 byte3; +}; + +static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf) +{ + int ret; + struct onfi_header *onfi_head = databuf; + + ret = mxs_nand_read_id(info, 0x20, databuf, sizeof(struct onfi_header)); + if (ret) + return ret; + + pr_debug("ONFI Byte0: 0x%x\n", onfi_head->byte0); + pr_debug("ONFI Byte1: 0x%x\n", onfi_head->byte1); + pr_debug("ONFI Byte2: 0x%x\n", onfi_head->byte2); + pr_debug("ONFI Byte3: 0x%x\n", onfi_head->byte3); + + if (onfi_head->byte0 != 'O' || onfi_head->byte1 != 'N' || + onfi_head->byte2 != 'F' || onfi_head->byte3 != 'I') + return 1; + + return 0; +} + +struct readid_data { + u8 byte0; + u8 byte1; + u8 byte2; + u8 byte3; + u8 byte4; +}; + +static int mxs_nand_get_readid(struct mxs_nand_info *info, void *databuf) +{ + int ret; + struct readid_data *id_data = databuf; + + ret = mxs_nand_read_id(info, 0x0, databuf, sizeof(struct readid_data)); + if (ret) + return ret; + + pr_debug("NAND Byte0: 0x%x\n", id_data->byte0); + pr_debug("NAND Byte1: 0x%x\n", id_data->byte1); + pr_debug("NAND Byte2: 0x%x\n", id_data->byte2); + pr_debug("NAND Byte3: 0x%x\n", id_data->byte3); + pr_debug("NAND Byte4: 0x%x\n", id_data->byte4); + + if (id_data->byte0 == 0xff || id_data->byte1 == 0xff || + id_data->byte2 == 0xff || id_data->byte3 == 0xff || + id_data->byte4 == 0xff) { + pr_err("\"READ ID\" returned 0xff, possible error!\n"); + return -EOVERFLOW; + } + + /* Fill the NAND organization struct with data */ + info->organization.bits_per_cell = + (1 << ((id_data->byte2 >> 2) & 0x3)) * 2; + info->organization.pagesize = + (1 << (id_data->byte3 & 0x3)) * SZ_1K; + info->organization.oobsize = id_data->byte3 & 0x4 ? + info->organization.pagesize / 512 * 16 : + info->organization.pagesize / 512 * 8; + info->organization.pages_per_eraseblock = + (1 << ((id_data->byte3 >> 4) & 0x3)) * SZ_64K / + info->organization.pagesize; + info->organization.planes_per_lun = + 1 << ((id_data->byte4 >> 2) & 0x3); + info->nand_size = info->organization.planes_per_lun * + (1 << ((id_data->byte4 >> 4) & 0x7)) * SZ_8M; + info->organization.eraseblocks_per_lun = info->nand_size / + (info->organization.pages_per_eraseblock * + info->organization.pagesize); + + return ret; +} + +static int mxs_nand_get_info(struct mxs_nand_info *info, void *databuf) +{ + int ret, i; + + ret = mxs_nand_reset(info, databuf); + if (ret) + return ret; + + ret = mxs_nand_check_onfi(info, databuf); + if (ret) { + if (ret != 1) + return ret; + pr_info("ONFI not supported, try \"READ ID\"...\n"); + } else { + /* + * Some NAND's don't return the correct data the first time + * "READ PARAMETER PAGE" is returned. Execute the command + * multimple times + */ + for (i = 0; i < 3; i++) { + /* + * Some NAND's need to be reset before "READ PARAMETER + * PAGE" can be successfully executed. + */ + ret = mxs_nand_reset(info, databuf); + if (ret) + return ret; + ret = mxs_nand_get_onfi(info, databuf); + if (ret) + pr_err("ONFI error: %d\n", ret); + else + break; + } + if (!ret) + goto succ; + } + + /* + * If ONFI is not supported or if it fails try to get NAND's info from + * "READ ID" command. + */ + ret = mxs_nand_reset(info, databuf); + if (ret) + return ret; + pr_debug("Trying \"READ ID\" command...\n"); + ret = mxs_nand_get_readid(info, databuf); + if (ret) { + pr_err("xloader supports only ONFI and generic \"READ ID\" " \ + "supported NANDs\n"); + return -1; + } +succ: + pr_debug("NAND page_size: %d\n", info->organization.pagesize); + pr_debug("NAND block_size: %d\n", + info->organization.pages_per_eraseblock + * info->organization.pagesize); + pr_debug("NAND oob_size: %d\n", info->organization.oobsize); + pr_debug("NAND nand_size: %lu\n", info->nand_size); + pr_debug("NAND bits_per_cell: %d\n", info->organization.bits_per_cell); + pr_debug("NAND planes_per_lun: %d\n", + info->organization.planes_per_lun); + pr_debug("NAND luns_per_target: %d\n", + info->organization.luns_per_target); + pr_debug("NAND eraseblocks_per_lun: %d\n", + info->organization.eraseblocks_per_lun); + pr_debug("NAND ntargets: %d\n", info->organization.ntargets); + + + return 0; +} + +/* ---------------------------- BCB handling part -------------------------- */ + +static uint32_t calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) + chksum += bp[i]; + + return ~chksum; +} + +static int imx6_get_fcb(struct mxs_nand_info *info, void *databuf) +{ + int i, pagenum, ret; + uint32_t checksum; + struct fcb_block *fcb = &info->fcb; + + /* First page read fails, this shouldn't be necessary */ + mxs_nand_read_page(info, info->organization.pagesize, + info->organization.oobsize, 0, databuf, 1, false); + + for (i = 0; i < 4; i++) { + pagenum = info->organization.pages_per_eraseblock * i; + + ret = mxs_nand_read_page(info, info->organization.pagesize, + info->organization.oobsize, pagenum, databuf, 1, false); + if (ret) + continue; + + ret = mxs_nand_get_ecc_status(info, databuf); + if (ret) + continue; + + memcpy(fcb, databuf + mxs_nand_aux_status_offset(), + sizeof(*fcb)); + + if (fcb->FingerPrint != FCB_FINGERPRINT) { + pr_err("No FCB found on page %d\n", pagenum); + continue; + } + + checksum = calc_chksum((void *)fcb + + sizeof(uint32_t), sizeof(*fcb) - sizeof(uint32_t)); + + if (checksum != fcb->Checksum) { + pr_err("FCB on page %d has invalid checksum. " \ + "Expected: 0x%08x, calculated: 0x%08x", + pagenum, fcb->Checksum, checksum); + continue; + } + + return 0; + } + + return -EINVAL; +} + +static int imx7_get_fcb_n(struct mxs_nand_info *info, void *databuf, int num) +{ + int ret; + int flips = 0; + uint8_t *status; + int i; + + ret = mxs_nand_read_page(info, BCH62_WRITESIZE, BCH62_OOBSIZE, + info->organization.pages_per_eraseblock * num, databuf, 0, true); + if (ret) + return ret; + + /* Loop over status bytes, accumulating ECC status. */ + status = databuf + BCH62_WRITESIZE + 32; + + for (i = 0; i < 8; i++) { + switch (status[i]) { + case 0x0: + break; + case 0xff: + /* + * A status of 0xff means the chunk is erased, but due to + * the randomizer we see this as random data. Explicitly + * memset it. + */ + memset(databuf + 0x80 * i, 0xff, 0x80); + break; + case 0xfe: + return -EBADMSG; + default: + flips += status[0]; + break; + } + } + + return ret; +} + +static int imx7_get_fcb(struct mxs_nand_info *info, void *databuf) +{ + int i, ret; + struct fcb_block *fcb = &info->fcb; + + mxs_nand_mode_fcb_62bit(info->bch_base); + + for (i = 0; i < 4; i++) { + ret = imx7_get_fcb_n(info, databuf, i); + if (!ret) + break; + } + + if (ret) { + pr_err("Cannot find FCB\n"); + } else { + memcpy(fcb, databuf, sizeof(*fcb)); + } + + return ret; +} + +static int get_dbbt(struct mxs_nand_info *info, void *databuf) +{ + int i, ret; + int page; + int startpage = info->fcb.DBBTSearchAreaStartAddress; + struct dbbt_block dbbt; + + for (i = 0; i < 4; i++) { + page = startpage + i * info->organization.pages_per_eraseblock; + + ret = mxs_nand_read_page(info, info->organization.pagesize, + info->organization.oobsize, page, databuf, 0, false); + if (ret) + continue; + + ret = mxs_nand_get_ecc_status(info, databuf); + if (ret) + continue; + + memcpy(&dbbt, databuf, sizeof(struct dbbt_block)); + + if (*(u32 *)(databuf + sizeof(u32)) != DBBT_FINGERPRINT) + continue; + + /* Version check */ + if (be32_to_cpup(databuf + 2 * sizeof(u32)) < 1) + return -ENOENT; + + ret = mxs_nand_read_page(info, info->organization.pagesize, + info->organization.oobsize, page + 4, databuf, 0, false); + if (ret) + continue; + + ret = mxs_nand_get_ecc_status(info, databuf); + if (ret) + continue; + + info->dbbt_num_entries = *(u32 *)(databuf + sizeof(u32)); + + pr_debug("Found DBBT with %d entries\n", + info->dbbt_num_entries); + pr_debug("Checksum = 0x%08x\n", dbbt.Checksum); + pr_debug("FingerPrint = 0x%08x\n", dbbt.FingerPrint); + pr_debug("Version = 0x%08x\n", dbbt.Version); + pr_debug("numberBB = 0x%08x\n", dbbt.numberBB); + pr_debug("DBBTNumOfPages= 0x%08x\n", dbbt.DBBTNumOfPages); + + for (i = 0; i < info->dbbt_num_entries; i++) + pr_debug("badblock %d at block %d\n", i, + *(u32 *)(databuf + (2 + i) * sizeof(u32))); + + info->dbbt = databuf + 2 * sizeof(u32); + + return 0; + } + + return -ENOENT; +} + +static int block_is_bad(struct mxs_nand_info *info, int blocknum) +{ + int i; + u32 *dbbt = info->dbbt; + + if (!dbbt) + return 0; + + for (i = 0; i < info->dbbt_num_entries; i++) { + if (dbbt[i] == blocknum) + return 1; + } + + return 0; +} + +static int read_firmware(struct mxs_nand_info *info, int startpage, + void *dest, int len) +{ + int curpage = startpage; + struct fcb_block *fcb = &info->fcb; + int pagesperblock = fcb->SectorsPerBlock; + int numpages = (len / fcb->PageDataSize) + 1; + int ret; + int pagesize = fcb->PageDataSize; + int oobsize = fcb->TotalPageSize - pagesize; + + pr_debug("Reading %d pages starting from page %d\n", + numpages, startpage); + + if (block_is_bad(info, curpage / pagesperblock)) + curpage = ALIGN_DOWN(curpage + pagesperblock, pagesperblock); + + while (numpages) { + if (!(curpage & (pagesperblock - 1))) { + /* Check for bad blocks on each block boundary */ + if (block_is_bad(info, curpage / pagesperblock)) { + pr_debug("Skipping bad block at page %d\n", + curpage); + curpage += pagesperblock; + continue; + } + } + + ret = mxs_nand_read_page(info, pagesize, oobsize, + curpage, dest, 0, false); + if (ret) { + pr_debug("Failed to read page %d\n", curpage); + return ret; + } + + *((u8 *)dest + fcb->BadBlockMarkerByte) = + *(u8 *)(dest + pagesize); + + numpages--; + dest += pagesize; + curpage++; + } + + return 0; +} + +struct imx_nand_params { + struct mxs_nand_info info; + struct apbh_dma apbh; + void *sdram; + int (*get_fcb)(struct mxs_nand_info *info, void *databuf); +}; + +static int __maybe_unused imx6_nand_load_image(struct imx_nand_params *params, + void *databuf, void *dest, int len) +{ + struct mxs_nand_info *info = ¶ms->info; + struct mxs_dma_chan pchan = { + .channel = 0, /* MXS: MXS_DMA_CHANNEL_AHB_APBH_GPMI0 */ + .apbh = ¶ms->apbh, + }; + int ret; + struct fcb_block *fcb; + void __iomem *bch_regs = info->bch_base; + u32 fl0, fl1; + + info->dma_channel = &pchan; + + pr_debug("cmdbuf: 0x%p descs: 0x%p databuf: 0x%p dest: 0x%p\n", + info->cmd_buf, info->desc, databuf, dest); + + ret = mxs_nand_get_info(info, databuf); + if (ret) + return ret; + + ret = params->get_fcb(info, databuf); + if (ret) + return ret; + + fcb = &info->fcb; + + pr_debug("Found FCB:\n"); + pr_debug("PageDataSize: 0x%08x\n", fcb->PageDataSize); + pr_debug("TotalPageSize: 0x%08x\n", fcb->TotalPageSize); + pr_debug("SectorsPerBlock: 0x%08x\n", fcb->SectorsPerBlock); + pr_debug("FW1_startingPage: 0x%08x\n", + fcb->Firmware1_startingPage); + pr_debug("PagesInFW1: 0x%08x\n", fcb->PagesInFirmware1); + pr_debug("FW2_startingPage: 0x%08x\n", + fcb->Firmware2_startingPage); + pr_debug("PagesInFW2: 0x%08x\n", fcb->PagesInFirmware2); + + info->organization.oobsize = fcb->TotalPageSize - fcb->PageDataSize; + info->organization.pagesize = fcb->PageDataSize; + + fl0 = FIELD_PREP(BCH_FLASHLAYOUT0_NBLOCKS, fcb->NumEccBlocksPerPage) | + FIELD_PREP(BCH_FLASHLAYOUT0_META_SIZE, fcb->MetadataBytes) | + FIELD_PREP(IMX6_BCH_FLASHLAYOUT0_ECC0, fcb->EccBlock0EccType) | + (fcb->BCHType ? BCH_FLASHLAYOUT0_GF13_0_GF14_1 : 0) | + FIELD_PREP(BCH_FLASHLAYOUT0_DATA0_SIZE, fcb->EccBlock0Size / 4); + fl1 = FIELD_PREP(BCH_FLASHLAYOUT1_PAGE_SIZE, fcb->TotalPageSize) | + FIELD_PREP(IMX6_BCH_FLASHLAYOUT1_ECCN, fcb->EccBlockNEccType) | + (fcb->BCHType ? BCH_FLASHLAYOUT1_GF13_0_GF14_1 : 0) | + FIELD_PREP(BCH_FLASHLAYOUT1_DATAN_SIZE, fcb->EccBlockNSize / 4); + writel(fl0, bch_regs + BCH_FLASH0LAYOUT0); + writel(fl1, bch_regs + BCH_FLASH0LAYOUT1); + + get_dbbt(info, databuf); + + ret = read_firmware(info, fcb->Firmware1_startingPage, dest, len); + if (ret) { + pr_err("Failed to read firmware1, trying firmware2\n"); + ret = read_firmware(info, fcb->Firmware2_startingPage, + dest, len); + if (ret) { + pr_err("Failed to also read firmware2\n"); + return ret; + } + } + + return 0; +} + +static int imx_nand_start_image(struct imx_nand_params *params) +{ + struct mxs_nand_info *info = ¶ms->info; + int ret; + void __noreturn (*bb)(void); + void *databuf; + + /* Command buffers */ + info->cmd_buf = params->sdram; + info->desc = params->sdram + MXS_NAND_COMMAND_BUFFER_SIZE; + databuf = info->desc + + sizeof(struct mxs_dma_cmd) * MXS_NAND_DMA_DESCRIPTOR_COUNT; + bb = (void *)PAGE_ALIGN((unsigned long)databuf + SZ_8K); + + ret = imx6_nand_load_image(params, databuf, bb, imx_image_size()); + if (ret) { + pr_err("Loading image failed: %d\n", ret); + return ret; + } + + pr_debug("Starting barebox image at 0x%p\n", bb); + + arm_early_mmu_cache_invalidate(); + barrier(); + + bb(); +} + +int imx6_nand_start_image(void) +{ + static struct imx_nand_params params = { + .info.io_base = IOMEM(MX6_GPMI_BASE_ADDR), + .info.bch_base = IOMEM(MX6_BCH_BASE_ADDR), + .apbh.regs = IOMEM(MX6_APBH_BASE_ADDR), + .apbh.id = IMX28_DMA, + .sdram = (void *)MX6_MMDC_PORT01_BASE_ADDR, + .get_fcb = imx6_get_fcb, + }; + + /* Apply ERR007117 workaround */ + imx6_errata_007117_enable(); + + return imx_nand_start_image(¶ms); +} + +int imx7_nand_start_image(void) +{ + static struct imx_nand_params params = { + .info.io_base = IOMEM(MX7_GPMI_BASE), + .info.bch_base = IOMEM(MX7_BCH_BASE), + .apbh.regs = IOMEM(MX7_APBH_BASE), + .apbh.id = IMX28_DMA, + .sdram = (void *)MX7_DDR_BASE_ADDR, + .get_fcb = imx7_get_fcb, + }; + + return imx_nand_start_image(¶ms); +} diff --git a/arch/arm/mach-imx/xload-imx-nand.c b/arch/arm/mach-imx/xload-imx-nand.c index 22e41fac77..e80f99eb99 100644 --- a/arch/arm/mach-imx/xload-imx-nand.c +++ b/arch/arm/mach-imx/xload-imx-nand.c @@ -1,25 +1,16 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #define pr_fmt(fmt) "imx-nand-boot: " fmt #include <common.h> #include <init.h> #include <io.h> +#include <linux/mtd/rawnand.h> #include <linux/mtd/nand.h> -#include <mach/imx-nand.h> -#include <mach/generic.h> -#include <mach/imx53-regs.h> -#include <mach/xload.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/xload.h> struct imx_nand { void __iomem *base; diff --git a/arch/arm/mach-imx/xload-qspi.c b/arch/arm/mach-imx/xload-qspi.c new file mode 100644 index 0000000000..327a560f8b --- /dev/null +++ b/arch/arm/mach-imx/xload-qspi.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <linux/sizes.h> +#include <mach/imx/atf.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/xload.h> + +#define IMX8M_QSPI_MMAP 0x8000000 + +/* Make use of AHB reads */ +static +int imx8m_qspi_read(void *dest, size_t len, void *priv) +{ + void __iomem *qspi_ahb = priv; + + memcpy(dest, qspi_ahb, len); + + return 0; +} + +/** + * imx8mm_qspi_start_image - Load and optionally start an image from the + * FlexSPI controller. + * @instance: The FlexSPI controller instance + * + * This uses imx8m_qspi_load_image() to load an image from QSPI. It is assumed + * that the image is the currently running barebox image. + * The image is not started afterwards. + * + * Return: If image successfully loaded, returns 0. + * A negative error code is returned when this function fails. + */ +static +int imx8m_qspi_load_image(int instance, off_t offset, off_t ivt_offset, void *bl33) +{ + void __iomem *qspi_ahb = IOMEM(IMX8M_QSPI_MMAP); + + return imx_load_image(MX8M_DDR_CSD1_BASE_ADDR, (ptrdiff_t)bl33, + offset, ivt_offset, false, 0, + imx8m_qspi_read, qspi_ahb); +} + +int imx8mm_qspi_load_image(int instance, void *bl33) +{ + return imx8m_qspi_load_image(instance, 0, SZ_4K, bl33); +} + +int imx8mn_qspi_load_image(int instance, void *bl33) +{ + return imx8m_qspi_load_image(instance, SZ_4K, 0, bl33); +} + +int imx8mp_qspi_load_image(int instance, void *bl33) + __alias(imx8mn_qspi_load_image); diff --git a/arch/arm/mach-imx/xload-spi.c b/arch/arm/mach-imx/xload-spi.c index e87af81e41..621e9557be 100644 --- a/arch/arm/mach-imx/xload-spi.c +++ b/arch/arm/mach-imx/xload-spi.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <io.h> #include <spi/imx-spi.h> -#include <mach/imx6-regs.h> -#include <mach/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/generic.h> #include <bootsource.h> #include <asm/sections.h> #include <linux/sizes.h> -#include <mach/xload.h> +#include <mach/imx/xload.h> static int cspi_2_3_read_data(void __iomem *base, u32 *data) { |