diff options
Diffstat (limited to 'arch/arm/mach-socfpga/cyclone5-generic.c')
| -rw-r--r-- | arch/arm/mach-socfpga/cyclone5-generic.c | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c index dfb1f49e4d..0cb46b51e9 100644 --- a/arch/arm/mach-socfpga/cyclone5-generic.c +++ b/arch/arm/mach-socfpga/cyclone5-generic.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <malloc.h> #include <envfs.h> @@ -10,11 +12,11 @@ #include <linux/stat.h> #include <linux/sizes.h> #include <asm/memory.h> -#include <mach/cyclone5-system-manager.h> -#include <mach/cyclone5-reset-manager.h> -#include <mach/cyclone5-regs.h> -#include <mach/generic.h> -#include <mach/nic301.h> +#include <mach/socfpga/cyclone5-system-manager.h> +#include <mach/socfpga/cyclone5-reset-manager.h> +#include <mach/socfpga/cyclone5-regs.h> +#include <mach/socfpga/generic.h> +#include <mach/socfpga/nic301.h> #include <platform_data/dw_mmc.h> #include <platform_data/serial-ns16550.h> #include <platform_data/cadence_qspi.h> @@ -60,7 +62,7 @@ static struct cadence_qspi_platform_data qspi_pdata = { static void add_cadence_qspi_device(int id, resource_size_t ctrl, resource_size_t data, void *pdata) { - struct device_d *dev; + struct device *dev; struct resource *res; res = xzalloc(sizeof(struct resource) * 2); @@ -100,7 +102,7 @@ static struct NS16550_plat uart_pdata = { void socfpga_cyclone5_uart_init(void) { - struct device_d *dev; + struct device *dev; clks[uart] = clk_fixed("uart", 100000000); clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL); @@ -113,7 +115,7 @@ void socfpga_cyclone5_uart_init(void) void socfpga_cyclone5_timer_init(void) { - struct device_d *dev; + struct device *dev; clks[timer] = clk_fixed("timer", 200000000); clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL); @@ -126,7 +128,8 @@ void socfpga_cyclone5_timer_init(void) static int socfpga_detect_sdram(void) { void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS; - uint32_t dramaddrw, ctrlwidth, memsize; + uint32_t dramaddrw, ctrlwidth; + uint64_t memsize; int colbits, rowbits, bankbits; int width_bytes; @@ -151,12 +154,20 @@ static int socfpga_detect_sdram(void) break; } - memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes; + memsize = (1ULL << colbits) * (1ULL << rowbits) * (1ULL << bankbits) * + width_bytes; - pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n", + pr_debug( + "%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08llx\n", __func__, colbits, rowbits, bankbits, width_bytes, memsize); - arm_add_mem_device("ram0", 0x0, memsize); + /* To work around an erratum in the dram controller, the previous booting + * stage may have increased the amount of rows to fake having 4G of RAM. In + * that case, we assume the previous booting stage will have fixed up a + * proper memory size into the device tree and don't add a bank here */ + if (memsize < SZ_4G) { + arm_add_mem_device("ram0", 0x0, memsize); + } return 0; } |