diff options
Diffstat (limited to 'arch/mips/boards/qemu-malta/lowlevel.S')
| -rw-r--r-- | arch/mips/boards/qemu-malta/lowlevel.S | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S index 98821e0426..8ff7d93a74 100644 --- a/arch/mips/boards/qemu-malta/lowlevel.S +++ b/arch/mips/boards/qemu-malta/lowlevel.S @@ -11,10 +11,9 @@ #include <asm/pbl_macros.h> #include <asm/pbl_nmon.h> #include <linux/sizes.h> - #include <asm/addrspace.h> -#include <asm/gt64120.h> -#include <mach/mach-gt64120.h> + +#include <mach/gt64120.h> #ifdef CONFIG_CPU_LITTLE_ENDIAN #define GT_CPU_TO_LE32(x) (x) @@ -32,18 +31,8 @@ #define GT_HD(x) (GT_CPU_TO_LE32(((x) >> 21) & 0x7f)) ENTRY_FUNCTION(BOARD_PBL_START) - b __start - nop - - /* - On MIPS Technologies boards - 0x1fc00010 address is reserved for BoardID - */ - .org 0x10 - .asciiz "barebox" -__start: - mips_disable_interrupts + mips_cpu_setup /* cpu specific setup ... */ /* ... absent */ @@ -56,14 +45,14 @@ __start: */ /* move GT64120 registers to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) + li t1, CKSEG1ADDR(GT_DEF_BASE) li t0, GT_LD(MIPS_GT_BASE) sw t0, GT_ISD_OFS(t1) /* * setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MIPS_GT_BASE) + li t1, CKSEG1ADDR(MIPS_GT_BASE) /* setup PCI0 io window */ li t0, GT_LD(0x18000000) |