diff options
Diffstat (limited to 'arch/mips/include/asm')
24 files changed, 225 insertions, 210 deletions
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 11f10e5011..dd3b5570dd 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -49,6 +49,16 @@ #define XPHYSADDR(a) ((_ACAST64_(a)) & \ _CONST64_(0x000000ffffffffff)) +/* + * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. + */ +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSSEG 0xc0000000 +#define KSEG3 0xe0000000 + #ifdef CONFIG_64BIT /* @@ -65,11 +75,6 @@ #define CKSSEG _CONST64_(0xffffffffc0000000) #define CKSEG3 _CONST64_(0xffffffffe0000000) -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) - /* * Cache modes for XKPHYS address conversion macros */ @@ -92,35 +97,25 @@ #else -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - /* * Map an address to a certain kernel segment */ #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) +#define KSSEGADDR(a) (CPHYSADDR(a) | KSSEG) #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) -/* - * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. - */ -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +#define CKUSEG KUSEG +#define CKSEG0 KSEG0 +#define CKSEG1 KSEG1 +#define CKSSEG KSSEG +#define CKSEG3 KSEG3 #endif +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSSEGADDR(a) (CPHYSADDR(a) | CKSSEG) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) + #endif /* _ASM_ADDRSPACE_H */ diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h index d370ee36a1..33db5a47e5 100644 --- a/arch/mips/include/asm/asm-offsets.h +++ b/arch/mips/include/asm/asm-offsets.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <generated/asm-offsets.h> diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 69931662ff..f6daae6757 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -83,8 +83,8 @@ symbol: .set noreorder; \ .section .text_head_entry.symbol; \ .align 4; \ - \ -EXPORT(symbol) +EXPORT(symbol) \ + mips_barebox_10h /* * ENTRY_FUNCTION_END - mark end of entry function @@ -94,10 +94,10 @@ EXPORT(symbol) copy_to_link_location symbol; \ stack_setup; \ \ - la a0, __dtb_ ## dtb##_start; \ - la a1, __dtb_ ## dtb##_end; \ - li a2, ram_size; \ - la v0, pbl_main_entry; \ + PTR_LA a0, __dtb_ ## dtb##_start; \ + PTR_LA a1, __dtb_ ## dtb##_end; \ + PTR_LI a2, ram_size; \ + PTR_LA v0, pbl_main_entry; \ jal v0; \ nop; \ \ @@ -122,7 +122,7 @@ EXPORT(symbol) /* Call some code from .text section. \ * It is needed to keep same linker script for \ * all images. */ \ - la v0, mips_dead_end; \ + PTR_LA v0, mips_dead_end; \ jal v0; \ nop; diff --git a/arch/mips/include/asm/barebox.lds.h b/arch/mips/include/asm/barebox.lds.h new file mode 100644 index 0000000000..124f3d5d66 --- /dev/null +++ b/arch/mips/include/asm/barebox.lds.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BAREBOX_OUTPUT_ARCH "mips" + +#include <asm-generic/barebox.lds.h> diff --git a/arch/mips/include/asm/bitsperlong.h b/arch/mips/include/asm/bitsperlong.h index 6dc0bb0c13..bf000a04cc 100644 --- a/arch/mips/include/asm/bitsperlong.h +++ b/arch/mips/include/asm/bitsperlong.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <asm-generic/bitsperlong.h> diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 4bb39b1cd4..f2f50986c7 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_MIPS_CACHE_H #define _ASM_MIPS_CACHE_H diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 9f60e0287d..1e4e361e22 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -12,6 +12,7 @@ */ #define Cache_I 0x00 #define Cache_D 0x01 +#define Cache_SD 0x03 #define Index_Writeback_Inv 0x00 #define Index_Store_Tag 0x08 @@ -23,9 +24,13 @@ */ #define Index_Invalidate_I (Cache_I | Index_Writeback_Inv) #define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) +#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv) #define Index_Store_Tag_I (Cache_I | Index_Store_Tag) #define Index_Store_Tag_D (Cache_D | Index_Store_Tag) +#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag) #define Hit_Invalidate_D (Cache_D | Hit_Invalidate) +#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate) #define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) +#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv) #endif /* __ASM_CACHEOPS_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 9d94eb346b..7fba0b77df 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * cpu.h: Values of the PRId register used to match up * various MIPS cpu types. @@ -49,9 +51,25 @@ * These are the PRID's for when 23:16 == PRID_COMP_MIPS */ +#define PRID_IMP_QEMU_GENERIC 0x0000 +#define PRID_IMP_4KC 0x8000 +#define PRID_IMP_5KC 0x8100 +#define PRID_IMP_20KC 0x8200 +#define PRID_IMP_4KEC 0x8400 +#define PRID_IMP_4KSC 0x8600 +#define PRID_IMP_25KF 0x8800 +#define PRID_IMP_5KE 0x8900 +#define PRID_IMP_4KECR2 0x9000 +#define PRID_IMP_4KEMPR2 0x9100 +#define PRID_IMP_4KSD 0x9200 #define PRID_IMP_24K 0x9300 +#define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 +#define PRID_IMP_M14KC 0x9c00 +#define PRID_IMP_M14KEC 0x9e00 /* * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM @@ -105,11 +123,15 @@ enum cpu_type_enum { /* * MIPS32 class processors */ - CPU_24K, - CPU_74K, - CPU_BMIPS3300, - CPU_JZRISC, - CPU_GS232, + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, + CPU_M14KC, CPU_M14KEC, CPU_1074K, CPU_BMIPS3300, CPU_JZRISC, CPU_GS232, + + /* + * MIPS64 class processors + */ + CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, + + CPU_QEMU_GENERIC, CPU_LAST }; diff --git a/arch/mips/include/asm/debug_ll.h b/arch/mips/include/asm/debug_ll.h new file mode 100644 index 0000000000..96e2082dc8 --- /dev/null +++ b/arch/mips/include/asm/debug_ll.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MIPS_DEBUG_LL_H +#define __ASM_MIPS_DEBUG_LL_H + +#include <mach/debug_ll.h> + +#endif /* __ASM_MIPS_DEBUG_LL_H */ diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h index 703bfaee77..7cfd844cb6 100644 --- a/arch/mips/include/asm/debug_ll_ns16550.h +++ b/arch/mips/include/asm/debug_ll_ns16550.h @@ -60,7 +60,7 @@ static inline void PUTC_LL(char ch) .macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR #ifdef CONFIG_DEBUG_LL - la t0, DEBUG_LL_UART_ADDR + PTR_LA t0, DEBUG_LL_UART_ADDR li t1, UART_LCR_DLAB /* DLAB on */ sb t1, UART_LCR(t0) /* Write it out */ @@ -83,7 +83,7 @@ static inline void PUTC_LL(char ch) .set push .set reorder - la t0, DEBUG_LL_UART_ADDR + PTR_LA t0, DEBUG_LL_UART_ADDR 201: lbu t1, UART_LSR(t0) /* get line status */ andi t1, t1, UART_LSR_THRE /* check for transmitter empty */ @@ -126,7 +126,7 @@ static inline void PUTC_LL(char ch) .set push .set reorder - la t0, DEBUG_LL_UART_ADDR + PTR_LA t0, DEBUG_LL_UART_ADDR /* get line status and check for data present */ lbu t1, UART_LSR(t0) diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h deleted file mode 100644 index c71a087038..0000000000 --- a/arch/mips/include/asm/dma-mapping.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _ASM_DMA_MAPPING_H -#define _ASM_DMA_MAPPING_H - -#include <common.h> -#include <xfuncs.h> -#include <asm/addrspace.h> -#include <asm/types.h> -#include <malloc.h> -#include <asm/io.h> - -static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) -{ - void *ret; - - ret = xmemalign(PAGE_SIZE, size); - - memset(ret, 0, size); - - if (dma_handle) - *dma_handle = CPHYSADDR(ret); - - dma_flush_range((unsigned long)ret, (unsigned long)(ret + size)); - - return (void *)CKSEG1ADDR(ret); -} - -static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle, - size_t size) -{ - if (IS_ENABLED(CONFIG_MMU)) - free((void *)CKSEG0ADDR(vaddr)); - else - free(vaddr); -} - -#endif /* _ASM_DMA_MAPPING_H */ diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index e0b4689172..dbcbfa4076 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -6,6 +6,45 @@ #ifndef __ASM_DMA_H #define __ASM_DMA_H -#include "asm/dma-mapping.h" +#include <linux/pagemap.h> +#include <linux/types.h> +#include <malloc.h> +#include <xfuncs.h> +#include <asm/addrspace.h> +#include <asm/cpu-info.h> +#include <asm/io.h> +#include <asm/types.h> + +#define DMA_ALIGNMENT \ + max(current_cpu_data.dcache.linesz, current_cpu_data.scache.linesz) + +#define dma_alloc_coherent dma_alloc_coherent +static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) +{ + void *ptr; + unsigned long virt; + + ptr = xmemalign(PAGE_SIZE, size); + memset(ptr, 0, size); + + virt = (unsigned long)ptr; + + if (dma_handle) + *dma_handle = CPHYSADDR(virt); + + dma_flush_range(virt, virt + size); + + return (void *)CKSEG1ADDR(virt); +} + +#define dma_free_coherent dma_free_coherent +static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle, + size_t size) +{ + if (IS_ENABLED(CONFIG_MMU) && vaddr) + free((void *)CKSEG0ADDR((unsigned long)vaddr)); + else + free(vaddr); +} #endif /* __ASM_DMA_H */ diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h deleted file mode 100644 index 34d2382593..0000000000 --- a/arch/mips/include/asm/gt64120.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard <carstenl@mips.com> - * Maciej W. Rozycki <macro@mips.com> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_GT64120_H -#define _ASM_GT64120_H - -#define MSK(n) ((1 << (n)) - 1) - -#define GT_DEF_BASE 0x14000000 - -/* - * Register offset addresses - */ - -/* CPU Address Decode. */ -#define GT_PCI0IOLD_OFS 0x048 -#define GT_PCI0IOHD_OFS 0x050 -#define GT_PCI0M0LD_OFS 0x058 -#define GT_PCI0M0HD_OFS 0x060 -#define GT_ISD_OFS 0x068 - -#define GT_PCI0M1LD_OFS 0x080 -#define GT_PCI0M1HD_OFS 0x088 - -#define GT_PCI0IOREMAP_OFS 0x0f0 -#define GT_PCI0M0REMAP_OFS 0x0f8 -#define GT_PCI0M1REMAP_OFS 0x100 - -/* Interrupts. */ -#define GT_INTRCAUSE_OFS 0xc18 - -/* PCI Internal. */ -#define GT_PCI0_CMD_OFS 0xc00 -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc - -#define GT_PCI_DCRM_SHF 21 -#define GT_PCI_LD_SHF 0 -#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) -#define GT_PCI_HD_SHF 0 -#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) -#define GT_PCI_REMAP_SHF 0 -#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) - -#define GT_INTRCAUSE_MASABORT0_SHF 18 -#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) -#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK - -#define GT_INTRCAUSE_TARABORT0_SHF 19 -#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) -#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - -#define GT_PCI0_CMD_MBYTESWAP_SHF 0 -#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) -#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK -#define GT_PCI0_CMD_SBYTESWAP_SHF 16 -#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) -#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. We also provide non-swapping versions. - */ -#define __GT_READ(ofs) \ - (*(volatile u32 *)(GT64120_BASE+(ofs))) -#define __GT_WRITE(ofs, data) \ - do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) -#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) -#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) - -#endif /* _ASM_GT64120_H */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 4df9853680..4584eec8ca 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * Stolen from the linux-2.6/include/asm-generic/io.h */ @@ -25,9 +27,10 @@ void dma_inv_range(unsigned long, unsigned long); * The returned physical address is the physical (CPU) mapping for * the memory address given. */ -static inline unsigned long virt_to_phys(const void *address) +#define virt_to_phys virt_to_phys +static inline unsigned long virt_to_phys(const volatile void *address) { - return (unsigned long)CPHYSADDR(address); + return CPHYSADDR((unsigned long)address); } /* @@ -37,6 +40,7 @@ static inline unsigned long virt_to_phys(const void *address) * The returned virtual address is a current CPU mapping for * the memory address given. */ +#define phys_to_virt phys_to_virt static inline void *phys_to_virt(unsigned long address) { if (IS_ENABLED(CONFIG_MMU)) { diff --git a/arch/mips/include/asm/memory.h b/arch/mips/include/asm/memory.h index 2aa28b7686..0821b432f8 100644 --- a/arch/mips/include/asm/memory.h +++ b/arch/mips/include/asm/memory.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_MIPS_MEMORY_H #define __ASM_MIPS_MEMORY_H diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9e7d656542..0b618320ff 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -406,18 +406,14 @@ #define MIPS_CONF1_PC (_ULCAST_(1) << 4) #define MIPS_CONF1_MD (_ULCAST_(1) << 5) #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA_SHF 7 -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL_SHF 10 -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS_SHF 13 -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA_SHF 16 - #define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DA_SHF 7 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DL_SHF 10 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_DS_SHF 13 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IA_SHF 16 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) #define MIPS_CONF1_IS (_ULCAST_(7) << 22) #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h index 95af871420..1c2646ebb3 100644 --- a/arch/mips/include/asm/mmu.h +++ b/arch/mips/include/asm/mmu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_MMU_H #define __ASM_MMU_H diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h index c62910ff60..61e12cd004 100644 --- a/arch/mips/include/asm/pbl_macros.h +++ b/arch/mips/include/asm/pbl_macros.h @@ -30,9 +30,9 @@ .set noreorder li t9, \addr li t8, \val - lw t7, 0(t9) - or t7, t8 - sw t7, 0(t9) + lw ta3, 0(t9) + or ta3, t8 + sw ta3, 0(t9) .set pop .endm @@ -41,10 +41,10 @@ .set noreorder li t9, \addr li t8, \clr - lw t7, 0(t9) + lw ta3, 0(t9) not t8, t8 - and t7, t8 - sw t7, 0(t9) + and ta3, t8 + sw ta3, 0(t9) .set pop .endm @@ -73,7 +73,7 @@ .macro pbl_probe_mem ret1 ret2 addr .set push .set noreorder - la \ret1, \addr + PTR_LA \ret1, \addr sw zero, 0(\ret1) li \ret2, 0x12345678 sw \ret2, 0(\ret1) @@ -97,7 +97,7 @@ move \temp, ra # preserve ra beforehand bal 255f nop -255: addiu \rd, ra, \label - 255b # label is assumed to be +255: PTR_ADDIU \rd, ra, \label - 255b # label is assumed to be move ra, \temp # within pc +/- 32KB .set pop .endm @@ -110,32 +110,31 @@ ADR a0, \start_addr, t1 /* a0 <- pc-relative position of start_addr */ - la a1, \start_addr /* a1 <- link (RAM) start_addr address */ + PTR_LA a1, \start_addr /* a1 <- link (RAM) start_addr address */ beq a0, a1, copy_loop_exit nop - la t0, \start_addr - la t1, __bss_start - subu t2, t1, t0 /* t2 <- size of pbl */ - addu a2, a0, t2 /* a2 <- source end address */ + PTR_LA t0, \start_addr + PTR_LA t1, __bss_start + PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */ + PTR_ADDU a2, a0, t2 /* a2 <- source end address */ -#define WSIZE 4 copy_loop: /* copy from source address [a0] */ - lw t4, WSIZE * 0(a0) - lw t5, WSIZE * 1(a0) - lw t6, WSIZE * 2(a0) - lw t7, WSIZE * 3(a0) + LONG_L ta0, LONGSIZE * 0(a0) + LONG_L ta1, LONGSIZE * 1(a0) + LONG_L ta2, LONGSIZE * 2(a0) + LONG_L ta3, LONGSIZE * 3(a0) /* copy to target address [a1] */ - sw t4, WSIZE * 0(a1) - sw t5, WSIZE * 1(a1) - sw t6, WSIZE * 2(a1) - sw t7, WSIZE * 3(a1) - addi a0, WSIZE * 4 - subu t3, a0, a2 + LONG_S ta0, LONGSIZE * 0(a1) + LONG_S ta1, LONGSIZE * 1(a1) + LONG_S ta2, LONGSIZE * 2(a1) + LONG_S ta3, LONGSIZE * 3(a1) + PTR_ADDI a0, LONGSIZE * 4 + PTR_SUBU t3, a0, a2 blez t3, copy_loop - addi a1, WSIZE * 4 + PTR_ADDI a1, LONGSIZE * 4 copy_loop_exit: @@ -152,6 +151,34 @@ copy_loop_exit: .set pop .endm + .macro mips_disable_watchpoints + .set push + .set noreorder + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI + .set pop + .endm + + .macro mips64_enable_64bit_addressing +#ifdef CONFIG_64BIT + .set push + .set noreorder + mfc0 k0, CP0_STATUS + or k0, ST0_KX + mtc0 k0, CP0_STATUS + .set pop +#endif + .endm + + .macro mips_cpu_setup + .set push + .set noreorder + mips_disable_interrupts + mips_disable_watchpoints + mips64_enable_64bit_addressing + .set pop + .endm + .macro mips_barebox_10h .set push .set noreorder @@ -160,8 +187,7 @@ copy_loop_exit: nop .org 0x10 - .ascii "barebox" - .byte 0 + .asciiz "barebox" .align 4 1: @@ -196,7 +222,7 @@ copy_loop_exit: .set noreorder /* set stack pointer; reserve four 32-bit argument slots */ - la sp, (TEXT_BASE - MALLOC_SIZE - 16) + PTR_LA sp, (TEXT_BASE - MALLOC_SIZE - 16) .set pop .endm diff --git a/arch/mips/include/asm/pbl_nmon.h b/arch/mips/include/asm/pbl_nmon.h index 0e4ec39967..73e4a9d2e9 100644 --- a/arch/mips/include/asm/pbl_nmon.h +++ b/arch/mips/include/asm/pbl_nmon.h @@ -5,6 +5,9 @@ * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> */ +#ifndef __ASM_PBL_NMON_H +#define __ASM_PBL_NMON_H + #include <mach/debug_ll.h> #define CODE_ESC 0x1b @@ -39,12 +42,12 @@ .set push .set reorder - move t6, a0 - li t5, 32 + move ta2, a0 + li ta1, 32 202: - addi t5, t5, -4 - srlv a0, t6, t5 + addi ta1, ta1, -4 + srlv a0, ta2, ta1 /* output one hex digit */ andi a0, a0, 15 @@ -57,7 +60,7 @@ debug_ll_outc_a0 - bgtz t5, 202b + bgtz ta1, 202b .set pop #endif /* CONFIG_DEBUG_LL */ @@ -286,3 +289,5 @@ nmon_exit: #endif /* CONFIG_NMON */ .set pop .endm + +#endif /* __ASM_PBL_NMON_H */ diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h index 1300251661..df87582e8e 100644 --- a/arch/mips/include/asm/regdef.h +++ b/arch/mips/include/asm/regdef.h @@ -3,6 +3,8 @@ * Copyright (C) 1985 MIPS Computer Systems, Inc. * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. + * Copyright (C) 2011 Wind River Systems, + * written by Ralf Baechle <ralf@linux-mips.org> */ #ifndef _ASM_REGDEF_H #define _ASM_REGDEF_H @@ -27,9 +29,13 @@ #define t2 $10 #define t3 $11 #define t4 $12 +#define ta0 $12 #define t5 $13 +#define ta1 $13 #define t6 $14 +#define ta2 $14 #define t7 $15 +#define ta3 $15 #define s0 $16 /* callee saved */ #define s1 $17 #define s2 $18 diff --git a/arch/mips/include/asm/reloc.h b/arch/mips/include/asm/reloc.h new file mode 100644 index 0000000000..adffd6f1c7 --- /dev/null +++ b/arch/mips/include/asm/reloc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_RELOC_H_ +#define _ASM_RELOC_H_ + +static inline unsigned long get_runtime_offset(void) +{ + /* On MIPS, we always relocate before jumping into C */ + return 0; +} + +#include <asm-generic/reloc.h> + +#endif diff --git a/arch/mips/include/asm/setjmp.h b/arch/mips/include/asm/setjmp.h index 81f4d4c15f..39e01e27df 100644 --- a/arch/mips/include/asm/setjmp.h +++ b/arch/mips/include/asm/setjmp.h @@ -19,7 +19,7 @@ typedef struct __jmp_buf_internal_tag { void *__sp; /* Callee-saved registers s0 through s7. */ - int __regs[8]; + unsigned long __regs[8]; /* The frame pointer. */ void *__fp; diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 2295d7f02f..64ec37478a 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -89,8 +89,10 @@ #endif LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) + MFC0 v1, CP0_BADVADDR LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + LONG_S v1, PT_BVADDR(sp) .set pop .endm @@ -157,11 +159,13 @@ MTC0 v1, CP0_EPC LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) + LONG_L v1, PT_BVADDR(sp) LONG_L $25, PT_R25(sp) #ifdef CONFIG_64BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif + MTC0 v0, CP0_BADVADDR LONG_L $7, PT_R7(sp) LONG_L $6, PT_R6(sp) LONG_L $5, PT_R5(sp) diff --git a/arch/mips/include/asm/word-at-a-time.h b/arch/mips/include/asm/word-at-a-time.h new file mode 100644 index 0000000000..f6306fb896 --- /dev/null +++ b/arch/mips/include/asm/word-at-a-time.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <asm-generic/word-at-a-time.h> |