diff options
Diffstat (limited to 'arch/riscv')
93 files changed, 1206 insertions, 503 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a814a1a45b..8f2cd089a2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + config RISCV def_bool y select GENERIC_FIND_NEXT_BIT @@ -6,14 +8,15 @@ config RISCV select OFDEVICE select COMMON_CLK select COMMON_CLK_OF_PROVIDER - select CLKDEV_LOOKUP select HAS_DMA + select ARCH_DMA_DEFAULT_COHERENT select HAVE_PBL_IMAGE select HAVE_PBL_MULTI_IMAGES select HAVE_IMAGE_COMPRESSION - select HAS_ARCH_SJLJ + select ARCH_HAS_SJLJ select HAS_KALLSYMS select RISCV_TIMER if RISCV_SBI + select HW_HAS_PCI config ARCH_TEXT_BASE hex @@ -82,6 +85,16 @@ config RISCV_EXCEPTIONS default y select ARCH_HAS_DATA_ABORT_MASK +config RISCV_UNWIND + bool "enable stack unwinding support" + select ARCH_HAS_STACK_DUMP + select ARCH_WANT_FRAME_POINTERS + help + This option enables stack unwinding support in barebox + using the information automatically generated by the + compiler. The resulting kernel image is slightly bigger but + the performance is not affected. + config HAS_NMON bool diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index bd4a44a575..cef9cd5230 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + menu "SoC selection" config SOC_ERIZO bool "Erizo SoC" depends on ARCH_RV32I - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON select USE_COMPRESSED_DTB select RISCV_M_MODE @@ -18,13 +20,25 @@ config SOC_VIRT select RISCV_S_MODE select BOARD_RISCV_GENERIC_DT select HAS_CACHE + select HAS_DEBUG_LL help Generates an image tht can be be booted by QEMU. The image is called barebox-dt-2nd.img +config BOARD_RISCV_VIRT + depends on SOC_VIRT + bool "QEMU Virt Machine" + select OF_OVERLAY + select BOARD_QEMU_VIRT + default y + help + Enables environment and state on top of QEMU RISC-V Virt machine + cfi-flash. + config BOARD_RISCVEMU depends on SOC_VIRT bool "TinyEMU Virt Machine (riscvemu)" + select OF_OVERLAY default y help TinyEMU's Virt machine differs from QEMU in poweroff and restart @@ -42,7 +56,7 @@ config SOC_SIFIVE select CLK_SIFIVE_PRCI select RISCV_TIMER select HAS_MACB - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL help This enables support for SiFive SoC platform hardware. @@ -59,7 +73,7 @@ config SOC_STARFIVE bool "StarFive SoCs" select ARCH_HAS_RESET_CONTROLLER select RISCV_S_MODE - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON help This enables support for SiFive SoC platform hardware. @@ -74,6 +88,7 @@ config SOC_STARFIVE_JH7100 bool select SOC_STARFIVE_JH71XX select SIFIVE_L2 + select OF_DMA_COHERENCY help Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent with respect to DMA masters like GMAC and DW MMC controller. @@ -97,6 +112,22 @@ config BOARD_BEAGLEV_BETA endif +config SOC_ALLWINNER_SUN20I + bool "Allwinner Sun20i SoCs" + depends on ARCH_RV64I + select HAS_DEBUG_LL + select HAS_CACHE + +if SOC_ALLWINNER_SUN20I + +config BOARD_ALLWINNER_D1 + bool "Allwinner D1 Nezha" + select RISCV_S_MODE + select RISCV_M_MODE + def_bool y + +endif + comment "CPU features" config SIFIVE_L2 @@ -106,7 +137,7 @@ config SIFIVE_L2 config SOC_LITEX bool "LiteX SoCs" depends on ARCH_RV32I - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON select USE_COMPRESSED_DTB select RISCV_TIMER diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b1278936d..71ca82fe8d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -1,24 +1,34 @@ -KBUILD_DEFCONFIG := virt64_defconfig +# SPDX-License-Identifier: GPL-2.0-only + +KBUILD_DEFCONFIG := rv64i_defconfig KBUILD_CPPFLAGS += -fno-strict-aliasing ifeq ($(CONFIG_ARCH_RV32I),y) - riscv-cflags-y += -march=rv32im -mabi=ilp32 + KBUILD_CPPFLAGS += -mabi=ilp32 riscv-ldflags-y += -melf32lriscv else - riscv-cflags-y += -march=rv64im -mabi=lp64 + KBUILD_CPPFLAGS += -mabi=lp64 riscv-ldflags-y += -melf64lriscv endif -riscv-cflags-y += -Wstrict-prototypes -mcmodel=medany -fpic -riscv-ldflags-y += -pie -static +# ISA string setting +riscv-march-$(CONFIG_ARCH_RV32I) := rv32im +riscv-march-$(CONFIG_ARCH_RV64I) := rv64im -PBL_CPPFLAGS += $(riscv-cflags-y) -LDFLAGS_pbl += $(riscv-ldflags-y) +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei -cflags-y += $(riscv-cflags-y) -LDFLAGS_barebox += -nostdlib +KBUILD_CPPFLAGS += -march=$(riscv-march-y) +KBUILD_CFLAGS += -mno-save-restore +KBUILD_CFLAGS += -fno-asynchronous-unwind-tables -fno-unwind-tables +KBUILD_CFLAGS += $(call cc-option,-mstrict-align) +KBUILD_CPPFLAGS += -Wstrict-prototypes -mcmodel=medany -fpic +riscv-ldflags-y += -pie -static +LDFLAGS_pbl += $(riscv-ldflags-y) LDFLAGS_barebox += $(riscv-ldflags-y) ifndef CONFIG_MODULES @@ -28,6 +38,7 @@ LDFLAGS_barebox += -static --gc-sections endif KBUILD_BINARY := barebox.bin +KBUILD_IMAGE := $(KBUILD_BINARY) archprepare: maketools @@ -40,11 +51,6 @@ common-y += arch/riscv/boot/ common-$(CONFIG_OFTREE) += arch/riscv/dts/ -KBUILD_CPPFLAGS += $(cflags-y) -KBUILD_CFLAGS += $(cflags-y) - lds-y := arch/riscv/lib/barebox.lds CLEAN_FILES += arch/riscv/lib/barebox.lds - -KBUILD_IMAGE := $(KBUILD_BINARY) diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile index 3b763ff308..df16d38496 100644 --- a/arch/riscv/boards/Makefile +++ b/arch/riscv/boards/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_BOARD_ALLWINNER_D1) += allwinner-d1/ obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/ obj-$(CONFIG_BOARD_HIFIVE) += hifive/ obj-$(CONFIG_BOARD_BEAGLEV) += beaglev/ diff --git a/arch/riscv/boards/allwinner-d1/Makefile b/arch/riscv/boards/allwinner-d1/Makefile new file mode 100644 index 0000000000..3d217ffe0b --- /dev/null +++ b/arch/riscv/boards/allwinner-d1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.o diff --git a/arch/riscv/boards/allwinner-d1/lowlevel.c b/arch/riscv/boards/allwinner-d1/lowlevel.c new file mode 100644 index 0000000000..2b07a81edb --- /dev/null +++ b/arch/riscv/boards/allwinner-d1/lowlevel.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-riscv.h> + +#define DRAM_BASE 0x40000000 + +ENTRY_FUNCTION(start_allwinner_d1, a0, a1, a2) +{ + barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, a0, (void *)a1); +} diff --git a/arch/riscv/boards/beaglev/board.c b/arch/riscv/boards/beaglev/board.c index 110754ea95..d466eef7f1 100644 --- a/arch/riscv/boards/beaglev/board.c +++ b/arch/riscv/boards/beaglev/board.c @@ -8,7 +8,7 @@ #include <bbu.h> #include <envfs.h> -static int beaglev_probe(struct device_d *dev) +static int beaglev_probe(struct device *dev) { barebox_set_hostname("beaglev-starlight"); @@ -21,8 +21,9 @@ static const struct of_device_id beaglev_of_match[] = { { .compatible = "beagle,beaglev-starlight-jh7100" }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, beaglev_of_match); -static struct driver_d beaglev_board_driver = { +static struct driver beaglev_board_driver = { .name = "board-beaglev", .probe = beaglev_probe, .of_compatible = beaglev_of_match, diff --git a/arch/riscv/boards/litex-linux/lowlevel.c b/arch/riscv/boards/litex-linux/lowlevel.c index da23ef5633..6be3d62e64 100644 --- a/arch/riscv/boards/litex-linux/lowlevel.c +++ b/arch/riscv/boards/litex-linux/lowlevel.c @@ -10,12 +10,12 @@ ENTRY_FUNCTION(start_litex_linux, a0, a1, a2) extern char __dtb_z_litex_linux_start[]; void *fdt; + /* BIOS will have loaded us into RAM */ + barebox_nmon_entry(); putc_ll('>'); - /* On POR, we are running from read-only memory here. */ - fdt = __dtb_z_litex_linux_start + get_runtime_offset(); barebox_riscv_machine_entry(0x40000000, SZ_256M, fdt); diff --git a/arch/riscv/boards/riscvemu/Makefile b/arch/riscv/boards/riscvemu/Makefile index dcfc2937d3..baada2136e 100644 --- a/arch/riscv/boards/riscvemu/Makefile +++ b/arch/riscv/boards/riscvemu/Makefile @@ -1 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o +obj-y += riscvemu-sram.dtbo.o +bbenv-$(CONFIG_CMD_TUTORIAL) += defaultenv-riscvemu + +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z +clean-files += *.dtbo *.dtbo.S .*.dtso diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c index 7dbf9afe4c..afd6608ac5 100644 --- a/arch/riscv/boards/riscvemu/board.c +++ b/arch/riscv/boards/riscvemu/board.c @@ -5,8 +5,10 @@ #include <common.h> #include <driver.h> +#include <envfs.h> #include <poweroff.h> #include <restart.h> +#include <deep-probe.h> #include <asm/system.h> #include <asm/barebox-riscv.h> @@ -16,22 +18,13 @@ struct riscvemu_priv { }; -#define HTIF_BASE_ADDR IOMEM(0x40008000) -#define HTIF_TOHOST_LOW (HTIF_BASE_ADDR + 0) -#define HTIF_TOHOST_HIGH (HTIF_BASE_ADDR + 4) - -static void __noreturn riscvemu_poweroff(struct poweroff_handler *pwr) -{ - writel(1, HTIF_TOHOST_LOW); - writel(0, HTIF_TOHOST_HIGH); - - __builtin_unreachable(); -} - static void __noreturn riscvemu_restart(struct restart_handler *rst) { struct riscvemu_priv *priv = container_of(rst, struct riscvemu_priv, rst); + /* clear screen on graphic console */ + puts("\e[J"); + /* * barebox PBL relocates itself to end of RAM early on, so unless * something explicitly scrubbed the initial PBL, we can jump back to @@ -40,14 +33,21 @@ static void __noreturn riscvemu_restart(struct restart_handler *rst) priv->restart(riscv_hartid(), barebox_riscv_boot_dtb()); } -static int riscvemu_probe(struct device_d *dev) +extern char __dtbo_riscvemu_sram_start[]; + +static int riscvemu_probe(struct device *dev) { struct device_node *of_chosen; + struct device_node *overlay; struct riscvemu_priv *priv; u64 start; - if (of_find_compatible_node(NULL, NULL, "ucb,htif0")) - poweroff_handler_register_fn(riscvemu_poweroff); + overlay = of_unflatten_dtb(__dtbo_riscvemu_sram_start, INT_MAX); + of_overlay_apply_tree(dev->of_node, overlay); + /* of_probe() will happen later at of_populate_initcall */ + + if (IS_ENABLED(CONFIG_CMD_TUTORIAL)) + defaultenv_append_directory(defaultenv_riscvemu); of_chosen = of_find_node_by_path("/chosen"); @@ -67,8 +67,9 @@ static const struct of_device_id riscvemu_of_match[] = { { .compatible = "ucbbar,riscvemu-bar_dev" }, { /* sentinel */ }, }; +BAREBOX_DEEP_PROBE_ENABLE(riscvemu_of_match); -static struct driver_d riscvemu_board_driver = { +static struct driver riscvemu_board_driver = { .name = "board-riscvemu", .probe = riscvemu_probe, .of_compatible = riscvemu_of_match, diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init new file mode 100644 index 0000000000..1ff43142ba --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init @@ -0,0 +1,12 @@ + +You are using Hush, barebox' default shell. You are currently using it +interactively, but it can execute scripts as part of the startup and boot +procedure as well. See for yourself: +``` + cat /env/init/90-tutorial-intro +``` +Look around as you like. When you are ready to continue the tutorial, +type `next` again. The `prev` command does the inverse and shows previous +tutorial steps. The `help` command will show help usage text, +e.g. `help next`. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive new file mode 100644 index 0000000000..8b285cd9f4 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive @@ -0,0 +1,7 @@ + +The interactive shell, its commands and the nodes in the virtual +file system they operate on enable quick UNIX-like prototyping +and debugging. Let's give it a try, shall we? +Type `of_dump` to list the open firmware (OF) device tree barebox +used to discover the hardware and `next` to continue the tutorial. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump new file mode 100644 index 0000000000..3271f734b2 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump @@ -0,0 +1,6 @@ + +That's a lot of output, so let's restrict ourselves to just part +of the tree: +``` + of_dump /soc/virtio@40010000 +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo new file mode 100644 index 0000000000..74bc9aa88a --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo @@ -0,0 +1,5 @@ + +This node tells barebox enough information to instantiate a device and +to try match it with existing drivers. Type `devinfo` to see the tree of +devices known to barebox. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 new file mode 100644 index 0000000000..fdb878fa93 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 @@ -0,0 +1,11 @@ + +In this tree, you will find 40010000.virtio@40010000.of, the +device corresponding to the device tree node we've just seen. +Devices can have child devices themselves. This device's +grandchild is `cs0`, the virtual console device that prints +you this very text. + +See for yourself: +``` + echo -a /dev/cs0 Append this text to virtio console +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo new file mode 100644 index 0000000000..068bf303d8 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo @@ -0,0 +1,4 @@ + +Let's look at more devices. Type `drvinfo` to see what drivers are +available and what devices they were successfully matched with. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev new file mode 100644 index 0000000000..f706915ba2 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev @@ -0,0 +1,6 @@ + +Let's pick another device out of the list: HTIF. We can display some extra +info with `devinfo`. (Use the tab completion to avoid writing it all out!) +``` +devinfo 40008000.htif.of +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw new file mode 100644 index 0000000000..4278f8f391 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw @@ -0,0 +1,9 @@ + +We see that the device has a memory mapped I/O region of 8 bytes that +can be used for communication. Poking 0x010100000000002e in little- +endian into that region should print a period '.'. +Let's do that quad-word memory write (`mw -q`) 80 times by having a shell +local variable keep count: +``` +i=0; while [ $i -lt 80 ]; do mw -q 0x40008000 0x010100000000002e; let i=$i+1; done +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs new file mode 100644 index 0000000000..b117e4bb16 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs @@ -0,0 +1,8 @@ + +`mw` is complemented by `md` for memory display. There are further commands +like `mm` (memory modify), `memcpy` and `memcmp` (copy/compare ranges). +These commands operate on `/dev/mem` by default, but any seekable device +or file can be used instead. Let's see what device files we got here: +``` +ls /dev +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions new file mode 100644 index 0000000000..552ab2ab1e --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions @@ -0,0 +1,9 @@ + +The `mtdram0` looks interesting. That's the 64K SRAM at the start of the +address space. The virtual machine places the boot "rom" there as well +as the flattened (compiled) device tree (FDT). barebox can be informed +about partitioning and will create extra devices for each partition. +This allows you to reference them from commands easily: +``` +of_dump -f /dev/mtdram0.fdt +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment new file mode 100644 index 0000000000..d1a6f85119 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment @@ -0,0 +1,8 @@ + +Not all of the 64K is used, so the barebox board support here uses +the unused mtd-ram space for saving modified environment and state. +The barebox environment is a file system which contains scripts, variables +and data: +``` +ls -R /env +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data new file mode 100644 index 0000000000..81e3f47ee7 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data @@ -0,0 +1,12 @@ + +The environment you see here is the built-in environment barebox was +compiled with. It contains default values for non-volatile variables, +(init) scripts and data. It's generated from directories on the host +system specified during build and stored as an archive within +barebox. This environment may also be compressed allowing shipping +larger files and even binaries. For example, this barebox binary +has the option CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_IKCONFIG=y, +which ships a copy of the used barebox configuration. See for yourself: +``` +cat /env/data/config +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg new file mode 100644 index 0000000000..61cdd2adaf --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg @@ -0,0 +1,9 @@ + +In the field, you will probably want to depend exclusively on the built-in +environment, but it can be very handy to persist environment changes during +development. You may recall that barebox told us at first boot that the +environment was never written? If you don't, no problem, log messages are, +you guessed it, logged: +``` +dmesg +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin new file mode 100644 index 0000000000..34b7ab554b --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin @@ -0,0 +1,11 @@ + +Let's modify the environment to add a new script (Remember +`help` can show you the usage, e.g. `help mw`): +``` +cd /env/bin +echo -o putc '#!/bin/sh' +echo -a putc 'mw -l 0x40008000 $1' +echo -a putc 'mw -l 0x40008004 0x01010000' +cd / +putc 0x40 # Print an @ character +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init new file mode 100644 index 0000000000..184a4f571f --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init @@ -0,0 +1,8 @@ + +We could have added the last script anywhere in `/env`. But `/env/bin` is +already in the executable search `PATH`, so you don't have to write out +the full path when invoking the script. Another special directory is +`/env/init`. Anything there will be sourced on shell startup. +Let's poke the HTIF a bit every time we start: Open a new file with +`edit /env/init/99-percent` and type into it `putc 0x40`. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar new file mode 100644 index 0000000000..ec2912da9f --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar @@ -0,0 +1,10 @@ + +As init scripts only run on initialization, we'll have to do a reset to +see them in action. But first, we'll want to save our tutorial progress. +This happens via $global.variables. Many parts of barebox monitor reads +and writes to such variables to make information available to the shell. + +The `next` command also does it. How would you know? +``` +magicvar +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv new file mode 100644 index 0000000000..3440e01947 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv @@ -0,0 +1,12 @@ + +Now that you know that $global.tutorial.step holds the next step, you +will want to initialize it on the next reset. We could write an init shell +script for that, but there is something much more convenient: + +On startup, barebox needs to assign initial values for each +$global.variable; if a suitably named non-volatile $nv.variable already +exists, it will be used as initial value. Let's see what global variables +we got (leading asterisk '*' means it was initialized from NV): +``` +global +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv new file mode 100644 index 0000000000..f929838138 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv @@ -0,0 +1,7 @@ + +Now that we have written a normal script and an init script, add a +nv variable to the mix, save the environment and reset to see them +all in action: +``` +nv tutorial.step=$global.tutorial.step; saveenv; reset +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage new file mode 100644 index 0000000000..1f4ff37f86 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage @@ -0,0 +1,5 @@ + +Welcome back! You have successfully saved the environment. Make sure +to reset your environment with `saveenv -z` when you are done. You wouldn't +want to chase ghosts, because you changed an init script and forgot about it. :) + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt new file mode 100644 index 0000000000..3122e6ffa4 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt @@ -0,0 +1,11 @@ + +We now have seen `/dev`, which holds the devfs, and `/env` which holds the +active environment. `/tmp` is as you have guessed it a directory where temporary +files can be placed. `/pstore` is short for persistent storage, a Linux +mechanism to store and retrieve error records even after a kernel panic. + +This leaves `/mnt`. Let's take a peek at it as well at our active mounts: +``` +mount +ls /mnt +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount new file mode 100644 index 0000000000..4d4787a9a8 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount @@ -0,0 +1,9 @@ + +Strangely, nothing inside `/mnt` is seen in the `mount` output. Why you +ask? Because these are automounts that are deferred until first access. +So when you `bootm /mnt/nfs/boot/Image.gz` the first time, barebox will +bring up the network and mount the network file system (provided you do +have network). We can list what automounts there are: +``` +automount -l +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs new file mode 100644 index 0000000000..cc5e64c66c --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs @@ -0,0 +1,11 @@ + +`/mnt/virtioblk0` is an interesting one. Block device partitions +automatically get automount entries created. On first access, +barebox will determine what file system is located in the partition +and mount it. Thus you can just use `/mnt/virtioblk0/DOOM1.WAD` in +your script and not incur the overhead of mounting unless it's accessed: +``` +mount +ll /mnt/virtioblk0/DOOM1.WAD +mount +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state new file mode 100644 index 0000000000..1a71204cf5 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state @@ -0,0 +1,11 @@ + +You'll note most file systems in barebox are read-only. While those that aren't +could be used with `saveenv` to store a packed environment for Linux use, that's +murky waters: atomicity, limiting scope, authentication and journal handling +complicate things. barebox state is the mechanism how barebox stores variables +(and only variables) in a power-fail safe manner that's also accessible to Linux. + +Check the `state` device: +``` +devinfo state +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params new file mode 100644 index 0000000000..3f8d31f171 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params @@ -0,0 +1,11 @@ + +The state driver parses the device tree to learn the state layout +and how it's (redundantly) placed. The information it learns are +registered with the device as device parameters. Device Parameters +make it easy to interact with the shell. For example, the MAC address +of a network adapter is a device parameter. We already saw some other +device parameters before. Those of the global and nv device: +``` +devinfo global +devinfo nv +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types new file mode 100644 index 0000000000..36a311d011 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types @@ -0,0 +1,8 @@ + +Many device parameters are simple strings, some have specific types +and run actions on read/write or accept only specific values. +`devinfo` will show you what type a variable has and writing an +invalid value will give you an error: +``` +global.tutorial.step=non-existent +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot new file mode 100644 index 0000000000..90c2266973 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot @@ -0,0 +1,12 @@ + +You should now know enough about barebox' architecture, that +we could talk about barebox' actual function without it +seeming too magical: Booting. + +We still need to add that part to the tutorial though, but you +can check out `help boot`, `help bootm` as well as the barebox +documentation linked below. Also give the graphical mode a +try! + +Tutorial to be continued.. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end new file mode 100644 index 0000000000..4744f2b3ee --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end @@ -0,0 +1 @@ +End of tutorial reached! diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro new file mode 100644 index 0000000000..716905534c --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro @@ -0,0 +1,6 @@ +source /env/data/ansi-colors + +echo -e $YELLOW +echo -e This is the barebox shell. See ${RED}help${YELLOW} for a listing of commands. +echo -e Type ${RED}next${YELLOW} for the next tutorial tip. +echo -e $NC diff --git a/arch/riscv/boards/riscvemu/riscvemu-sram.dtso b/arch/riscv/boards/riscvemu/riscvemu-sram.dtso new file mode 100644 index 0000000000..395fde84c1 --- /dev/null +++ b/arch/riscv/boards/riscvemu/riscvemu-sram.dtso @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/dts-v1/; +/plugin/; + +&{/soc} { + #address-cells = <2>; + #size-cells = <2>; + sram@1000 { + compatible = "mtd-ram"; + reg = <0 0x1000 0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootrom"; + reg = <0x0 0x40>; + }; + + partition@40 { + label = "fdt"; + reg = <0x40 0x1fc0>; + }; + + environment_sram: partition@3000 { + label = "barebox-environment"; + reg = <0x3000 0xb000>; + }; + + backend_state_sram: partition@e000 { + label = "barebox-state"; + reg = <0xe000 0x1000>; + }; + }; + }; +}; + +&{/chosen} { + environment { + compatible = "barebox,environment"; + device-path = "/soc/sram@1000/partitions/partition@3000"; + }; +}; + +&{/} { + aliases { + state = "/state"; + }; + + state { + #address-cells = <1>; + #size-cells = <1>; + compatible = "barebox,state"; + magic = <0x290cf8c6>; + backend-type = "raw"; + backend = <&backend_state_sram>; + backend-stridesize = <64>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <21>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&{/htif} { + reg = <0 0x40008000 0 0x8>; +}; diff --git a/arch/riscv/boot/board-dt-2nd.c b/arch/riscv/boot/board-dt-2nd.c index 8b78e1b11d..f1479d8346 100644 --- a/arch/riscv/boot/board-dt-2nd.c +++ b/arch/riscv/boot/board-dt-2nd.c @@ -50,6 +50,12 @@ static void noinline __noreturn start_dt_2nd_nonnaked(unsigned long hartid, if (!fdt) hang(); + /* + * We need to call this here, as a multiplatform build + * depends on querying mode for riscv_vendor_id() + */ + riscv_set_flags(RISCV_S_MODE); + relocate_to_current_adr(); setup_c(); diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c index e4a5c2208d..f5a536fc78 100644 --- a/arch/riscv/boot/entry.c +++ b/arch/riscv/boot/entry.c @@ -25,6 +25,7 @@ void __noreturn __naked barebox_riscv_entry(unsigned long membase, { unsigned long stack_top = riscv_mem_stack_top(membase, membase + memsize); asm volatile ("move sp, %0" : : "r"(stack_top)); - barebox_pbl_start(membase, memsize, boarddata, flags); + riscv_set_flags(flags); + barebox_pbl_start(membase, memsize, boarddata); } diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h index fb4af5eae5..b3a24d2783 100644 --- a/arch/riscv/boot/entry.h +++ b/arch/riscv/boot/entry.h @@ -6,12 +6,10 @@ void __noreturn barebox_non_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, - unsigned flags); + void *boarddata); void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, - unsigned flags); + void *boarddata); #endif diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c index 72ab93cb76..92991d0f6a 100644 --- a/arch/riscv/boot/start.c +++ b/arch/riscv/boot/start.c @@ -3,6 +3,10 @@ #define pr_fmt(fmt) "start.c: " fmt +#ifdef CONFIG_DEBUG_INITCALLS +#define DEBUG +#endif + #include <common.h> #include <init.h> #include <linux/sizes.h> @@ -27,12 +31,10 @@ static unsigned long riscv_barebox_size; static unsigned long riscv_endmem; static void *barebox_boarddata; static unsigned long barebox_boarddata_size; -unsigned barebox_riscv_pbl_flags; void *barebox_riscv_boot_dtb(void) { void *dtb; - void *data; int ret; struct barebox_boarddata_compressed_dtb *compressed_dtb; static void *boot_dtb; @@ -56,9 +58,8 @@ void *barebox_riscv_boot_dtb(void) if (!dtb) return NULL; - data = compressed_dtb + 1; - - ret = uncompress(data, compressed_dtb->datalen, NULL, NULL, dtb, NULL, NULL); + ret = uncompress(compressed_dtb->data, compressed_dtb->datalen, + NULL, NULL, dtb, NULL, NULL); if (ret) { pr_err("uncompressing dtb failed\n"); free(dtb); @@ -110,7 +111,7 @@ device_initcall(barebox_memory_areas_init); */ __noreturn __no_sanitize_address __section(.text_entry) void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, unsigned flags) + void *boarddata) { unsigned long endmem = membase + memsize; unsigned long malloc_start, malloc_end; @@ -123,7 +124,7 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, barrier(); - irq_init_vector(__riscv_mode(flags)); + irq_init_vector(riscv_mode()); pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize); @@ -173,20 +174,18 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1); - barebox_riscv_pbl_flags = flags; - pr_debug("starting barebox...\n"); start_barebox(); } -void start(unsigned long membase, unsigned long memsize, void *boarddata, unsigned flags); +void start(unsigned long membase, unsigned long memsize, void *boarddata); /* * First function in the uncompressed image. We get here from * the pbl. The stack already has been set up by the pbl. */ void __no_sanitize_address __section(.text_entry) start(unsigned long membase, - unsigned long memsize, void *boarddata, unsigned flags) + unsigned long memsize, void *boarddata) { - barebox_non_pbl_start(membase, memsize, boarddata, flags); + barebox_non_pbl_start(membase, memsize, boarddata); } diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c index 4ed9b4d371..84142acf9c 100644 --- a/arch/riscv/boot/uncompress.c +++ b/arch/riscv/boot/uncompress.c @@ -24,20 +24,20 @@ unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, - void *fdt, unsigned flags) + void *fdt) { uint32_t pg_len, uncompressed_len; - void __noreturn (*barebox)(unsigned long, unsigned long, void *, unsigned); + void __noreturn (*barebox)(unsigned long, unsigned long, void *); unsigned long endmem = membase + memsize; unsigned long barebox_base; void *pg_start, *pg_end; unsigned long pc = get_pc(); - irq_init_vector(__riscv_mode(flags)); + irq_init_vector(riscv_mode()); /* piggy data is not relocated, so determine the bounds now */ - pg_start = input_data + get_runtime_offset(); - pg_end = input_data_end + get_runtime_offset(); + pg_start = runtime_address(input_data); + pg_end = runtime_address(input_data_end); pg_len = pg_end - pg_start; uncompressed_len = input_data_len(); @@ -72,5 +72,5 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt); - barebox(membase, memsize, fdt, flags); + barebox(membase, memsize, fdt); } diff --git a/arch/riscv/configs/starfive_defconfig b/arch/riscv/configs/rv64i_defconfig index c4df2256f5..53c367c5e4 100644 --- a/arch/riscv/configs/starfive_defconfig +++ b/arch/riscv/configs/rv64i_defconfig @@ -1,7 +1,12 @@ CONFIG_ARCH_RV64I=y +CONFIG_SOC_ALLWINNER_SUN20I=y +CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y +CONFIG_SOC_VIRT=y +CONFIG_BOARD_ALLWINNER_D1=y CONFIG_BOARD_BEAGLEV=y CONFIG_BOARD_BEAGLEV_BETA=y +CONFIG_BOARD_HIFIVE=y CONFIG_BOARD_RISCV_GENERIC_DT=y CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y CONFIG_STACK_SIZE=0x20000 @@ -14,15 +19,16 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y +CONFIG_BOOTM_VERBOSE=y CONFIG_BOOTM_INITRD=y CONFIG_SYSTEM_PARTITIONS=y -CONFIG_IMD_TARGET=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_IKCONFIG=y CONFIG_STATE=y CONFIG_STATE_CRYPTO=y CONFIG_BOOTCHOOSER=y @@ -54,8 +60,12 @@ CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_FBTEST=y CONFIG_CMD_READLINE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_MEMTEST=y @@ -64,6 +74,7 @@ CONFIG_CMD_CLK=y CONFIG_CMD_DETECT=y CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_WD=y @@ -77,19 +88,50 @@ CONFIG_CMD_OF_FIXUP_STATUS=y CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y CONFIG_CMD_DHRYSTONE=y CONFIG_NET=y CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_FASTBOOT=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_DRIVER_NET_MACB=y CONFIG_DRIVER_NET_DESIGNWARE=y CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y +CONFIG_DRIVER_NET_VIRTIO=y CONFIG_MICREL_PHY=y CONFIG_SPI_MEM=y CONFIG_DRIVER_SPI_GPIO=y +CONFIG_SPI_SIFIVE=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_RAW_DEVICE=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_MTDRAM=y +CONFIG_DRIVER_CFI=y +CONFIG_DRIVER_CFI_BANK_WIDTH_8=y +CONFIG_DISK=y +CONFIG_DISK_WRITE=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_BOCHS_PCI=y +CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y CONFIG_MCI=y +CONFIG_MCI_SPI=y CONFIG_MCI_DW=y CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_STATE_DRV=y +CONFIG_EEPROM_AT24=y +CONFIG_VIRTIO_INPUT=y CONFIG_SRAM=y CONFIG_STARFIVE_PWRSEQ=y CONFIG_LED=y @@ -99,6 +141,8 @@ CONFIG_LED_TRIGGERS=y CONFIG_WATCHDOG=y CONFIG_STARFIVE_WDT=y CONFIG_HWRNG=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_GPIO_SIFIVE=y CONFIG_HW_RANDOM_STARFIVE=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_STARFIVE=y @@ -106,12 +150,16 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_NVMEM=y CONFIG_NVMEM_RMEM=y CONFIG_STARFIVE_OTP=y +CONFIG_PCI_ECAM_GENERIC=y +CONFIG_BLK_DEV_NVME=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_NVMEM_REBOOT_MODE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_HTIF_POWEROFF=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_VIRTIO_MMIO=y # CONFIG_VIRTIO_MENU is not set CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y @@ -128,4 +176,8 @@ CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DECOMPRESS=y CONFIG_BASE64=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DIGEST_CRC32_GENERIC=y +CONFIG_IMD_TARGET=y +CONFIG_BAREBOXENV_TARGET=y +CONFIG_BAREBOXCRC32_TARGET=y diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig deleted file mode 100644 index 59cfebf194..0000000000 --- a/arch/riscv/configs/sifive_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_ARCH_RV64I=y -CONFIG_SOC_SIFIVE=y -CONFIG_BOARD_HIFIVE=y -CONFIG_BOARD_RISCV_GENERIC_DT=y -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_STACK_SIZE=0x20000 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PANIC_HANG=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_IMD_TARGET=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_PBL_CONSOLE=y -CONFIG_PARTITION_DISK_EFI=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y -CONFIG_STATE=y -CONFIG_STATE_CRYPTO=y -CONFIG_BOOTCHOOSER=y -CONFIG_RESET_SOURCE=y -CONFIG_MACHINE_ID=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_IMD=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_POLLER=y -CONFIG_CMD_SLICE=y -CONFIG_CMD_GO=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_RESET=y -CONFIG_CMD_BOOTCHOOSER=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_CMP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_PING=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_FBTEST=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_2048=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_DIFF=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OF_OVERLAY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_NET_FASTBOOT=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_SERIAL_SIFIVE=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DRIVER_SPI_GPIO=y -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_M25P80=y -CONFIG_DRIVER_CFI=y -CONFIG_DRIVER_CFI_BANK_WIDTH_8=y -CONFIG_DISK=y -CONFIG_DISK_WRITE=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIDEO=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 -CONFIG_EEPROM_AT24=y -CONFIG_HWRNG=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_GPIO_SIFIVE=y -# CONFIG_PINCTRL is not set -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_VIRTIO_MMIO=y -CONFIG_FS_EXT4=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_FS_UIMAGEFS=y -CONFIG_FS_PSTORE=y -CONFIG_FS_SQUASHFS=y -CONFIG_ZLIB=y -CONFIG_BZLIB=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DECOMPRESS=y -CONFIG_BASE64=y -CONFIG_DIGEST_CRC32_GENERIC=y diff --git a/arch/riscv/configs/virt32_defconfig b/arch/riscv/configs/virt32_defconfig index 218fee57b7..b5044cf34a 100644 --- a/arch/riscv/configs/virt32_defconfig +++ b/arch/riscv/configs/virt32_defconfig @@ -10,14 +10,15 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y -CONFIG_IMD_TARGET=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y -CONFIG_POLLER=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_IKCONFIG=y CONFIG_STATE=y CONFIG_STATE_CRYPTO=y CONFIG_BOOTCHOOSER=y @@ -47,6 +48,9 @@ CONFIG_CMD_SHA1SUM=y CONFIG_CMD_SHA256SUM=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y CONFIG_CMD_SPLASH=y CONFIG_CMD_FBTEST=y @@ -71,9 +75,17 @@ CONFIG_CMD_OF_FIXUP_STATUS=y CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y CONFIG_CMD_DHRYSTONE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_FASTBOOT=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_VIRTIO_CONSOLE=y +CONFIG_DRIVER_NET_VIRTIO=y CONFIG_DRIVER_SPI_GPIO=y CONFIG_I2C=y CONFIG_I2C_GPIO=y @@ -81,6 +93,7 @@ CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set CONFIG_MTD_CONCAT=y CONFIG_MTD_M25P80=y +CONFIG_MTD_MTDRAM=y CONFIG_DRIVER_CFI=y CONFIG_DRIVER_CFI_BANK_WIDTH_8=y CONFIG_DISK=y @@ -88,18 +101,26 @@ CONFIG_DISK_WRITE=y CONFIG_VIRTIO_BLK=y CONFIG_VIDEO=y CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_BOCHS_PCI=y CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_STATE_DRV=y CONFIG_EEPROM_AT24=y +CONFIG_VIRTIO_INPUT=y CONFIG_HWRNG=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_PINCTRL is not set +CONFIG_PCI_ECAM_GENERIC=y +CONFIG_BLK_DEV_NVME=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_HTIF_POWEROFF=y CONFIG_VIRTIO_MMIO=y CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y @@ -114,3 +135,6 @@ CONFIG_XZ_DECOMPRESS=y CONFIG_BASE64=y CONFIG_LZO_DECOMPRESS=y CONFIG_DIGEST_CRC32_GENERIC=y +CONFIG_IMD_TARGET=y +CONFIG_BAREBOXENV_TARGET=y +CONFIG_BAREBOXCRC32_TARGET=y diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/virt64_defconfig deleted file mode 100644 index 04a4f1e2f4..0000000000 --- a/arch/riscv/configs/virt64_defconfig +++ /dev/null @@ -1,117 +0,0 @@ -CONFIG_SOC_VIRT=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_STACK_SIZE=0x20000 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PANIC_HANG=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_IMD_TARGET=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_PBL_CONSOLE=y -CONFIG_PARTITION_DISK_EFI=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y -CONFIG_POLLER=y -CONFIG_STATE=y -CONFIG_STATE_CRYPTO=y -CONFIG_BOOTCHOOSER=y -CONFIG_RESET_SOURCE=y -CONFIG_MACHINE_ID=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_IMD=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_POLLER=y -CONFIG_CMD_SLICE=y -CONFIG_CMD_GO=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_RESET=y -CONFIG_CMD_BOOTCHOOSER=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_CMP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_FBTEST=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_2048=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_DIFF=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OF_OVERLAY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_DRIVER_SPI_GPIO=y -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_M25P80=y -CONFIG_DRIVER_CFI=y -CONFIG_DRIVER_CFI_BANK_WIDTH_8=y -CONFIG_DISK=y -CONFIG_DISK_WRITE=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIDEO=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 -CONFIG_EEPROM_AT24=y -CONFIG_HWRNG=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_GPIO_GENERIC_PLATFORM=y -# CONFIG_PINCTRL is not set -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_VIRTIO_MMIO=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_FS_UIMAGEFS=y -CONFIG_FS_PSTORE=y -CONFIG_FS_SQUASHFS=y -CONFIG_ZLIB=y -CONFIG_BZLIB=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DECOMPRESS=y -CONFIG_BASE64=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DIGEST_CRC32_GENERIC=y diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 717baaaaa7..d79bafc6f1 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -2,6 +2,8 @@ obj-y += core.o time.o obj-$(CONFIG_HAS_DMA) += dma.o +ifeq ($(CONFIG_RISCV_EXCEPTIONS),y) obj-pbl-$(CONFIG_RISCV_M_MODE) += mtrap.o obj-pbl-$(CONFIG_RISCV_S_MODE) += strap.o obj-pbl-y += interrupts.o +endif diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c index 1d5902a51f..38aa402758 100644 --- a/arch/riscv/cpu/core.c +++ b/arch/riscv/cpu/core.c @@ -32,8 +32,8 @@ static int riscv_request_stack(void) } coredevice_initcall(riscv_request_stack); -static struct device_d timer_dev; -static struct device_d serial_sbi_dev; +static struct device timer_dev; +static struct device serial_sbi_dev; static s64 hartid; @@ -43,7 +43,7 @@ static int riscv_fixup_cpus(struct device_node *root, void *context) { struct device_node *cpus_node, *np, *tmp; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; @@ -60,14 +60,14 @@ static int riscv_fixup_cpus(struct device_node *root, void *context) return 0; } -static int riscv_probe(struct device_d *parent) +static int riscv_probe(struct device *parent) { int ret; /* Each hart has a timer, but we only need one */ if (IS_ENABLED(CONFIG_RISCV_TIMER) && !timer_dev.parent) { timer_dev.id = DEVICE_ID_SINGLE; - timer_dev.device_node = parent->device_node; + timer_dev.of_node = parent->of_node; timer_dev.parent = parent; dev_set_name(&timer_dev, "riscv-timer"); @@ -78,7 +78,7 @@ static int riscv_probe(struct device_d *parent) if (IS_ENABLED(CONFIG_SERIAL_SBI) && !serial_sbi_dev.parent) { serial_sbi_dev.id = DEVICE_ID_SINGLE; - serial_sbi_dev.device_node = 0; + serial_sbi_dev.of_node = 0; serial_sbi_dev.parent = parent; dev_set_name(&serial_sbi_dev, "riscv-serial-sbi"); @@ -98,8 +98,9 @@ static struct of_device_id riscv_dt_ids[] = { { .compatible = "riscv", }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, riscv_dt_ids); -static struct driver_d riscv_driver = { +static struct driver riscv_driver = { .name = "riscv", .probe = riscv_probe, .of_compatible = riscv_dt_ids, diff --git a/arch/riscv/cpu/dma.c b/arch/riscv/cpu/dma.c index 5a4d714e5e..511170aaa4 100644 --- a/arch/riscv/cpu/dma.c +++ b/arch/riscv/cpu/dma.c @@ -52,23 +52,24 @@ void dma_set_ops(const struct dma_ops *ops) dma_ops = ops; } -void dma_sync_single_for_cpu(dma_addr_t address, size_t size, enum dma_data_direction dir) +void arch_sync_dma_for_cpu(void *vaddr, size_t size, + enum dma_data_direction dir) { - /* - * FIXME: This function needs a device argument to support non 1:1 mappings - */ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; + if (dir != DMA_TO_DEVICE) - dma_ops->inv_range(address, address + size); + dma_ops->inv_range(start, end); } -void dma_sync_single_for_device(dma_addr_t address, size_t size, enum dma_data_direction dir) +void arch_sync_dma_for_device(void *vaddr, size_t size, + enum dma_data_direction dir) { - /* - * FIXME: This function needs a device argument to support non 1:1 mappings - */ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; if (dir == DMA_FROM_DEVICE) - dma_ops->inv_range(address, address + size); + dma_ops->inv_range(start, end); else - dma_ops->flush_range(address, address + size); + dma_ops->flush_range(start, end); } diff --git a/arch/riscv/cpu/interrupts.c b/arch/riscv/cpu/interrupts.c index 0e8951b619..0bb56d441d 100644 --- a/arch/riscv/cpu/interrupts.c +++ b/arch/riscv/cpu/interrupts.c @@ -14,6 +14,7 @@ #include <asm/ptrace.h> #include <asm/irq.h> #include <asm/csr.h> +#include <asm/unwind.h> #include <abort.h> #include <pbl.h> @@ -81,6 +82,8 @@ static void report_trap(const struct pt_regs *regs) regs->epc, regs->ra, regs->badaddr); show_regs(regs); + + unwind_backtrace(regs); } @@ -122,7 +125,7 @@ unsigned long handle_trap(struct pt_regs *regs) goto skip; if (regs->cause == 2) { /* illegal instruction */ - switch(*(unsigned long *)regs->epc) { + switch(*(u32 *)regs->epc) { case 0x0000100f: /* fence.i */ goto skip; default: diff --git a/arch/riscv/dts/.gitignore b/arch/riscv/dts/.gitignore deleted file mode 100644 index 077903c50a..0000000000 --- a/arch/riscv/dts/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*dtb* diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17d7d249e4..a3c8fbd9d0 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -10,4 +10,4 @@ pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \ pbl-$(CONFIG_BOARD_BEAGLEV) += jh7100-beaglev-starlight.dtb.o pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o -clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts index 65694bfd24..3b82c16ff0 100644 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -1,3 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR X11 */ #include <riscv/sifive/hifive-unleashed-a00.dts> + +/* probing on QEMU v5.2.0 triggers load access fault @0x10040014 */ +&qspi0 { status = "disabled"; }; +&qspi2 { status = "disabled"; }; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts index b8793e9105..24a4c798a9 100644 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -1,3 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 OR X11 */ #include <riscv/sifive/hifive-unmatched-a00.dts> + +/* probing on QEMU v5.2.0 triggers load access fault @0x10040014 */ +&qspi0 { status = "disabled"; }; +&qspi1 { status = "disabled"; }; +&spi0 { status = "disabled"; }; diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi index e3990582af..b11801553b 100644 --- a/arch/riscv/dts/jh7100.dtsi +++ b/arch/riscv/dts/jh7100.dtsi @@ -212,6 +212,7 @@ #clock-cells = <1>; compatible = "simple-bus"; ranges; + dma-noncoherent; intram0: sram@18000000 { compatible = "mmio-sram"; diff --git a/arch/riscv/include/asm/asm-offsets.h b/arch/riscv/include/asm/asm-offsets.h index d370ee36a1..33db5a47e5 100644 --- a/arch/riscv/include/asm/asm-offsets.h +++ b/arch/riscv/include/asm/asm-offsets.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <generated/asm-offsets.h> diff --git a/arch/riscv/include/asm/barebox-riscv-head.h b/arch/riscv/include/asm/barebox-riscv-head.h index a4c33472cd..4d62c20d1b 100644 --- a/arch/riscv/include/asm/barebox-riscv-head.h +++ b/arch/riscv/include/asm/barebox-riscv-head.h @@ -23,6 +23,7 @@ ".ascii \"" magic2 "\"\n" /* magic 2 */ \ ".word 0\n" /* reserved (PE-COFF offset) */ \ "1:\n" \ + "li fp, 0\n" \ ) #define __barebox_riscv_header(instr, load_offset, version, magic1, magic2) \ diff --git a/arch/riscv/include/asm/barebox-riscv.h b/arch/riscv/include/asm/barebox-riscv.h index abb3202427..db6ff0ea71 100644 --- a/arch/riscv/include/asm/barebox-riscv.h +++ b/arch/riscv/include/asm/barebox-riscv.h @@ -20,14 +20,8 @@ #include <asm/sections.h> #include <asm/barebox-riscv-head.h> #include <asm/system.h> - -unsigned long get_runtime_offset(void); - -void setup_c(void); -void relocate_to_current_adr(void); -void relocate_to_adr(unsigned long target); - -void sync_caches_for_execution(void); +#include <asm/cache.h> +#include <asm/reloc.h> void __noreturn __naked barebox_riscv_entry(unsigned long membase, unsigned long memsize, void *boarddata, unsigned int flags); diff --git a/arch/riscv/include/asm/barebox.lds.h b/arch/riscv/include/asm/barebox.lds.h new file mode 100644 index 0000000000..0fa05df6ff --- /dev/null +++ b/arch/riscv/include/asm/barebox.lds.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BAREBOX_OUTPUT_ARCH "riscv" +#ifdef CONFIG_64BIT +#define BAREBOX_OUTPUT_FORMAT "elf64-littleriscv" +#else +#define BAREBOX_OUTPUT_FORMAT "elf32-littleriscv" +#endif + +#include <asm-generic/barebox.lds.h> diff --git a/arch/riscv/include/asm/bitsperlong.h b/arch/riscv/include/asm/bitsperlong.h index 6dc0bb0c13..bf000a04cc 100644 --- a/arch/riscv/include/asm/bitsperlong.h +++ b/arch/riscv/include/asm/bitsperlong.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <asm-generic/bitsperlong.h> diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h index 0be826927b..36dfd37524 100644 --- a/arch/riscv/include/asm/byteorder.h +++ b/arch/riscv/include/asm/byteorder.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_RISCV_BYTEORDER_H #define _ASM_RISCV_BYTEORDER_H diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h new file mode 100644 index 0000000000..c787f89001 --- /dev/null +++ b/arch/riscv/include/asm/cache.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +#include <asm/vendorid_list.h> + +static inline void thead_local_flush_icache_all(void) +{ + /* + * According [1] "13.3 Example of cache settings" + * [1]: https://github.com/T-head-Semi/openc906/blob/main/ \ + * doc/openc906%20datasheet.pd + */ + __asm__ volatile (".long 0x0100000b" ::: "memory"); /* th.icache.iall */ + __asm__ volatile (".long 0x01b0000b" ::: "memory"); /* th.sync.is */ +} + +static inline void local_flush_icache_all(void) +{ +#ifdef CONFIG_HAS_CACHE + switch(riscv_vendor_id()) { + case THEAD_VENDOR_ID: + thead_local_flush_icache_all(); + break; + default: + __asm__ volatile ("fence.i" ::: "memory"); + } +#endif +} + +#define sync_caches_for_execution sync_caches_for_execution +void sync_caches_for_execution(void); + +#include <asm-generic/cache.h> + +#endif /* _ASM_RISCV_CACHEFLUSH_H */ diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h deleted file mode 100644 index 9ff25740c6..0000000000 --- a/arch/riscv/include/asm/cacheflush.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Regents of the University of California - */ - -#ifndef _ASM_RISCV_CACHEFLUSH_H -#define _ASM_RISCV_CACHEFLUSH_H - -static inline void local_flush_icache_all(void) -{ -#ifdef HAS_CACHE - asm volatile ("fence.i" ::: "memory"); -#endif -} - -#endif /* _ASM_RISCV_CACHEFLUSH_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 1a15089cae..8bba809e45 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -13,13 +13,12 @@ /* Status register flags */ #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ -#ifdef CONFIG_RISCV_PRIV_1_9 -#define SR_PUM _AC(0x00040000, UL) /* Protect User Memory Access */ -#else +#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ -#endif #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) @@ -33,22 +32,6 @@ #define SR_XS_CLEAN _AC(0x00010000, UL) #define SR_XS_DIRTY _AC(0x00018000, UL) -#ifdef CONFIG_RISCV_PRIV_1_9 -#define SR_VM _AC(0x1F000000, UL) /* Virtualization Management */ -#define SR_VM_MODE_BARE _AC(0x00000000, UL) /* No translation or protection */ -#define SR_VM_MODE_BB _AC(0x01000000, UL) /* Single base-and-bound */ -/* Separate instruction and data base-and-bound */ -#define SR_VM_MODE_BBID _AC(0x02000000, UL) -#ifndef CONFIG_64BIT -#define SR_VM_MODE_32 _AC(0x08000000, UL) -#define SR_VM_MODE SR_VM_MODE_32 -#else -#define SR_VM_MODE_39 _AC(0x09000000, UL) -#define SR_VM_MODE_48 _AC(0x0A000000, UL) -#define SR_VM_MODE SR_VM_MODE_39 -#endif -#endif - #ifndef CONFIG_64BIT #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ #else @@ -56,51 +39,127 @@ #endif /* SATP flags */ -#ifndef CONFIG_RISCV_PRIV_1_9 #ifndef CONFIG_64BIT #define SATP_PPN _AC(0x003FFFFF, UL) #define SATP_MODE_32 _AC(0x80000000, UL) #define SATP_MODE SATP_MODE_32 +#define SATP_ASID_BITS 9 +#define SATP_ASID_SHIFT 22 +#define SATP_ASID_MASK _AC(0x1FF, UL) #else #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) #define SATP_MODE_39 _AC(0x8000000000000000, UL) #define SATP_MODE SATP_MODE_39 -#endif +#define SATP_ASID_BITS 16 +#define SATP_ASID_SHIFT 44 +#define SATP_ASID_MASK _AC(0xFFFF, UL) #endif -/* SCAUSE */ -#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) +/* Exception cause high bit - is an interrupt if set */ +#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) #define IRQ_U_SOFT 0 +/* Interrupt causes (minus the high bit) */ #define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_U_EXT 8 #define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +/* Exception causes */ #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 +#define EXC_INST_ILLEGAL 2 #define EXC_BREAKPOINT 3 #define EXC_LOAD_ACCESS 5 #define EXC_STORE_ACCESS 7 #define EXC_SYSCALL 8 +#define EXC_HYPERVISOR_SYSCALL 9 +#define EXC_SUPERVISOR_SYSCALL 10 #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +#define EXC_INST_GUEST_PAGE_FAULT 20 +#define EXC_LOAD_GUEST_PAGE_FAULT 21 +#define EXC_VIRTUAL_INST_FAULT 22 +#define EXC_STORE_GUEST_PAGE_FAULT 23 + +/* PMP configuration */ +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_A_TOR 0x08 +#define PMP_A_NA4 0x10 +#define PMP_A_NAPOT 0x18 +#define PMP_L 0x80 + +/* HSTATUS flags */ +#ifdef CONFIG_64BIT +#define HSTATUS_VSXL _AC(0x300000000, UL) +#define HSTATUS_VSXL_SHIFT 32 +#endif +#define HSTATUS_VTSR _AC(0x00400000, UL) +#define HSTATUS_VTW _AC(0x00200000, UL) +#define HSTATUS_VTVM _AC(0x00100000, UL) +#define HSTATUS_VGEIN _AC(0x0003f000, UL) +#define HSTATUS_VGEIN_SHIFT 12 +#define HSTATUS_HU _AC(0x00000200, UL) +#define HSTATUS_SPVP _AC(0x00000100, UL) +#define HSTATUS_SPV _AC(0x00000080, UL) +#define HSTATUS_GVA _AC(0x00000040, UL) +#define HSTATUS_VSBE _AC(0x00000020, UL) + +/* HGATP flags */ +#define HGATP_MODE_OFF _AC(0, UL) +#define HGATP_MODE_SV32X4 _AC(1, UL) +#define HGATP_MODE_SV39X4 _AC(8, UL) +#define HGATP_MODE_SV48X4 _AC(9, UL) + +#define HGATP32_MODE_SHIFT 31 +#define HGATP32_VMID_SHIFT 22 +#define HGATP32_VMID_MASK _AC(0x1FC00000, UL) +#define HGATP32_PPN _AC(0x003FFFFF, UL) + +#define HGATP64_MODE_SHIFT 60 +#define HGATP64_VMID_SHIFT 44 +#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) +#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) + +#define HGATP_PAGE_SHIFT 12 -/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ -#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT) -#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) -#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) -#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +#ifdef CONFIG_64BIT +#define HGATP_PPN HGATP64_PPN +#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT +#define HGATP_VMID_MASK HGATP64_VMID_MASK +#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT +#else +#define HGATP_PPN HGATP32_PPN +#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT +#define HGATP_VMID_MASK HGATP32_VMID_MASK +#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT +#endif + +/* VSIP & HVIP relation */ +#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) +#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ + (_AC(1, UL) << IRQ_S_TIMER) | \ + (_AC(1, UL) << IRQ_S_EXT)) -#define CSR_FCSR 0x003 +/* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 + #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 @@ -110,40 +169,90 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 -#ifdef CONFIG_RISCV_PRIV_1_9 -#define CSR_SPTBR 0x180 -#else #define CSR_SATP 0x180 -#endif + +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HGEIP 0xe12 + #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 -#ifdef CONFIG_RISCV_PRIV_1_9 -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHCOUNTEREN 0x322 -#else -#define CSR_MCOUNTEREN 0x306 -#endif #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 -#ifdef CONFIG_RISCV_PRIV_1_9 -#define CSR_MBASE 0x380 -#define CSR_MBOUND 0x381 -#define CSR_MIBASE 0x382 -#define CSR_MIBOUND 0x383 -#define CSR_MDBASE 0x384 -#define CSR_MDBOUND 0x385 -#endif -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPADDR0 0x3b0 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#ifdef CONFIG_RISCV_M_MODE +# define CSR_STATUS CSR_MSTATUS +# define CSR_IE CSR_MIE +# define CSR_TVEC CSR_MTVEC +# define CSR_SCRATCH CSR_MSCRATCH +# define CSR_EPC CSR_MEPC +# define CSR_CAUSE CSR_MCAUSE +# define CSR_TVAL CSR_MTVAL +# define CSR_IP CSR_MIP + +# define SR_IE SR_MIE +# define SR_PIE SR_MPIE +# define SR_PP SR_MPP + +# define RV_IRQ_SOFT IRQ_M_SOFT +# define RV_IRQ_TIMER IRQ_M_TIMER +# define RV_IRQ_EXT IRQ_M_EXT +#else /* CONFIG_RISCV_M_MODE */ +# define CSR_STATUS CSR_SSTATUS +# define CSR_IE CSR_SIE +# define CSR_TVEC CSR_STVEC +# define CSR_SCRATCH CSR_SSCRATCH +# define CSR_EPC CSR_SEPC +# define CSR_CAUSE CSR_SCAUSE +# define CSR_TVAL CSR_STVAL +# define CSR_IP CSR_SIP + +# define SR_IE SR_SIE +# define SR_PIE SR_SPIE +# define SR_PP SR_SPP + +# define RV_IRQ_SOFT IRQ_S_SOFT +# define RV_IRQ_TIMER IRQ_S_TIMER +# define RV_IRQ_EXT IRQ_S_EXT +#endif /* CONFIG_RISCV_M_MODE */ + +/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ +#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) +#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) +#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h index a3b9c1c4bc..34294b09dd 100644 --- a/arch/riscv/include/asm/debug_ll.h +++ b/arch/riscv/include/asm/debug_ll.h @@ -17,20 +17,31 @@ #if defined CONFIG_DEBUG_ERIZO #define DEBUG_LL_UART_ADDR 0x90000000 #define DEBUG_LL_UART_CLK (24000000 / 16) +#define DEBUG_LL_UART_SHIFT 2 +#define DEBUG_LL_UART_IOSIZE32 #elif defined CONFIG_DEBUG_STARFIVE #define DEBUG_LL_UART_ADDR 0x12440000 #define DEBUG_LL_UART_CLK (100000000 / 16) -#endif - #define DEBUG_LL_UART_SHIFT 2 #define DEBUG_LL_UART_IOSIZE32 +#elif defined CONFIG_DEBUG_RISCV_VIRT +#define DEBUG_LL_UART_ADDR 0x10000000 +#define DEBUG_LL_UART_CLK (58982400 / 16) +#define DEBUG_LL_UART_SHIFT 0 +#define DEBUG_LL_UART_IOSIZE8 +#elif defined CONFIG_DEBUG_SUN20I +#define DEBUG_LL_UART_ADDR 0x2500000 +#define DEBUG_LL_UART_CLK (24000000 / 16) +#define DEBUG_LL_UART_SHIFT 2 +#define DEBUG_LL_UART_IOSIZE32 +#endif #define DEBUG_LL_UART_BPS CONFIG_BAUDRATE #define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) #include <asm/debug_ll_ns16550.h> -#elif defined CONFIG_DEBUG_SIFIVE +#elif defined CONFIG_DEBUG_SIFIVE && !defined __ASSEMBLY__ #include <io.h> @@ -47,6 +58,17 @@ static inline void PUTC_LL(char ch) #include <asm/debug_ll_litex.h> +#elif defined CONFIG_DEBUG_RISCVEMU_HTIF + +#include <asm/htif.h> + +#ifndef __ASSEMBLY__ +static inline void PUTC_LL(char ch) +{ + htif_putc(IOMEM(HTIF_DEFAULT_BASE_ADDR), ch); +} +#endif + #endif #ifndef debug_ll_init diff --git a/arch/riscv/include/asm/debug_ll_litex.h b/arch/riscv/include/asm/debug_ll_litex.h index 2fcdd9b0ec..295477fc10 100644 --- a/arch/riscv/include/asm/debug_ll_litex.h +++ b/arch/riscv/include/asm/debug_ll_litex.h @@ -90,11 +90,11 @@ static inline void PUTC_LL(char ch) li t0, DEBUG_LL_UART_ADDR /* get line status and check for data present */ - lbu s0, UART_RXEMPTY(t0) - bnez s0, 243f - li s0, 1 + lbu s1, UART_RXEMPTY(t0) + bnez s1, 243f + li s1, 1 j 244f -243: li s0, 0 +243: li s1, 0 244: nop #endif /* CONFIG_DEBUG_LL */ .endm @@ -109,10 +109,10 @@ static inline void PUTC_LL(char ch) debug_ll_tstc /* try again */ - beqz s0, 204b + beqz s1, 204b /* read a character */ - lb s0, UART_RXTX(t0) + lb s1, UART_RXTX(t0) li t1, UART_EV_RX sb t1, UART_EV_PENDING(t0) diff --git a/arch/riscv/include/asm/debug_ll_ns16550.h b/arch/riscv/include/asm/debug_ll_ns16550.h index e208ef4fb1..47f0be328c 100644 --- a/arch/riscv/include/asm/debug_ll_ns16550.h +++ b/arch/riscv/include/asm/debug_ll_ns16550.h @@ -143,8 +143,8 @@ static inline void debug_ll_ns16550_init(void) li t0, DEBUG_LL_UART_ADDR /* get line status and check for data present */ - UART_REG_L s0, UART_LSR(DEBUG_LL_UART_SHIFT)(t0) - andi s0, s0, UART_LSR_DR + UART_REG_L s1, UART_LSR(DEBUG_LL_UART_SHIFT)(t0) + andi s1, s1, UART_LSR_DR #endif /* CONFIG_DEBUG_LL */ .endm @@ -159,10 +159,10 @@ static inline void debug_ll_ns16550_init(void) debug_ll_tstc /* try again */ - beqz s0, 204b + beqz s1, 204b /* read a character */ - UART_REG_L s0, UART_RBR(DEBUG_LL_UART_SHIFT)(t0) + UART_REG_L s1, UART_RBR(DEBUG_LL_UART_SHIFT)(t0) #endif /* CONFIG_DEBUG_LL */ .endm diff --git a/arch/riscv/include/asm/htif.h b/arch/riscv/include/asm/htif.h new file mode 100644 index 0000000000..b35afdd98e --- /dev/null +++ b/arch/riscv/include/asm/htif.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __ASM_HTIF_LL__ +#define __ASM_HTIF_LL__ + +#define HTIF_DEFAULT_BASE_ADDR 0x40008000 + +#define HTIF_DEV_SYSCALL 0 +#define HTIF_CMD_SYSCALL 0 + +#define HTIF_DEV_CONSOLE 1 /* blocking character device */ +#define HTIF_CMD_GETCHAR 0 +#define HTIF_CMD_PUTCHAR 1 + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> +#include <io-64-nonatomic-lo-hi.h> + +static inline void __htif_tohost(void __iomem *htif, u8 device, u8 command, u64 arg) +{ + writeq(((u64)device << 56) | ((u64)command << 48) | arg, htif); +} + +static inline void htif_tohost(u8 device, u8 command, u64 arg) +{ + __htif_tohost(IOMEM(HTIF_DEFAULT_BASE_ADDR), device, command, arg); +} + +static inline void htif_putc(void __iomem *base, int c) +{ + __htif_tohost(base, HTIF_DEV_CONSOLE, HTIF_CMD_PUTCHAR, c); +} + +#endif + +#endif diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 795e670e3b..76d66c0a3b 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_RISCV_IO_H #define __ASM_RISCV_IO_H @@ -5,14 +7,4 @@ #include <asm-generic/io.h> -static inline void *phys_to_virt(unsigned long phys) -{ - return (void *)phys; -} - -static inline unsigned long virt_to_phys(volatile void *mem) -{ - return (unsigned long)mem; -} - #endif /* __ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 95af871420..1c2646ebb3 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_MMU_H #define __ASM_MMU_H diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h new file mode 100644 index 0000000000..dd18499a37 --- /dev/null +++ b/arch/riscv/include/asm/pci.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_PCI_H +#define __ASM_PCI_H + +#define pcibios_assign_all_busses() 1 + +#endif diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h index 22cae6230c..feaed42471 100644 --- a/arch/riscv/include/asm/posix_types.h +++ b/arch/riscv/include/asm/posix_types.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <asm-generic/posix_types.h> diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index b5e792f666..319c50f946 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -61,7 +61,7 @@ struct pt_regs { #define MAX_REG_OFFSET offsetof(struct pt_regs, cause) /* Helpers for working with the instruction pointer */ -static inline unsigned long instruction_pointer(struct pt_regs *regs) +static inline unsigned long instruction_pointer(const struct pt_regs *regs) { return regs->epc; } @@ -74,7 +74,7 @@ static inline void instruction_pointer_set(struct pt_regs *regs, #define profile_pc(regs) instruction_pointer(regs) /* Helpers for working with the user stack pointer */ -static inline unsigned long user_stack_pointer(struct pt_regs *regs) +static inline unsigned long user_stack_pointer(const struct pt_regs *regs) { return regs->sp; } @@ -85,13 +85,13 @@ static inline void user_stack_pointer_set(struct pt_regs *regs, } /* Valid only for Kernel mode traps. */ -static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +static inline unsigned long kernel_stack_pointer(const struct pt_regs *regs) { return regs->sp; } /* Helpers for working with the frame pointer */ -static inline unsigned long frame_pointer(struct pt_regs *regs) +static inline unsigned long frame_pointer(const struct pt_regs *regs) { return regs->s0; } @@ -101,7 +101,7 @@ static inline void frame_pointer_set(struct pt_regs *regs, regs->s0 = val; } -static inline unsigned long regs_return_value(struct pt_regs *regs) +static inline unsigned long regs_return_value(const struct pt_regs *regs) { return regs->a0; } diff --git a/arch/riscv/include/asm/reloc.h b/arch/riscv/include/asm/reloc.h new file mode 100644 index 0000000000..9a59326cad --- /dev/null +++ b/arch/riscv/include/asm/reloc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_RELOC_H_ +#define _ASM_RELOC_H_ + +unsigned long get_runtime_offset(void); + +void relocate_to_current_adr(void); +void relocate_to_adr(unsigned long target); + +void setup_c(void); + +#include <asm-generic/reloc.h> + +#endif /* _BAREBOX_RISCV_H_ */ diff --git a/arch/riscv/include/asm/riscv_nmon.h b/arch/riscv/include/asm/riscv_nmon.h index 8a44e216d7..3e349025fe 100644 --- a/arch/riscv/include/asm/riscv_nmon.h +++ b/arch/riscv/include/asm/riscv_nmon.h @@ -84,7 +84,7 @@ nmon_main: debug_ll_getc li a0, 'q' - bne s0, a0, 3f + bne s1, a0, 3f jal a2, _nmon_outc_a0 @@ -92,13 +92,13 @@ nmon_main: 3: li a0, 'd' - beq s0, a0, nmon_cmd_d + beq s1, a0, nmon_cmd_d li a0, 'w' - beq s0, a0, nmon_cmd_w + beq s1, a0, nmon_cmd_w li a0, 'g' - beq s0, a0, nmon_cmd_g + beq s1, a0, nmon_cmd_g j nmon_main_help @@ -112,7 +112,7 @@ nmon_cmd_d: nmon_outs msg_nl - lw a0, (s0) + lw a0, (s1) debug_ll_outhexw j nmon_main @@ -124,13 +124,13 @@ nmon_cmd_w: jal a2, _nmon_outc_a0 jal a2, _nmon_gethexw - move s2, s0 + move s3, s1 li a0, ' ' jal a2, _nmon_outc_a0 jal a2, _nmon_gethexw - sw s0, 0(s2) + sw s1, 0(s3) j nmon_main nmon_cmd_g: @@ -140,11 +140,11 @@ nmon_cmd_g: jal a2, _nmon_outc_a0 jal a2, _nmon_gethexw - move s2, s0 + move s3, s1 nmon_outs msg_nl - jalr s2 + jalr s3 j nmon_main _nmon_outc_a0: @@ -169,37 +169,37 @@ _nmon_gethexw: _get_hex_digit: debug_ll_getc - li s1, CODE_ESC - beq s0, s1, nmon_main + li s2, CODE_ESC + beq s1, s2, nmon_main - li s1, '0' - bge s0, s1, 0f + li s2, '0' + bge s1, s2, 0f j _get_hex_digit 0: - li s1, '9' - ble s0, s1, 9f + li s2, '9' + ble s1, s2, 9f - li s1, 'f' - ble s0, s1, 1f + li s2, 'f' + ble s1, s2, 1f j _get_hex_digit 1: - li s1, 'a' - bge s0, s1, 8f + li s2, 'a' + bge s1, s2, 8f j _get_hex_digit -8: /* s0 \in {'a', 'b' ... 'f'} */ - sub a3, s0, s1 +8: /* s1 \in {'a', 'b' ... 'f'} */ + sub a3, s1, s2 addi a3, a3, 0xa j 0f -9: /* s0 \in {'0', '1' ... '9'} */ +9: /* s1 \in {'0', '1' ... '9'} */ li a3, '0' - sub a3, s0, a3 + sub a3, s1, a3 -0: move a0, s0 +0: move a0, s1 debug_ll_outc_a0 sll t2, t2, 4 @@ -212,7 +212,7 @@ _get_hex_digit: j _get_hex_digit 0: - move s0, t2 + move s1, t2 _nmon_jr_ra_exit: jr a2 diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h index 6673648bcd..cea039cc5e 100644 --- a/arch/riscv/include/asm/sections.h +++ b/arch/riscv/include/asm/sections.h @@ -6,6 +6,7 @@ #include <asm-generic/sections.h> #include <linux/types.h> #include <asm/unaligned.h> +#include <asm/reloc.h> extern char __rel_dyn_start[]; extern char __rel_dyn_end[]; @@ -19,7 +20,7 @@ unsigned long get_runtime_offset(void); static inline unsigned int input_data_len(void) { - return get_unaligned((const u32 *)(input_data_end + get_runtime_offset() - 4)); + return get_unaligned((const u32 *)runtime_address(input_data_end) - 1); } #endif diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h index 60a90120b6..0ca746f0f1 100644 --- a/arch/riscv/include/asm/swab.h +++ b/arch/riscv/include/asm/swab.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_SWAB_H #define _ASM_SWAB_H diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index adf856f9e9..f0b6bf2945 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -5,6 +5,8 @@ #ifndef __ASSEMBLY__ +#include <asm/sbi.h> + #define RISCV_MODE_MASK 0x3 enum riscv_mode { RISCV_U_MODE = 0, @@ -13,7 +15,39 @@ enum riscv_mode { RISCV_M_MODE = 3, }; -static inline enum riscv_mode __riscv_mode(u32 flags) +static inline void riscv_set_flags(unsigned flags) +{ + switch (flags & RISCV_MODE_MASK) { + case RISCV_S_MODE: + __asm__ volatile("csrw sscratch, %0" : : "r"(flags)); + break; + case RISCV_M_MODE: + __asm__ volatile("csrw mscratch, %0" : : "r"(flags)); + break; + default: + /* Other modes are not implemented yet */ + break; + } +} + +static inline u32 riscv_get_flags(void) +{ + u32 flags = 0; + + if (IS_ENABLED(CONFIG_RISCV_S_MODE)) + __asm__ volatile("csrr %0, sscratch" : "=r"(flags)); + + /* + * Since we always set the scratch register on the very beginning, a + * empty flags indicates that we are running in M-mode. + */ + if (!flags) + __asm__ volatile("csrr %0, mscratch" : "=r"(flags)); + + return flags; +} + +static inline enum riscv_mode riscv_mode(void) { /* allow non-LTO builds to discard code for unused modes */ if (!IS_ENABLED(CONFIG_RISCV_MULTI_MODE)) { @@ -23,14 +57,14 @@ static inline enum riscv_mode __riscv_mode(u32 flags) return RISCV_S_MODE; } - return flags & RISCV_MODE_MASK; + return riscv_get_flags() & RISCV_MODE_MASK; } -static inline long __riscv_hartid(u32 flags) +static inline long riscv_hartid(void) { long hartid = -1; - switch (__riscv_mode(flags)) { + switch (riscv_mode()) { case RISCV_S_MODE: __asm__ volatile("mv %0, tp\n" : "=r"(hartid) :); break; @@ -42,19 +76,29 @@ static inline long __riscv_hartid(u32 flags) return hartid; } -#ifndef __PBL__ -extern unsigned barebox_riscv_pbl_flags; - -static inline enum riscv_mode riscv_mode(void) +static inline long riscv_vendor_id(void) { - return __riscv_mode(barebox_riscv_pbl_flags); -} + struct sbiret ret; + long id; -static inline long riscv_hartid(void) -{ - return __riscv_hartid(barebox_riscv_pbl_flags); + switch (riscv_mode()) { + case RISCV_M_MODE: + __asm__ volatile("csrr %0, mvendorid\n" : "=r"(id)); + return id; + case RISCV_S_MODE: + /* + * We need to use the sbi_ecall() since it can be that we got + * called without a working stack + */ + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, + 0, 0, 0, 0, 0, 0); + if (!ret.error) + return ret.value; + return -1; + default: + return -1; + } } -#endif #endif diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 1ad5904f91..add1c94fc7 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_RISCV_TYPES_H #define __ASM_RISCV_TYPES_H diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h index c37b71c21e..3bc2930989 100644 --- a/arch/riscv/include/asm/unaligned.h +++ b/arch/riscv/include/asm/unaligned.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_RISCV_UNALIGNED_H #define _ASM_RISCV_UNALIGNED_H diff --git a/arch/riscv/include/asm/unwind.h b/arch/riscv/include/asm/unwind.h index 9e5c8b5420..00f7845147 100644 --- a/arch/riscv/include/asm/unwind.h +++ b/arch/riscv/include/asm/unwind.h @@ -4,6 +4,12 @@ struct pt_regs; -void unwind_backtrace(struct pt_regs *regs); +#if defined CONFIG_RISCV_UNWIND && !defined __PBL__ +void unwind_backtrace(const struct pt_regs *regs); +#else +static inline void unwind_backtrace(const struct pt_regs *regs) +{ +} +#endif #endif diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h new file mode 100644 index 0000000000..cb89af3f07 --- /dev/null +++ b/arch/riscv/include/asm/vendorid_list.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ +#ifndef ASM_VENDOR_LIST_H +#define ASM_VENDOR_LIST_H + +#define SIFIVE_VENDOR_ID 0x489 +#define THEAD_VENDOR_ID 0x5b7 + +#endif diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h new file mode 100644 index 0000000000..74f077d38f --- /dev/null +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + * + * Derived from arch/x86/include/asm/word-at-a-time.h + */ + +#ifndef _ASM_RISCV_WORD_AT_A_TIME_H +#define _ASM_RISCV_WORD_AT_A_TIME_H + + +#include <linux/kernel.h> +#include <linux/bitops.h> + +struct word_at_a_time { + const unsigned long one_bits, high_bits; +}; + +#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) } + +static inline unsigned long has_zero(unsigned long val, + unsigned long *bits, const struct word_at_a_time *c) +{ + unsigned long mask = ((val - c->one_bits) & ~val) & c->high_bits; + *bits = mask; + return mask; +} + +static inline unsigned long prep_zero_mask(unsigned long val, + unsigned long bits, const struct word_at_a_time *c) +{ + return bits; +} + +static inline unsigned long create_zero_mask(unsigned long bits) +{ + bits = (bits - 1) & ~bits; + return bits >> 7; +} + +static inline unsigned long find_zero(unsigned long mask) +{ + return fls64(mask) >> 3; +} + +/* The mask we created is directly usable as a bytemask */ +#define zero_bytemask(mask) (mask) + +#endif /* _ASM_RISCV_WORD_AT_A_TIME_H */ diff --git a/arch/riscv/lib/.gitignore b/arch/riscv/lib/.gitignore index d1165788c9..03987a7009 100644 --- a/arch/riscv/lib/.gitignore +++ b/arch/riscv/lib/.gitignore @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + barebox.lds diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index a399de7399..6932480800 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -4,8 +4,9 @@ extra-y += barebox.lds obj-y += dtb.o obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o -obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o +obj-$(CONFIG_ARCH_HAS_SJLJ) += setjmp.o longjmp.o obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o obj-$(CONFIG_RISCV_SBI) += sbi.o obj-$(CONFIG_CMD_RISCV_CPUINFO) += cpuinfo.o obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_RISCV_UNWIND) += stacktrace.o diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index 4b869690f1..48960e58a6 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /* * Generate definitions needed by assembly language modules. * This code generates raw asm output which is post-processed to extract diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S index 7856b57a52..101615ab05 100644 --- a/arch/riscv/lib/barebox.lds.S +++ b/arch/riscv/lib/barebox.lds.S @@ -11,15 +11,11 @@ * */ -#include <asm-generic/barebox.lds.h> +#include <asm/barebox.lds.h> -OUTPUT_ARCH(riscv) +OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH) ENTRY(start) -#ifdef CONFIG_64BIT -OUTPUT_FORMAT("elf64-littleriscv") -#else -OUTPUT_FORMAT("elf32-littleriscv") -#endif +OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT) SECTIONS { . = 0x0; diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6984f282be..a6655b8aaf 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -36,6 +36,12 @@ static struct image_handler riscv_linux_handler = { .filetype = filetype_riscv_linux_image, }; +static struct image_handler riscv_linux_efi_handler = { + .name = "RISC-V Linux/EFI image", + .bootm = do_bootm_linux, + .filetype = filetype_riscv_efi_linux_image, +}; + static struct image_handler riscv_fit_handler = { .name = "FIT image", .bootm = do_bootm_linux, @@ -51,6 +57,7 @@ static struct image_handler riscv_barebox_handler = { static int riscv_register_image_handler(void) { register_image_handler(&riscv_linux_handler); + register_image_handler(&riscv_linux_efi_handler); register_image_handler(&riscv_barebox_handler); if (IS_ENABLED(CONFIG_FITIMAGE)) diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S index e238b2bfd3..0fe7dfda8e 100644 --- a/arch/riscv/lib/pbl.lds.S +++ b/arch/riscv/lib/pbl.lds.S @@ -2,15 +2,11 @@ /* SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #include <linux/sizes.h> -#include <asm-generic/barebox.lds.h> +#include <asm/barebox.lds.h> #include <asm-generic/memory_layout.h> -OUTPUT_ARCH(riscv) -#ifdef CONFIG_64BIT -OUTPUT_FORMAT("elf64-littleriscv") -#else -OUTPUT_FORMAT("elf32-littleriscv") -#endif +OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH) +OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT) SECTIONS { . = 0x0; @@ -74,8 +70,6 @@ SECTIONS .piggydata : { *(.piggydata) } - __piggydata_end = .; - .image_end : { KEEP(*(.__image_end)) } pbl_image_size = .; diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c index 479d586afd..0c1ec8b488 100644 --- a/arch/riscv/lib/reloc.c +++ b/arch/riscv/lib/reloc.c @@ -5,7 +5,7 @@ #include <linux/linkage.h> #include <asm/sections.h> #include <asm/barebox-riscv.h> -#include <asm/cacheflush.h> +#include <asm/cache.h> #include <debug_ll.h> #include <asm-generic/module.h> @@ -42,9 +42,13 @@ void relocate_to_current_adr(void) if (!offset) return; - dstart = __rel_dyn_start + offset; - dend = __rel_dyn_end + offset; - dynsym = (void *)__dynsym_start + offset; + /* + * We have yet to relocate, so using runtime_address + * to compute the relocated address + */ + dstart = runtime_address(__rel_dyn_start); + dend = runtime_address(__rel_dyn_end); + dynsym = runtime_address(__dynsym_start); for (rela = dstart; (void *)rela < dend; rela++) { unsigned long *fixup; @@ -66,7 +70,7 @@ void relocate_to_current_adr(void) putc_ll(' '); puthex_ll(rela->r_addend); putc_ll('\n'); - panic(""); + __hang(); } } diff --git a/arch/riscv/lib/stacktrace.c b/arch/riscv/lib/stacktrace.c new file mode 100644 index 0000000000..663938019e --- /dev/null +++ b/arch/riscv/lib/stacktrace.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2008 ARM Limited + * Copyright (C) 2014 Regents of the University of California + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + * + * Framepointer assisted stack unwinder + */ + +#include <linux/kernel.h> +#include <printk.h> +#include <asm/unwind.h> +#include <asm/ptrace.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +struct stackframe { + unsigned long fp; + unsigned long ra; +}; + +static void dump_backtrace_entry(unsigned long where, unsigned long from) +{ +#ifdef CONFIG_KALLSYMS + printf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); +#else + printf("Function entered at [<%08lx>] from [<%08lx>]\n", where, from); +#endif +} + +static int unwind_frame(struct stackframe *frame, unsigned long *sp) +{ + unsigned long low, high; + unsigned long fp = frame->fp; + + low = *sp; + high = ALIGN(low, STACK_SIZE); + + if (fp < low || fp > high - sizeof(struct stackframe) || fp & 0x7) + return -1; + + *frame = *((struct stackframe *)fp - 1); + *sp = fp; + + return 0; +} + +void unwind_backtrace(const struct pt_regs *regs) +{ + struct stackframe frame = {}; + register unsigned long current_sp asm ("sp"); + unsigned long sp = 0; + + if (regs) { + frame.fp = frame_pointer(regs); + frame.ra = regs->ra; + } else { + sp = current_sp; + frame.fp = (unsigned long)__builtin_frame_address(0); + frame.ra = (unsigned long)unwind_backtrace; + } + + printf("Call trace:\n"); + for (;;) { + unsigned long where = frame.ra; + int ret; + + ret = unwind_frame(&frame, &sp); + if (ret < 0) + break; + + dump_backtrace_entry(where, frame.ra); + } +} + +void dump_stack(void) +{ + unwind_backtrace(NULL); +} |