diff options
Diffstat (limited to 'dts/Bindings/rtc')
-rw-r--r-- | dts/Bindings/rtc/brcm,brcmstb-waketimer.txt | 20 | ||||
-rw-r--r-- | dts/Bindings/rtc/brcm,brcmstb-waketimer.yaml | 44 | ||||
-rw-r--r-- | dts/Bindings/rtc/epson,rx8900.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/rtc/nvidia,tegra20-rtc.txt | 24 | ||||
-rw-r--r-- | dts/Bindings/rtc/nvidia,tegra20-rtc.yaml | 61 | ||||
-rw-r--r-- | dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml | 9 | ||||
-rw-r--r-- | dts/Bindings/rtc/st,stm32-rtc.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/rtc/sunplus,sp7021-rtc.yaml | 56 |
8 files changed, 171 insertions, 45 deletions
diff --git a/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt b/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt deleted file mode 100644 index d946f28502..0000000000 --- a/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt +++ /dev/null @@ -1,20 +0,0 @@ -Broadcom STB wake-up Timer - -The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the -ability to wake up the system from low-power suspend/standby modes. - -Required properties: -- compatible : should contain "brcm,brcmstb-waketimer" -- reg : the register start and length for the WKTMR block -- interrupts : The TIMER interrupt -- clocks : The phandle to the UPG fixed clock (27Mhz domain) - -Example: - -waketimer@f0411580 { - compatible = "brcm,brcmstb-waketimer"; - reg = <0xf0411580 0x14>; - interrupts = <0x3>; - interrupt-parent = <&aon_pm_l2_intc>; - clocks = <&upg_fixed>; -}; diff --git a/dts/Bindings/rtc/brcm,brcmstb-waketimer.yaml b/dts/Bindings/rtc/brcm,brcmstb-waketimer.yaml new file mode 100644 index 0000000000..9fe079917a --- /dev/null +++ b/dts/Bindings/rtc/brcm,brcmstb-waketimer.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/brcm,brcmstb-waketimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB wake-up Timer + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +description: + The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the + ability to wake up the system from low-power suspend/standby modes. + +allOf: + - $ref: "rtc.yaml#" + +properties: + compatible: + const: brcm,brcmstb-waketimer + + reg: + maxItems: 1 + + interrupts: + description: the TIMER interrupt + maxItems: 1 + + clocks: + description: clock reference in the 27MHz domain + maxItems: 1 + +additionalProperties: false + +examples: + - | + rtc@f0411580 { + compatible = "brcm,brcmstb-waketimer"; + reg = <0xf0411580 0x14>; + interrupts = <0x3>; + interrupt-parent = <&aon_pm_l2_intc>; + clocks = <&upg_fixed>; + }; diff --git a/dts/Bindings/rtc/epson,rx8900.yaml b/dts/Bindings/rtc/epson,rx8900.yaml index 29fe39bb08..d12855e7ff 100644 --- a/dts/Bindings/rtc/epson,rx8900.yaml +++ b/dts/Bindings/rtc/epson,rx8900.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: enum: + - epson,rx8804 - epson,rx8900 - microcrystal,rv8803 diff --git a/dts/Bindings/rtc/nvidia,tegra20-rtc.txt b/dts/Bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e0..0000000000 --- a/dts/Bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip> - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/dts/Bindings/rtc/nvidia,tegra20-rtc.yaml b/dts/Bindings/rtc/nvidia,tegra20-rtc.yaml new file mode 100644 index 0000000000..17d6280e55 --- /dev/null +++ b/dts/Bindings/rtc/nvidia,tegra20-rtc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra real-time clock + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra RTC maintains seconds and milliseconds counters, and five + alarm registers. The alarms and other interrupts may wake the system + from low-power state. + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-rtc + - items: + - enum: + - nvidia,tegra30-rtc + - nvidia,tegra114-rtc + - nvidia,tegra124-rtc + - nvidia,tegra210-rtc + - nvidia,tegra186-rtc + - nvidia,tegra194-rtc + - nvidia,tegra234-rtc + - const: nvidia,tegra20-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + timer@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; + }; diff --git a/dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml b/dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml index 4fba6dba16..6fa7d9fc2d 100644 --- a/dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/dts/Bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -19,7 +19,14 @@ properties: - qcom,pmk8350-rtc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: rtc + - const: alarm interrupts: maxItems: 1 diff --git a/dts/Bindings/rtc/st,stm32-rtc.yaml b/dts/Bindings/rtc/st,stm32-rtc.yaml index 2359f541b7..764717ce18 100644 --- a/dts/Bindings/rtc/st,stm32-rtc.yaml +++ b/dts/Bindings/rtc/st,stm32-rtc.yaml @@ -127,6 +127,7 @@ examples: st,syscfg = <&pwrcfg 0x00 0x100>; }; + - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/stm32mp1-clks.h> rtc@5c004000 { diff --git a/dts/Bindings/rtc/sunplus,sp7021-rtc.yaml b/dts/Bindings/rtc/sunplus,sp7021-rtc.yaml new file mode 100644 index 0000000000..fd1b3e71ff --- /dev/null +++ b/dts/Bindings/rtc/sunplus,sp7021-rtc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/sunplus,sp7021-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Real Time Clock controller + +maintainers: + - Vincent Shih <vincent.sunplus@gmail.com> + +properties: + compatible: + const: sunplus,sp7021-rtc + + reg: + maxItems: 1 + + reg-names: + items: + - const: rtc + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rtc: serial@9c003a00 { + compatible = "sunplus,sp7021-rtc"; + reg = <0x9c003a00 0x80>; + reg-names = "rtc"; + clocks = <&clkc 0x12>; + resets = <&rstc 0x02>; + interrupt-parent = <&intc>; + interrupts = <163 IRQ_TYPE_EDGE_RISING>; + }; +... |