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-rw-r--r--dts/Bindings/usb/brcm,bdc.txt29
-rw-r--r--dts/Bindings/usb/brcm,bdc.yaml50
-rw-r--r--dts/Bindings/usb/dwc2.yaml13
-rw-r--r--dts/Bindings/usb/dwc3-xilinx.txt56
-rw-r--r--dts/Bindings/usb/dwc3-xilinx.yaml131
-rw-r--r--dts/Bindings/usb/intel,keembay-dwc3.yaml3
-rw-r--r--dts/Bindings/usb/nvidia,tegra-xudc.yaml13
-rw-r--r--dts/Bindings/usb/qcom,dwc3.yaml4
-rw-r--r--dts/Bindings/usb/snps,dwc3.yaml6
9 files changed, 220 insertions, 85 deletions
diff --git a/dts/Bindings/usb/brcm,bdc.txt b/dts/Bindings/usb/brcm,bdc.txt
deleted file mode 100644
index c9f52b97ce..0000000000
--- a/dts/Bindings/usb/brcm,bdc.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Broadcom USB Device Controller (BDC)
-====================================
-
-Required properties:
-
-- compatible: must be one of:
- "brcm,bdc-udc-v2"
- "brcm,bdc"
-- reg: the base register address and length
-- interrupts: the interrupt line for this controller
-
-Optional properties:
-
-On Broadcom STB platforms, these properties are required:
-
-- phys: phandle to one or two USB PHY blocks
- NOTE: Some SoC's have a single phy and some have
- USB 2.0 and USB 3.0 phys
-- clocks: phandle to the functional clock of this block
-
-Example:
-
- bdc@f0b02000 {
- compatible = "brcm,bdc-udc-v2";
- reg = <0xf0b02000 0xfc4>;
- interrupts = <0x0 0x60 0x0>;
- phys = <&usbphy_0 0x0>;
- clocks = <&sw_usbd>;
- };
diff --git a/dts/Bindings/usb/brcm,bdc.yaml b/dts/Bindings/usb/brcm,bdc.yaml
new file mode 100644
index 0000000000..9e561fee98
--- /dev/null
+++ b/dts/Bindings/usb/brcm,bdc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom USB Device Controller (BDC)
+
+maintainers:
+ - Al Cooper <alcooperx@gmail.com>
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bdc-udc-v2
+ - brcm,bdc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ minItems: 1
+ items:
+ - description: USB 2.0 or 3.0 PHY
+ - description: USB 3.0 PHY if there is a dedicated 2.0 PHY
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ usb@f0b02000 {
+ compatible = "brcm,bdc-udc-v2";
+ reg = <0xf0b02000 0xfc4>;
+ interrupts = <0x0 0x60 0x0>;
+ phys = <&usbphy_0 0x0>;
+ clocks = <&sw_usbd>;
+ };
diff --git a/dts/Bindings/usb/dwc2.yaml b/dts/Bindings/usb/dwc2.yaml
index 56a818478c..f00867ebc1 100644
--- a/dts/Bindings/usb/dwc2.yaml
+++ b/dts/Bindings/usb/dwc2.yaml
@@ -114,6 +114,8 @@ properties:
usb-role-switch: true
+ role-switch-default-mode: true
+
g-rx-fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: size of rx fifo size in gadget mode.
@@ -136,6 +138,17 @@ properties:
description: If present indicates that we need to reset the PHY when we
detect a wakeup. This is due to a hardware errata.
+ port:
+ description:
+ Any connector to the data bus of this controller should be modelled
+ using the OF graph bindings specified, if the "usb-role-switch"
+ property is used.
+ $ref: /schemas/graph.yaml#/properties/port
+
+dependencies:
+ port: [ usb-role-switch ]
+ role-switch-default-mode: [ usb-role-switch ]
+
required:
- compatible
- reg
diff --git a/dts/Bindings/usb/dwc3-xilinx.txt b/dts/Bindings/usb/dwc3-xilinx.txt
deleted file mode 100644
index 04813a46e5..0000000000
--- a/dts/Bindings/usb/dwc3-xilinx.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Xilinx SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
-- reg: Base address and length of the register control block
-- clocks: A list of phandles for the clocks listed in clock-names
-- clock-names: Should contain the following:
- "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
- operation and >= 60MHz for HS operation
-
- "ref_clk" Clock source to core during PHY power down
-- resets: A list of phandles for resets listed in reset-names
-- reset-names:
- "usb_crst" USB core reset
- "usb_hibrst" USB hibernation reset
- "usb_apbrst" USB APB reset
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Optional properties for snps,dwc3:
-- dma-coherent: Enable this flag if CCI is enabled in design. Adding this
- flag configures Global SoC bus Configuration Register and
- Xilinx USB 3.0 IP - USB coherency register to enable CCI.
-- interrupt-names: Should contain the following:
- "dwc_usb3" USB gadget mode interrupts
- "otg" USB OTG mode interrupts
- "hiber" USB hibernation interrupts
-
-Example device node:
-
- usb@0 {
- #address-cells = <0x2>;
- #size-cells = <0x1>;
- compatible = "xlnx,zynqmp-dwc3";
- reg = <0x0 0xff9d0000 0x0 0x100>;
- clock-names = "bus_clk", "ref_clk";
- clocks = <&clk125>, <&clk125>;
- resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
- <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
- <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
- reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
- ranges;
-
- dwc3@fe200000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe200000 0x40000>;
- interrupt-names = "dwc_usb3", "otg", "hiber";
- interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
- phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
- phy-names = "usb3-phy";
- dr_mode = "host";
- dma-coherent;
- };
- };
diff --git a/dts/Bindings/usb/dwc3-xilinx.yaml b/dts/Bindings/usb/dwc3-xilinx.yaml
new file mode 100644
index 0000000000..f77c16e203
--- /dev/null
+++ b/dts/Bindings/usb/dwc3-xilinx.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+ - Manish Narani <manish.narani@xilinx.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,zynqmp-dwc3
+ - xlnx,versal-dwc3
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ power-domains:
+ description: specifies a phandle to PM domain provider node
+ maxItems: 1
+
+ clocks:
+ description:
+ A list of phandle and clock-specifier pairs for the clocks
+ listed in clock-names.
+ items:
+ - description: Master/Core clock, has to be >= 125 MHz
+ for SS operation and >= 60MHz for HS operation.
+ - description: Clock source to core during PHY power down.
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: ref_clk
+
+ resets:
+ description:
+ A list of phandles for resets listed in reset-names.
+
+ items:
+ - description: USB core reset
+ - description: USB hibernation reset
+ - description: USB APB reset
+
+ reset-names:
+ items:
+ - const: usb_crst
+ - const: usb_hibrst
+ - const: usb_apbrst
+
+ phys:
+ minItems: 1
+ maxItems: 2
+
+ phy-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - usb2-phy
+ - usb3-phy
+
+# Required child node:
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: snps,dwc3.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - power-domains
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
+ #include <dt-bindings/power/xlnx-zynqmp-power.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+ #include <dt-bindings/phy/phy.h>
+ axi {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@0 {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ compatible = "xlnx,zynqmp-dwc3";
+ reg = <0x0 0xff9d0000 0x0 0x100>;
+ clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+ clock-names = "bus_clk", "ref_clk";
+ power-domains = <&zynqmp_firmware PD_USB_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ phy-names = "usb3-phy";
+ ranges;
+
+ usb@fe200000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe200000 0x0 0x40000>;
+ interrupt-names = "host", "otg";
+ interrupts = <0 65 4>, <0 69 4>;
+ dr_mode = "host";
+ dma-coherent;
+ };
+ };
+ };
diff --git a/dts/Bindings/usb/intel,keembay-dwc3.yaml b/dts/Bindings/usb/intel,keembay-dwc3.yaml
index 43b91ab620..d3511f48cd 100644
--- a/dts/Bindings/usb/intel,keembay-dwc3.yaml
+++ b/dts/Bindings/usb/intel,keembay-dwc3.yaml
@@ -13,6 +13,9 @@ properties:
compatible:
const: intel,keembay-dwc3
+ reg:
+ maxItems: 1
+
clocks:
maxItems: 4
diff --git a/dts/Bindings/usb/nvidia,tegra-xudc.yaml b/dts/Bindings/usb/nvidia,tegra-xudc.yaml
index 8428415896..a39c76b894 100644
--- a/dts/Bindings/usb/nvidia,tegra-xudc.yaml
+++ b/dts/Bindings/usb/nvidia,tegra-xudc.yaml
@@ -59,6 +59,19 @@ properties:
- const: fs_src
- const: hs_src
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ iommus:
+ maxItems: 1
+
power-domains:
items:
- description: XUSBB(device) power-domain
diff --git a/dts/Bindings/usb/qcom,dwc3.yaml b/dts/Bindings/usb/qcom,dwc3.yaml
index 2bdaba023c..2d23a4ff70 100644
--- a/dts/Bindings/usb/qcom,dwc3.yaml
+++ b/dts/Bindings/usb/qcom,dwc3.yaml
@@ -13,7 +13,9 @@ properties:
compatible:
items:
- enum:
+ - qcom,ipq4019-dwc3
- qcom,ipq6018-dwc3
+ - qcom,ipq8064-dwc3
- qcom,msm8996-dwc3
- qcom,msm8998-dwc3
- qcom,sc7180-dwc3
@@ -23,9 +25,11 @@ properties:
- qcom,sdx55-dwc3
- qcom,sm4250-dwc3
- qcom,sm6115-dwc3
+ - qcom,sm6350-dwc3
- qcom,sm8150-dwc3
- qcom,sm8250-dwc3
- qcom,sm8350-dwc3
+ - qcom,sm8450-dwc3
- const: qcom,dwc3
reg:
diff --git a/dts/Bindings/usb/snps,dwc3.yaml b/dts/Bindings/usb/snps,dwc3.yaml
index 25ac2c93dc..d29ffcd274 100644
--- a/dts/Bindings/usb/snps,dwc3.yaml
+++ b/dts/Bindings/usb/snps,dwc3.yaml
@@ -36,6 +36,9 @@ properties:
- const: synopsys,dwc3
deprecated: true
+ reg:
+ maxItems: 1
+
interrupts:
description:
It's either a single common DWC3 interrupt (dwc_usb3) or individual
@@ -65,6 +68,9 @@ properties:
- enum: [bus_early, ref, suspend]
- true
+ iommus:
+ maxItems: 1
+
usb-phy:
minItems: 1
items:
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 07:22:48 +0000